throbber
Trials@uspto.gov
`571-272-7822
`
`
`
`
`Paper 35
`Entered: February 10, 2014
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`v.
`
`XILINX, INC.
`Patent Owner
`____________
`
`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`JUSTIN T. ARBES, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`I. BACKGROUND
`
`Petitioner Intellectual Ventures Management, LLC (“IVM”) filed a
`
`Petition (Paper 6) (“Pet.”) seeking inter partes review of claims 1-13 of
`
`Patent 7,566,960 B1 (“the ’960 patent”) pursuant to 35 U.S.C. §§ 311-319.
`
`On February 12, 2013, the Board granted the Petition and instituted an inter
`
`partes review of all claims on four grounds of unpatentability (Paper 13)
`
`(“Dec. on Inst.”).
`
`Subsequent to institution, Patent Owner Xilinx, Inc. (“Xilinx”) filed a
`
`Patent Owner Response (Paper 17) (“PO Resp.”), and IVM filed a Reply
`
`(Paper 28) (“Pet. Reply”). Along with its Patent Owner Response, Xilinx
`
`filed a Motion to Amend. Paper 19. The motion was dismissed as defective,
`
`and Xilinx filed a Substitute Motion to Amend. See Papers 20, 22. After
`
`Xilinx filed its Substitute Motion, the Board entered a decision in Idle Free
`
`Systems, Inc. v. Bergstrom, Inc., IPR2012-00027, Paper 26 (June 11, 2013)
`
`(“Idle Free Decision”) regarding motions to amend. Xilinx requested, and
`
`received authorization from the Board, to file a second substitute motion to
`
`amend to comply with that decision. Paper 24. Xilinx then filed its Second
`
`Substitute Motion to Amend (Paper 26) (“Second Subst. Mot. to Amend”),
`
`proposing substitute claims 14-21 if the Board determines claim 1 to be
`
`unpatentable, and substitute claims 22-26 if the Board determines claim 9 to
`
`be unpatentable. IVM filed an Opposition to the Second Substitute Motion
`
`to Amend (Paper 29) (“Opp.”), and Xilinx filed a Reply (Paper 31) (“PO
`
`Reply”). The parties did not seek an oral hearing. Paper 34.
`
`The Board has jurisdiction under 35 U.S.C. § 6(c). This final written
`
`decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
`
`
`
`2
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`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`For the reasons that follow, we determine that IVM has shown by a
`
`preponderance of the evidence that claims 1-13 of the ’960 patent are
`
`unpatentable, and we deny Xilinx’s Second Substitute Motion to Amend.
`
`
`
`A. The’960 Patent
`
`The ’960 patent relates to an “interposer disposed inside an integrated
`
`circuit package between a die and the package, wherein the interposer
`
`provides bypass capacitance, signal redistribution functionality and/or signal
`
`termination structures close to the semiconductor die.” Ex. 1001, col. 1,
`
`ll. 5-9. The ’960 patent explains that it was known in the prior art to add a
`
`bypass capacitor to an integrated circuit (IC) device to reduce various power
`
`supply problems. Id. at col. 1, l. 49-col. 2, l. 30. According to the ’960
`
`patent, however, power supply problems often could not be anticipated
`
`during the initial design of an integrated circuit, and redesigning an
`
`integrated circuit to add bypass capacitance after it already has been
`
`designed and built “can be exceedingly expensive and slow.” Id. at col. 2,
`
`ll. 31-40. Also, the interconnections between the terminals on an integrated
`
`circuit and the signal traces on a printed circuit board (PCB) are sometimes
`
`incorrect, such that “[i]t would be desirable to be able to correct for this
`
`problem without having to redesign and refabricate the printed circuit.” Id.
`
`at col. 2, ll. 41-50. The ’960 patent describes adding an extremely thin
`
`“capacitive interposer (caposer),” which provides the necessary bypass
`
`capacitance, between an integrated circuit die and an inside surface of an
`
`integrated circuit package (connected to a printed circuit board). Id. at col.
`
`3, ll. 13-27; Fig. 1. The integrated circuit design then does not need to be
`
`
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`3
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`changed to solve power supply and interconnection problems that later arise.
`
`Id. at col. 3, ll. 41-44; col. 4, ll. 60-67.
`
`The ’960 patent describes various exemplary embodiments. Figure 10
`
`is reproduced below.
`
`
`
`Figure 10 depicts structure 1010 comprising (1) integrated circuit die 1011
`
`having micro-bumps 1013 on planar surface 1016, (2) ceramic integrated
`
`circuit package 1012 having landing pads 1014 on inside upper surface
`
`1017, and (3) through-hole caposer 10181 “disposed between inside upper
`
`surface 1017 of ceramic package 1012 and surface 1016 of die 1011.”
`
`Id. at col. 11, ll. 10-31. Integrated circuit package 1012 also has solder balls
`
`1023 on its bottom surface for coupling to a printed circuit board (not
`
`shown). Id. at col. 11, ll. 33-37.
`
`
`1 The ’960 patent explains that caposers may be either “through-hole” or
`“via.” Ex. 1001, col. 10, ll. 47-58. In a through-hole caposer, “an array of
`through holes passes through the caposer,” whereas in a via caposer,
`“conductive vias pass substantially orthogonally through the caposer.” Id.
`
`
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`4
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`
`Figure 24 depicts another embodiment and is reproduced below.
`
`
`
`As shown in Figure 24, caposer 1082 provides bypass capacitance and also
`
`“redistributes signals” through the use of multiple conductive layers 1101,
`
`1102, and 1106. Id. at col. 18, l. 47-col. 19, l. 3. Signal line 1109 is coupled
`
`to landing pad 1103, and third conductive layer 1106 of caposer 1082 is
`
`coupled to vias 1107 and 1108. Id. This creates an electrically conductive
`
`path between the micro-bump above landing pad 1103 and two different
`
`landing pads on integrated circuit package 1084: (1) the landing pad below
`
`pad 1104 and the corresponding micro-bump, and (2) the landing pad below
`
`micro-bump 1105. Id. Caposer 1082, therefore, “can be used to redistribute
`
`signal inputs and outputs from array positions on die 1083 to different
`
`positions on ceramic package 1084.” Id. at col. 18, l. 67-col. 19, l. 3.
`
`
`
`
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`5
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`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`B. Exemplary Claims
`
`Claims 1 and 9 of the ‘960 patent are the only independent claims:
`
`1. An assembly, comprising:
`
`an integrated circuit die having an array of micro-bumps
`disposed on a surface of the integrated circuit die in a first
`pattern;
`
`an integrated circuit package having an array of landing
`pads disposed on an inside surface of the integrated circuit
`package in a second pattern and an array of solder balls
`disposed on an outside surface of the integrated circuit package,
`wherein the first pattern and the second pattern are substantially
`identical patterns; and
`
`an interposing structure disposed inside the integrated
`circuit package between the integrated circuit die and the inside
`surface of the integrated circuit package, the interposer
`electrically coupling a first micro-bump in a first position in the
`array of micro-bumps to a first landing pad located opposite to
`the first position and to a second landing pad in the array of
`landing pads.
`
`9. An assembly, comprising:
`
`an integrated circuit die having an array of micro-bumps
`disposed on a surface of the integrated circuit die in a first
`pattern;
`
`an integrated circuit package having an array of landing
`pads disposed on an inside surface of the integrated circuit
`package in a second pattern and an array of solder balls
`disposed on an outside surface of the integrated circuit package,
`wherein the first pattern and the second pattern are substantially
`identical patterns; and
`
`means for electrically coupling a first micro-bump in a
`first position in the array of micro-bumps to a first landing pad
`disposed opposite the first position and to a second landing pad
`located in a different position in the array of landing pads, the
`means being disposed inside the integrated circuit package
`
`
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`6
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`

`Case IPR2012-00018
`Patent 7,566,960 B1
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`
`between the integrated circuit die and the inside surface of the
`integrated circuit package.
`
`
`
`C. Prior Art
`
`The pending grounds of unpatentability in this inter partes review are
`
`based on the following prior art:
`
`1. U.S. Patent No. 6,423,570 B1, issued July 23, 2002
`(Ex. 1008) (“Ma”);
`
`2. U.S. Patent No. 6,469,908 B2, issued Oct. 22, 2002
`(Ex. 1005) (“Patel”);
`
`3. U.S. Patent No. 6,730,540 B2, filed Apr. 18, 2002,
`issued May 4, 2004 (Ex. 1004) (“Siniaguine”); and
`
`4. U.S. Patent No. 6,970,362 B1, filed July 31, 2000,
`issued Nov. 29, 2005 (Ex. 1007) (“Chakravorty ’362”).
`
`
`
`D. Pending Grounds of Unpatentability
`
`This inter partes review involves the following grounds of
`
`unpatentability:
`
`References
`
`Basis
`
`Claims
`
`Chakravorty ’362 and
`Siniaguine
`
`Chakravorty ’362,
`Siniaguine, and Patel
`
`Siniaguine, Ma, and
`Chakravorty ’362
`
`Siniaguine, Ma,
`Chakravorty ’362, and
`Patel
`
`35 U.S.C. § 103(a) 1-5, 7-11, and 13
`
`35 U.S.C. § 103(a) 6 and 12
`
`35 U.S.C. § 103(a) 1-5, 7-11, and 13
`
`35 U.S.C. § 103(a) 6 and 12
`
`
`
`7
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`
`II. ANALYSIS
`
`A. Claim Interpretation
`
`Consistent with the statute and legislative history of the Leahy-Smith
`
`America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011) (“AIA”), the
`
`Board interprets claims using the “broadest reasonable construction in light
`
`of the specification of the patent in which [they] appear[].” 37 C.F.R.
`
`§ 42.100(b); see also Office Patent Trial Practice Guide, 77 Fed. Reg.
`
`48,756, 48,766 (Aug. 14, 2012). There is a “heavy presumption” that a
`
`claim term carries its ordinary and customary meaning. CCS Fitness, Inc. v.
`
`Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). However, a “claim
`
`term will not receive its ordinary meaning if the patentee acted as his own
`
`lexicographer and clearly set forth a definition of the disputed claim term in
`
`either the specification or prosecution history.” Id. “Although an inventor is
`
`indeed free to define the specific terms used to describe his or her invention,
`
`this must be done with reasonable clarity, deliberateness, and precision.” In
`
`re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Also, we must be careful
`
`not to read a particular embodiment appearing in the written description into
`
`the claim if the claim language is broader than the embodiment. See In re
`
`Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (“limitations are not to be
`
`read into the claims from the specification”).
`
`
`
`1. “Inside Surface” and “Inside the Integrated Circuit Package”
`
`Independent claims 1 and 9 recite an integrated circuit package having
`
`an array of landing pads disposed on an “inside surface” of the package and
`
`an array of solder balls disposed on an “outside surface” of the package.
`
`The claims further recite a structure (an “interposing structure” in claim 1
`
`
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`8
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`and a “means for electrically coupling” in claim 9) that is disposed “inside
`
`the integrated circuit package” between the inside surface of the package and
`
`an integrated circuit die.
`
`In the Decision on Institution, based on the arguments presented by
`
`IVM in its Petition and by Xilinx in its Preliminary Response, we interpreted
`
`the phrase “array of landing pads disposed on an inside surface of the
`
`integrated circuit package” in claims 1 and 9 to mean that the integrated
`
`circuit package has at least two surfaces (one facing in and one facing out)
`
`and that the array of landing pads is located on the surface facing in. Dec.
`
`on Inst. 8-11. We did not interpret the claim language as requiring the
`
`integrated circuit package to “completely surround” the integrated circuit die
`
`and landing pads, as Xilinx had argued in its Preliminary Response. Id.
`
`Rather, we concluded that, as ordinarily understood, “the fact that a structure
`
`has something on its ‘inside surface’ does not mean that the structure
`
`completely surrounds that thing (or any other thing).” Id. at 9. “For
`
`example, a box with its top off has an ‘inside surface’ and may have an
`
`object on that surface, even though it does not completely surround the
`
`object.” Id. IVM agrees with the Board’s interpretation; Xilinx does not.
`
`Xilinx first argues that the term “inside,” and the broader phrases in
`
`which it appears in the claims, are understood readily and do not require
`
`interpretation. PO Resp. 2-3. We conclude that interpretation is necessary
`
`under the circumstances, particularly because there is a disagreement
`
`between the parties as to whether the “inside” limitations require complete
`
`surrounding or encapsulation by the integrated circuit package, as explained
`
`below.
`
`
`
`9
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`

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`Case IPR2012-00018
`Patent 7,566,960 B1
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`
`Xilinx further proposes that, if interpretation of the “inside” claim
`
`limitations is deemed necessary, the term “inside” should be interpreted to
`
`mean “within,” and the term “inside surface” should be interpreted to mean a
`
`“surface within.” Id. at 2, 6-9. It is evident from Xilinx’s Patent Owner
`
`Response, however, that Xilinx imparts a further meaning to the word
`
`“within”—namely, that an object “within” another structure is one that is
`
`“completely surrounded by” or “encapsulated within” that structure. See id.
`
`at 4, 6-8 (arguing that the Specification of the ’960 patent “uses ‘inside’
`
`repeatedly to describe components encapsulated within, and completely
`
`surrounded by, the integrated circuit package,” and that the applicant
`
`“explained [during prosecution] that ‘inside’ means ‘completely surrounded’
`
`or ‘within’”). As such, Xilinx’s position appears to be that the interposing
`
`structure in claim 1 and the means for electrically coupling in claim 9, which
`
`are disposed “inside” the integrated circuit package, must be completely
`
`surrounded by or encapsulated within the integrated circuit package. We do
`
`not agree that this is the broadest reasonable interpretation of the claims in
`
`light of the Specification.
`
`
`
`Ordinary Meaning of “Inside”
`
`“Inside” is used in the claims both as an adjective (“inside surface”)
`
`and as a preposition (“inside the integrated circuit package”). One
`
`dictionary defines the adjective “inside” as “situated or being on or in the
`
`inside; interior; internal: an inside seat,” and the preposition “inside” as “on
`
`the inner side or part of; within: inside the circle; inside the envelope.”
`
`RANDOM HOUSE WEBSTER’S UNABRIDGED DICTIONARY 986 (2d ed. 2001)
`
`(Ex. 3002). Thus, Xilinx is correct that, at least in some circumstances,
`
`
`
`10
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`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`“inside” is synonymous with “within” (and also synonymous with “interior,”
`
`“inner,” and “internal”). See PO Resp. 6-9. Xilinx, however, does not point
`
`to evidence in the record indicating that “within,” as the term ordinarily is
`
`understood, means something that is completely surrounded by or
`
`encapsulated within another structure. Indeed, the dictionary examples
`
`above suggest just the opposite. A building with its door open may have an
`
`“inside seat,” and an unsealed envelope may have a letter “inside the
`
`envelope.” See Ex. 3002.
`
`This ordinary understanding is consistent with the box analogy
`
`discussed in the Decision on Institution. An object may be “inside” a box,
`
`situated on the box’s “inside surface,” even though the box has its top off,
`
`and, therefore, does not completely surround the object. See Dec. on Inst. 9.
`
`Xilinx contends that the box analogy leads to ambiguity because any surface
`
`may be considered “facing in” or “facing out” depending on the perspective
`
`from which it is viewed. PO Resp. 4-5. We do not agree. As IVM points
`
`out, whether a surface of the integrated circuit package faces in or out is
`
`viewed from the perspective of the overall package itself (which may have
`
`objects inside it). See Pet. Reply 5-6. IVM provides the following
`
`illustrative figure on page 6 of its Reply.
`
`IVM’s figure above shows a box with three sides (1, 2, and 3), each with a
`
`surface that faces in from the box (an “inside surface”) and a surface that
`
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`11
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`faces out from the box (an “outside surface”). Thus, the box analogy is not
`
`ambiguous and is consistent with the dictionary definitions of “inside” cited
`
`above. The analogy also is consistent with the language of the claims
`
`themselves, which recite the integrated circuit package having something
`
`disposed “inside” it, and objects on its “inside surface” and “outside
`
`surface,” but do not have any limitations that would imply a complete
`
`surrounding or encapsulation requirement. Thus, we do not agree with
`
`Xilinx that the ordinary and customary meaning of the “inside” claim
`
`limitations requires complete surrounding or encapsulation.
`
`
`
`Specification of the ’960 Patent
`
`Xilinx argues that the Specification of the ’960 patent uses the term
`
`“inside” to refer to “components encapsulated within, and completely
`
`surrounded by, the integrated circuit package.” PO Resp. 6-8. Xilinx cites
`
`the following statement in the Specification: “[v]arious embodiments are
`
`now disclosed in which caposers are disposed inside an IC package as
`
`opposed to being disposed outside the IC package between the package and
`
`a printed circuit board.” Id. at 7 (citing Ex. 1001, col. 10, ll. 47-50)
`
`(emphasis by Xilinx). We agree with Xilinx that the Specification
`
`distinguishes objects “inside” a structure from objects “outside” a structure.
`
`That does not mean necessarily, however, that an object must be completely
`
`surrounded by the structure to be inside the structure. Again, an object may
`
`be inside another structure and still be distinct from something outside that
`
`structure.
`
`Xilinx also relies on Figures 10 and 24 of the ’960 patent. Xilinx
`
`points to statements in the Specification that, in Figure 24, caposer 1082 is
`
`
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`12
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`Case IPR2012-00018
`Patent 7,566,960 B1
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`“inside” and “within” integrated circuit package 1084. Id. at 7-8 (citing Ex.
`
`1001, col. 17, ll. 45-48, col. 18, ll. 42-43). Figures 10 and 24, however, are
`
`merely exemplary embodiments of the invention. See, e.g., Ex. 1001, col. 6,
`
`ll. 13-15, 47-48; col. 11, ll. 9-11; col. 17, ll. 44-48. We do not see, and
`
`Xilinx does not point to, sufficient language in the Specification indicating
`
`that the patentee was defining the term “inside” to mean complete
`
`surrounding of one structure by another. For instance, although Figure 10
`
`depicts ceramic package 1012 surrounding caposer 1018, the written
`
`description of the ’960 patent does not state explicitly that the caposer in the
`
`disclosed embodiments is surrounded by or encapsulated within the
`
`integrated circuit package. We also note that Figure 24, unlike Figure 10,
`
`does not depict caposer 1082 as completely surrounded by integrated circuit
`
`package 1084. Rather, caposer 1082 is shown below die 1083 and above an
`
`inside surface of integrated circuit package 1084, with nothing shown on the
`
`sides of caposer 1082. Thus, we do not view Figures 10 and 24, and their
`
`corresponding descriptions, as supportive of Xilinx’s proposed
`
`interpretation.
`
`
`
`Prosecution History of the ’960 Patent
`
`Both parties rely on the prosecution history of the ’960 patent in their
`
`arguments regarding the proper interpretation of the “inside” claim
`
`limitations. See PO Resp. 8-9; Pet. Reply 2-4.
`
`Xilinx cites the following statement made by the applicant during
`
`prosecution of the ’960 patent:
`
`The Applicant refers the Examiner to FIG. 10, which
`shows a die 1011 inside a package 1012. The package 1012
`completely surrounds the die 1011, and hence the die 1011 is
`
`
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`Case IPR2012-00018
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`
`inside the package 1012. Further[,] Applicant’s specification
`states “[a]n integrated circuit die 1011 is mounted within an
`integrated circuit package 1012.” (Applicant’s specification,
`para. 0089).
`
`Ex. 2001 at 31; see PO Resp. 8. According to Xilinx, this indicates that the
`
`applicant meant “inside” to mean “completely surrounded” or “within.” PO
`
`Resp. 8-9.
`
`As explained in the Decision on Institution, we do not view the cited
`
`statement as an explicit definition of the claim language or an express and
`
`clear disclaimer of a broader definition. See Dec. on Inst. 10-11; In re Trans
`
`Texas Holdings Corp., 498 F.3d 1290, 1298 (Fed. Cir. 2007) (finding
`
`“nothing in the specification or the prosecution history that requires” a
`
`particular narrower interpretation proposed by a patent owner in a
`
`reexamination proceeding); In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir.
`
`2004) (“Absent claim language carrying a narrow meaning, the PTO should
`
`only limit the claim based on the specification or prosecution history when
`
`those sources expressly disclaim the broader definition.”). Also, the cited
`
`statement refers to the relationship between die 1011 and package 1012, and
`
`was made in response to a 35 U.S.C. § 112 rejection to show that the claims
`
`are “clear and definite.” Ex. 2001 at 31-32. According to the applicant, the
`
`statement specifically responds to the Examiner’s request that the applicant
`
`“explain the claimed structure as it relates to the drawings and
`
`specification.” Id.; see also id. at 39 (Office Action with 35 U.S.C. § 112
`
`rejection). The statement, therefore, describes related structure in the
`
`“drawings and specification.” See Ex. 2001 at 31-32, 39. It does not
`
`represent a limit on the claims or a disavowal of claim scope. As another
`
`example, the applicant vaguely explains that “one skilled in the art would
`
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`understand that a die and interposing structure can be positioned within or
`
`inside [a] surrounding structure, such as an integrated circuit package.” Id.
`
`at 31 (emphasis added). This statement of what “can be” included within the
`
`claim scope can be read as an attempt to maintain a reasonably broad scope
`
`that would encompass other (i.e., non-surrounding integrated circuit
`
`package) structures.
`
`Moreover, Xilinx’s argument that the prosecution history limits the
`
`claims is contradicted by another statement in the prosecution history.
`
`During prosecution, the Examiner rejected claim 1 and claim 12 (which
`
`became issued claim 9) as anticipated by Chakravorty ’362, citing Figure 2
`
`of Chakravorty ’362. Id. at 126-39. Figure 2 of Chakravorty ’362 is
`
`reproduced below.
`
`
`
`Figure 2 depicts solder bumps 58 on top of primary substrate 60. Ex. 1007,
`
`col. 4, ll. 64-66. During prosecution of the ’960 patent, the applicant argued
`
`the following as to Chakravorty ’362:
`
`The bumps (58) of the primary substrate in Chakravorty
`are disposed on the inside surface thereof, not the outside
`
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`
`surface. In particular, the Examiner cited the landing pads
`(61-67) on the primary substrate as being an “array of landing
`pads disposed on an inside surface of the integrated circuit
`package.” (Office Action, p. 4). Since these landing pads are
`coupled to the bumps (58), the bumps (58) of Chakravorty are
`on the inside of the substrate, not the outside.
`Ex. 2001 at 121 (emphasis added).2 Thus, the applicant took the position
`
`during prosecution that solder bumps 58 in Chakravorty ’362 are on an
`
`“inside surface” of, and “inside,” primary substrate 60, even though Figure 2
`
`does not depict primary substrate 60 as completely surrounding or
`
`encapsulating solder bumps 58. This position is in line with the other
`
`statements discussed above showing that the applicant did not intend to limit
`
`the claims during prosecution, and contrary to Xilinx’s current position that
`
`“inside” requires complete surrounding or encapsulation. See PO Resp. 8-9,
`
`10-11 (arguing that interposer 310 in Figure 3 of Chakravorty ’362 is not
`
`“inside” the primary substrate), 11-13 (making a similar argument as to
`
`Siniaguine).
`
`We are not persuaded by Xilinx’s arguments regarding the
`
`prosecution history of the ’960 patent. At best, the statements cited above
`
`are inconsistent, and do not indicate that the applicant was disclaiming a
`
`broader definition of the “inside” claim limitations as Xilinx contends.
`
`
`
`
`2 Notably, the applicant was able to overcome the Examiner’s rejection
`based on Chakravorty ’362 by arguing that the reference does not disclose
`an “array of solder balls disposed on an outside surface of the integrated
`circuit package.” See Ex. 2001 at 101-10, 121-22. IVM asserts, and Xilinx
`does not dispute, that this limitation is taught by Siniaguine. See Pet. 29-30,
`40-41.
`
`
`
`16
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`Other Evidence
`
`Xilinx also relies on the declaration of Dean Neikirk, Ph.D. (Exhibit
`
`2007) in support of its proposed interpretation. PO Resp. 9. Dr. Neikirk
`
`testifies that the purpose of an integrated circuit package is to “encapsulate
`
`and protect the fragile circuitry of an integrated circuit die” from potentially
`
`destructive substances and physical damage during manufacturing and use.
`
`Ex. 2007 ¶ 25. Therefore, according to Dr. Neikirk, a structure “inside” an
`
`integrated circuit package must be “within” the package. Id. We give Dr.
`
`Neikirk’s testimony little weight as to this point, as it is not supported by
`
`evidence in the record and is not tied to the actual language of the claims.
`
`See 37 C.F.R. § 42.65(a) (“Expert testimony that does not disclose the
`
`underlying facts or data on which the opinion is based is entitled to little or
`
`no weight.”). Further, the fact that there may be benefits to completely
`
`surrounding or encapsulating a structure in an integrated circuit package
`
`does not mean necessarily that the “inside” claim limitations should be
`
`interpreted to require such a structure. We see no reason why the claimed
`
`assemblies would require complete surrounding or encapsulation to function.
`
`
`
`Conclusion
`
`Applying the broadest reasonable interpretation of the claims in light
`
`of the Specification, we interpret “inside surface” to mean the surface of the
`
`integrated circuit package facing in from the package toward the integrated
`
`circuit die (as opposed to the “outside surface,” which is the surface of the
`
`package facing outward from the package away from the integrated circuit
`
`die). We also interpret “inside the integrated circuit package” to mean on
`
`the inner part of the integrated circuit package that faces in from the package
`
`
`
`17
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`toward the integrated circuit die. We do not interpret the claims as requiring
`
`the interposing structure (claim 1) or means for electrically coupling (claim
`
`9) to be completely surrounded by or encapsulated within the integrated
`
`circuit package.
`
`
`
`2. Other Terms
`
`In the Decision on Institution, we interpreted three other claim terms
`
`as follows:
`
`Term
`
`micro-bump (claims 1 and 9)
`
`Interpretation
`
`a small bump of electrically
`conductive material, such as
`solder
`
`means for electrically coupling a
`first micro-bump in a first
`position in the array of
`micro-bumps to a first landing
`pad disposed opposite the first
`position and to a second landing
`pad located in a different position
`in the array of landing pads (claim
`9)
`
`Function: “electrically coupling
`a first micro-bump in a first
`position in the array of
`micro-bumps to a first landing
`pad disposed opposite the first
`position and to a second landing
`pad located in a different
`position in the array of landing
`pads”
`
`Corresponding structure:
`caposer 1082
`
`
`
`18
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`
`Term
`
`Interpretation
`
`means for electrically coupling a
`first micro-bump in a first
`position in the array of
`micro-bumps to a first landing
`pad disposed opposite the first
`position and to a second landing
`pad located in a different position
`in the array of landing pads [and]
`for providing a bypass current to
`the integrated circuit die (claim
`10)
`
`Functions: “electrically
`coupling a first micro-bump in a
`first position in the array of
`micro-bumps to a first landing
`pad disposed opposite the first
`position and to a second landing
`pad located in a different
`position in the array of landing
`pads and providing a bypass
`current to the integrated circuit
`die”
`
`Corresponding structure:
`caposer 1082
`
`Dec. on Inst. 11-14. Neither party disputes these interpretations, and we
`
`apply them in this decision, for the reasons stated in the Decision on
`
`Institution.
`
`
`
`B. Claims 1-5, 7-11, and 13 are Unpatentable Over
`Chakravorty ’362 and Siniaguine
`
`With respect to the alleged obviousness of claims 1-5, 7-11, and 13
`
`over Chakravorty ’362 and Siniaguine, we have reviewed IVM’s Petition,
`
`Xilinx’s Patent Owner Response, and IVM’s Reply, as well as the evidence
`
`discussed in each of those papers. We are persuaded, by a preponderance of
`
`the evidence, that claims 1-5, 7-11, and 13 are unpatentable over
`
`Chakravorty ’362 and Siniaguine under 35 U.S.C. § 103(a). See Pet. 28-36;
`
`Ex. 1002 ¶¶ 65-81.
`
`Xilinx’s sole argument regarding the asserted ground is that
`
`Chakravorty ’362 does not teach “an interposing structure disposed inside
`
`
`
`19
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`the integrated circuit package,” as recited in independent claim 1.3 PO Resp.
`
`9-11. For the reasons explained below, Xilinx’s argument is not persuasive.
`
`Chakravorty ’362 is directed to an “electronic assembly that includes
`
`an interposer having one or more embedded capacitors to reduce switching
`
`noise in a high-speed integrated circuit, and to manufacturing methods
`
`related thereto.” Ex. 1007, col. 1, ll. 17-21. Figure 3 of Chakravorty ’362 is
`
`reproduced below.
`
`
`
`Figure 3 depicts an assembly comprising integrated circuit (IC) die 300,
`
`solder balls 301, lands 302, interposer 310 (with embedded capacitors),
`
`lands 312, solder balls 311, and primary substrate 320. Id. at col. 5,
`
`ll. 30-60. IVM identifies IC die 300 as the claimed “integrated circuit die,”
`
`primary substrate 320 as the claimed “integrated circuit package,” and
`
`3 Although Xilinx does not address specifically the language of the other
`independent claim, claim 9, which recites a “means for electrically coupling
`. . . disposed inside the integrated circuit package,” Xilinx’s argument
`regarding the “inside” limitation presumably applies to both claims. See
`PO Resp. 9-12.
`
`
`
`20
`
`

`

`Case IPR2012-00018
`Patent 7,566,960 B1
`
`interposer 310 as the claimed “interposing structure” of claim 1 and “means
`
`for electrically coupling” of claim 9. Pet. 28-30, 33-35. According to IVM,
`
`interposer 310 is disposed “inside” primary substrate 320 between the inside
`
`surface of the substrate and IC die 300.4 Id; see Ex. 1002 ¶ 70.
`
`Xilinx argues that interposer 310 is “outside,” not “inside,” primary
`
`substrate 320. PO Resp. 9-10. As explained above, however, “inside
`
`surface” means the surface of the integrated circuit package facing in from
`
`the package toward the integrated circuit die, and “inside the integrated
`
`circuit package” means on the inner part of the integrated circuit package
`
`that faces in from the package toward the integrated circuit die. See supra
`
`Section II.A.1. Although interposer 310 is not shown in Figure 3 as
`
`completely surrounded by or encapsulated within primary substrate 320,
`
`such surrounding or encapsulation is not required by the claims. See id. The
`
`inside surface of primary substrate 320 is the top of the substrate shown in
`
`Figure 3, which has signal terminals/bumps immediately below solder balls
`
`311. See Ex. 1007, col. 4, ll. 15-21; col. 5, ll. 20-25; Figs. 2-3. This surface
`
`faces in from primary substrate 320 toward IC die 300, in contrast to the
`
`bottom of the substrate shown in Figure 3, which faces outward away from
`
`IC die 300. Interposer 310 is disposed between the inside surface of primary
`
`substrate 320 and IC die 300. The area in which interposer 310 is located is
`
`the inner part of primary substrate 320. We also note that Figure 3 depicts
`
`

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