Trials@uspto.gov
`571-272-7822
`
`
`Paper 33
`Entered: February 10, 2014
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`v.
`
`XILINX, INC.
`Patent Owner
`____________
`
`Case IPR2012-00019
`Patent 8,062,968 B1
`
`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`JUSTIN T. ARBES, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`571-272-7822
`
`
`Paper 33
`Entered: February 10, 2014
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`v.
`
`XILINX, INC.
`Patent Owner
`____________
`
`Case IPR2012-00019
`Patent 8,062,968 B1
`
`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`JUSTIN T. ARBES, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`Case IPR2012-00019
`Patent 8,062,968 B1
`
`
`I. BACKGROUND
`
`Petitioner Intellectual Ventures Management, LLC (“IVM”) filed a
`
`Petition (Paper 5) (“Pet.”) seeking inter partes review of claims 1-15 of
`
`Patent 8,062,968 B1 (“the ’968 patent”) pursuant to 35 U.S.C. §§ 311-319.
`
`On February 12, 2013, the Board granted the Petition and instituted an inter
`
`partes review of all claims on six grounds of unpatentability (Paper 13)
`
`(“Dec. on Inst.”).
`
`Subsequent to institution, Patent Owner Xilinx, Inc. (“Xilinx”) filed a
`
`Patent Owner Response (Paper 17) (“PO Resp.”), and IVM filed a Reply
`
`(Paper 26) (“Pet. Reply”). Along with its Patent Owner Response, Xilinx
`
`filed a Motion to Amend. Paper 19. The motion was dismissed as defective,
`
`and Xilinx filed a Substitute Motion to Amend. See Papers 20, 21. After
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`Xilinx filed its Substitute Motion, the Board entered a decision in Idle Free
`
`Systems, Inc. v. Bergstrom, Inc., IPR2012-00027, Paper 26 (June 11, 2013)
`
`(“Idle Free Decision”) regarding motions to amend. Xilinx requested, and
`
`received authorization from the Board, to file a second substitute motion to
`
`amend to comply with that decision. Paper 23. Xilinx then filed its Second
`
`Substitute Motion to Amend (Paper 24) (“Second Subst. Mot. to Amend”),
`
`proposing substitute claims 16-23 if the Board determines claim 1 to be
`
`unpatentable, and substitute claims 24-30 if the Board determines claim 9 to
`
`be unpatentable. IVM filed an Opposition to the Second Substitute Motion
`
`to Amend (Paper 27) (“Opp.”), and Xilinx filed a Reply (Paper 29) (“PO
`
`Reply”). The parties did not seek an oral hearing. Paper 32.
`
`The Board has jurisdiction under 35 U.S.C. § 6(c). This final written
`
`decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
`
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`2
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`Case IPR2012-00019
`Patent 8,062,968 B1
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`For the reasons that follow, we determine that IVM has shown by a
`
`preponderance of the evidence that claims 1-15 of the ’968 patent are
`
`unpatentable, and we deny Xilinx’s Second Substitute Motion to Amend.
`
`
`
`A. The’968 Patent
`
`The ’968 patent relates to an “interposer disposed inside an integrated
`
`circuit package between a die and the package, wherein the interposer
`
`provides bypass capacitance, signal redistribution functionality and/or signal
`
`termination structures close to the semiconductor die.” Ex. 1001, col. 1,
`
`ll. 6-10. The ’968 patent explains that it was known in the prior art to add a
`
`bypass capacitor to an integrated circuit (IC) device to reduce various power
`
`supply problems. Id. at col. 1, l. 50-col. 2, l. 31. According to the ’968
`
`patent, however, power supply problems often could not be anticipated
`
`during the initial design of an integrated circuit, and redesigning an
`
`integrated circuit to add bypass capacitance after it already has been
`
`designed and built “can be exceedingly expensive and slow.” Id. at col. 2,
`
`ll. 32-41. Also, the interconnections between the terminals on an integrated
`
`circuit and the signal traces on a printed circuit board (PCB) are sometimes
`
`incorrect, such that “[i]t would be desirable to be able to correct for this
`
`problem without having to redesign and refabricate the printed circuit.” Id.
`
`at col. 2, ll. 42-51. The ’968 patent describes adding an extremely thin
`
`“capacitive interposer (caposer),” which provides the necessary bypass
`
`capacitance, between an integrated circuit die and an inside surface of an
`
`integrated circuit package (connected to a printed circuit board). Id. at col.
`
`3, ll. 14-28; Fig. 1. The integrated circuit design then does not need to be
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`3
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`Case IPR2012-00019
`Patent 8,062,968 B1
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`changed to solve power supply and interconnection problems that later arise.
`
`Id. at col. 3, ll. 41-44; col. 4, ll. 60-67.
`
`The ’968 patent describes various exemplary embodiments. Figure 10
`
`is reproduced below.
`
`
`
`Figure 10 depicts structure 1010 comprising (1) integrated circuit die 1011
`
`having micro-bumps 1013 on planar surface 1016, (2) ceramic integrated
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`circuit package 1012 having landing pads 1014 on inside upper surface
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`1017, and (3) through-hole caposer 10181 “disposed between inside upper
`
`surface 1017 of ceramic package 1012 and surface 1016 of die 1011.”
`
`Id. at col. 11, ll. 10-33. Integrated circuit package 1012 also has solder balls
`
`1023 on its bottom surface for coupling to a printed circuit board (not
`
`shown). Id. at col. 11, ll. 34-39.
`
`
`1 The ’968 patent explains that caposers may be either “through-hole” or
`“via.” Ex. 1001, col. 10, ll. 47-58. In a through-hole caposer, “an array of
`through-holes passes through the caposer,” whereas in a via caposer,
`“conductive vias pass substantially orthogonally through the caposer.” Id.
`
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`4
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`Patent 8,062,968 B1
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`Figure 24 depicts another embodiment and is reproduced below.
`
`
`
`As shown in Figure 24, caposer 1082 provides bypass capacitance and also
`
`“redistributes signals” through the use of multiple conductive layers 1101,
`
`1102, and 1106. Id. at col. 18, l. 47-col. 19, l. 3. Signal line 1109 is coupled
`
`to landing pad 1103, and third conductive layer 1106 of caposer 1082 is
`
`coupled to vias 1107 and 1108. Id. This creates an electrically conductive
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`path between the micro-bump above landing pad 1103 and two different
`
`landing pads on integrated circuit package 1084: (1) the landing pad below
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`pad 1104 and the corresponding micro-bump, and (2) the landing pad below
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`micro-bump 1105. Id. Caposer 1082, therefore, “can be used to redistribute
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`signal inputs and outputs from array positions on die 1083 to different
`
`positions on ceramic package 1084.” Id. at col. 18, l. 67-col. 19, l. 3.
`
`
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`B. Exemplary Claims
`
`Claims 1 and 9 of the ‘968 patent are the only independent claims:
`
`1. A method of conducting a signal between a
`micro-bump on a surface of an integrated circuit die and a
`landing pad on an inside surface of an integrated circuit
`package, the method comprising:
`
`disposing an interposing structure between the integrated
`circuit die and the inside surface of the integrated circuit
`package, wherein a plurality of micro-bumps in an array on the
`surface of the integrated circuit die align with a plurality of
`landing pads on the inside surface of the integrated circuit
`package; and
`
`re-routing, by way of a conductor disposed in the
`interposing structure, a signal present on the micro-bump at one
`position of the array to a different position of the array.
`
`9. A method to manufacture an assembly, comprising:
`
`disposing an array of landing pads on an inside surface of
`an integrated circuit package in a first pattern;
`
`fabricating an interposing structure above the array of
`landing pads on the inside surface of the integrated circuit
`package;
`
`fabricating an integrated circuit die above the interposing
`structure;
`
`disposing an array of micro-bumps on a surface of the
`integrated circuit die in a second pattern,
`
`coupling a particular one of the array of micro-bumps to
`a particular one of the array of landing pads by way of the
`interposing structure, wherein the plurality of micro-bumps in
`the array on the surface of the integrated circuit die align with
`the array of landing pads on the inside surface of the integrated
`circuit package;
`
`re-routing a signal present on a micro-bump at one
`position of the array of micro-bumps to a different position of
`the array of micro-bumps by way of a conductor disposed in the
`interposing structure; and
`
`
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`applying solder balls on the bottom surface of the
`integrated circuit package.
`
`
`
`C. Prior Art
`
`The pending grounds of unpatentability in this inter partes review are
`
`based on the following prior art:
`
`1. U.S. Patent No. 6,469,908 B2, issued Oct. 22, 2002
`(Ex. 1004) (“Patel”);
`
`2. U.S. Patent No. 6,730,540 B2, filed Apr. 18, 2002,
`issued May 4, 2004 (Ex. 1003) (“Siniaguine”); and
`
`3. U.S. Patent No. 6,970,362 B1, filed July 31, 2000,
`issued Nov. 29, 2005 (Ex. 1009) (“Chakravorty ’362”).
`
`
`
`D. Pending Grounds of Unpatentability
`
`The instant inter partes review involves the following grounds of
`
`unpatentability:
`
`Reference(s)
`
`Chakravorty ’362
`
`Chakravorty ’362 and
`Siniaguine
`
`Chakravorty ’362 and
`Patel
`
`Basis
`35 U.S.C. § 102(e)2
`
`Claim(s)
`
`1, 2, 4, 5, 7, and 8
`
`35 U.S.C. § 103(a)
`
`3, 9-12, 14, and 15
`
`35 U.S.C. § 103(a)
`
`6
`
`
`2 The Decision on Institution incorrectly cited 35 U.S.C. § 102(a) as the
`basis on which Chakravorty ’362 and Siniaguine qualify as prior art. See
`Dec. on Inst. 23. Both references are prior art at least under 35 U.S.C.
`§ 102(e), as they are patents granted on applications filed prior to the
`invention by the applicant of the ’968 patent. Xilinx does not dispute that
`Chakravorty ’362 and Siniaguine are prior art to the challenged claims of the
`’968 patent.
`
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`Reference(s)
`
`Basis
`
`Claim(s)
`
`Chakravorty ’362,
`Siniaguine, and Patel
`
`35 U.S.C. § 103(a)
`
`13
`
`Siniaguine
`
`35 U.S.C. § 102(e)
`
`1-5, 7-12, 14, and
`15
`
`Siniaguine and Patel
`
`35 U.S.C. § 103(a)
`
`6 and 13
`
`
`
`II. ANALYSIS
`
`A. Claim Interpretation
`
`Consistent with the statute and legislative history of the Leahy-Smith
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`America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011) (“AIA”), the
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`Board interprets claims using the “broadest reasonable construction in light
`
`of the specification of the patent in which [they] appear[].” 37 C.F.R.
`
`§ 42.100(b); see also Office Patent Trial Practice Guide, 77 Fed. Reg.
`
`48,756, 48,766 (Aug. 14, 2012). There is a “heavy presumption” that a
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`claim term carries its ordinary and customary meaning. CCS Fitness, Inc. v.
`
`Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). However, a “claim
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`term will not receive its ordinary meaning if the patentee acted as his own
`
`lexicographer and clearly set forth a definition of the disputed claim term in
`
`either the specification or prosecution history.” Id. “Although an inventor is
`
`indeed free to define the specific terms used to describe his or her invention,
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`this must be done with reasonable clarity, deliberateness, and precision.” In
`
`re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Also, we must be careful
`
`not to read a particular embodiment appearing in the written description into
`
`the claim if the claim language is broader than the embodiment. See In re
`
`Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993) (“limitations are not to be
`
`read into the claims from the specification”).
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`1. “Inside Surface”
`
`Independent claim 1 recites a “method of conducting a signal between
`
`a micro-bump on a surface of an integrated circuit die and a landing pad on
`
`an inside surface of an integrated circuit package,” comprising “disposing an
`
`interposing structure between the integrated circuit die and the inside surface
`
`of the integrated circuit package, wherein a plurality of micro-bumps in an
`
`array on the surface of the integrated circuit die align with a plurality of
`
`landing pads on the inside surface of the integrated circuit package”
`
`(emphasis added). Independent claim 9 similarly recites “disposing an array
`
`of landing pads on an inside surface of an integrated circuit package in a
`
`first pattern,” “fabricating an interposing structure above the array of landing
`
`pads on the inside surface of the integrated circuit package,” and
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`“fabricating an integrated circuit die above the interposing structure,”
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`wherein “the plurality of micro-bumps in the array on the surface of the
`
`integrated circuit die align with the array of landing pads on the inside
`
`surface of the integrated circuit package” (emphasis added).
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`In the Decision on Institution, based on the arguments presented by
`
`IVM in its Petition and by Xilinx in its Preliminary Response, we interpreted
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`the phrase “landing pads on the inside surface of the integrated circuit
`
`package” in claims 1 and 9 to mean that the integrated circuit package has at
`
`least two surfaces (one facing in and one facing out) and that the landing
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`pads are located on the surface facing in. Dec. on Inst. 8-12. We did not
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`interpret the claim language as requiring the integrated circuit package to
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`“completely surround” the integrated circuit die and landing pads, as Xilinx
`
`had argued in its Preliminary Response. Id. Rather, we concluded that, as
`
`ordinarily understood, “the fact that a structure has something on its ‘inside
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`surface’ does not mean that the structure completely surrounds that thing (or
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`any other thing).” Id. at 9. “For example, a box with its top off has an
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`‘inside surface’ and may have an object on that surface, even though it does
`
`not completely surround the object.” Id. at 9-10. IVM agrees with the
`
`Board’s interpretation; Xilinx does not.
`
`Xilinx first argues that the term “inside,” and the broader phrases in
`
`which it appears in the claims, are understood readily and do not require
`
`interpretation. PO Resp. 2-3. We conclude that interpretation is necessary
`
`under the circumstances, particularly because there is a disagreement
`
`between the parties as to whether the “inside surface” limitations require
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`complete surrounding or encapsulation by the integrated circuit package, as
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`explained below.
`
`Xilinx further proposes that, if interpretation of the “inside surface”
`
`claim limitations is deemed necessary, the term “inside” should be
`
`interpreted to mean “within,” and the term “inside surface” should be
`
`interpreted to mean a “surface within.” Id. at 2, 6-9. It is evident from
`
`Xilinx’s Patent Owner Response, however, that Xilinx imparts a further
`
`meaning to the word “within”—namely, that an object “within” another
`
`structure is one that is “completely surrounded by” or “encapsulated within”
`
`that structure. See id. at 4, 6-8 (arguing that the Specification of the ’968
`
`patent “uses ‘inside’ repeatedly to describe components encapsulated within,
`
`and completely surrounded by, the integrated circuit package,” and that the
`
`applicant “explained [during prosecution of the parent of the ’968 patent]
`
`that ‘inside’ means ‘completely surrounded’ or ‘within’”). As such, Xilinx’s
`
`position appears to be that the interposing structure in claims 1 and 9 must
`
`be completely surrounded by or encapsulated within the integrated circuit
`
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`Patent 8,062,968 B1
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`package. We do not agree that this is the broadest reasonable interpretation
`
`of the claims in light of the Specification.
`
`
`
`Ordinary Meaning of “Inside”
`
`“Inside” is used in the claims as an adjective (“inside surface”). One
`
`dictionary defines the adjective “inside” as “situated or being on or in the
`
`inside; interior; internal: an inside seat.” RANDOM HOUSE WEBSTER’S
`
`UNABRIDGED DICTIONARY 986 (2d ed. 2001) (Ex. 3002). Thus, at least in
`
`some circumstances, “inside” is synonymous with “interior” and “internal.”
`
`Xilinx, however, does not point to evidence in the record indicating that
`
`“inside,” as the term ordinarily is understood, means something that is
`
`completely surrounded by or encapsulated within another structure. Indeed,
`
`the dictionary example above suggests just the opposite. A building with its
`
`door open may have an “inside seat,” for example. See Ex. 3002.
`
`This ordinary understanding is consistent with the box analogy
`
`discussed in the Decision on Institution. An object may be “inside” a box,
`
`situated on the box’s “inside surface,” even though the box has its top off,
`
`and, therefore, does not completely surround the object. See Dec. on Inst.
`
`9-10. Xilinx contends that the box analogy leads to ambiguity because any
`
`surface may be considered “facing in” or “facing out” depending on the
`
`perspective from which it is viewed. PO Resp. 4-5. We do not agree. As
`
`IVM points out, whether a surface of the integrated circuit package faces in
`
`or out is viewed from the perspective of the overall package itself (which
`
`may have objects inside it). See Pet. Reply 8-9.
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`IVM provides the following illustrative figure on page 9 of its Reply.
`
`
`
`IVM’s figure above shows a box with three sides (1, 2, and 3), each with a
`
`surface that faces in from the box (an “inside surface”) and a surface that
`
`faces out from the box (an “outside surface”). Thus, the box analogy is not
`
`ambiguous and is consistent with the dictionary definitions of “inside” cited
`
`above. The analogy also is consistent with the language of the claims
`
`themselves, which recite the integrated circuit package having objects on its
`
`“inside surface,” and objects between its “inside surface” and an integrated
`
`circuit die, but do not have any limitations that would imply a complete
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`surrounding or encapsulation requirement. Thus, we do not agree with
`
`Xilinx that the ordinary and customary meaning of the “inside surface”
`
`claim limitations requires complete surrounding or encapsulation.
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`
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`Specification of the ’968 Patent
`
`Xilinx argues that the Specification of the ’968 patent uses the term
`
`“inside” to refer to “components encapsulated within, and completely
`
`surrounded by, the integrated circuit package.” PO Resp. 6-8. Xilinx cites
`
`the following statement in the Specification: “[v]arious embodiments are
`
`now disclosed in which caposers are disposed inside an IC package as
`
`opposed to being disposed outside the IC package between the package and
`
`a printed circuit board.” Id. at 7 (citing Ex. 1001, col. 10, ll. 47-50)
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`(emphasis by Xilinx). We agree with Xilinx that the Specification
`
`distinguishes objects “inside” a structure from objects “outside” a structure.
`
`That does not mean necessarily, however, that an object must be completely
`
`surrounded by the structure to be on an “inside surface” of the structure.
`
`Again, an object may be inside another structure and still be distinct from
`
`something outside that structure.
`
`Xilinx also relies on Figures 10 and 24 of the ’968 patent. Xilinx
`
`points to statements in the Specification that, in Figure 24, caposer 1082 is
`
`“inside” and “within” integrated circuit package 1084. Id. at 7-8 (citing Ex.
`
`1001, col. 17, ll. 45-48, col. 18, ll. 42-43). Figures 10 and 24, however, are
`
`merely exemplary embodiments of the invention. See, e.g., Ex. 1001, col. 6,
`
`ll. 14-16, 47-48; col. 11, ll. 9-11; col. 17, ll. 44-48. We do not see, and
`
`Xilinx does not point to, sufficient language in the Specification indicating
`
`that the patentee was defining the term “inside surface” to mean complete
`
`surrounding of one structure by another. For instance, although Figure 10
`
`depicts ceramic package 1012 surrounding caposer 1018, the written
`
`description of the ’968 patent does not state explicitly that the caposer in the
`
`disclosed embodiments is surrounded by or encapsulated within the
`
`integrated circuit package. We also note that Figure 24, unlike Figure 10,
`
`does not depict caposer 1082 as completely surrounded by integrated circuit
`
`package 1084. Rather, caposer 1082 is shown below die 1083 and above an
`
`inside surface of integrated circuit package 1084, with nothing shown on the
`
`sides of caposer 1082. Thus, we do not view Figures 10 and 24, and their
`
`corresponding descriptions, as supportive of Xilinx’s proposed
`
`interpretation.
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`Prosecution History of the ’960 Patent
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`Both parties rely on the prosecution history of U.S. Patent No.
`
`7,566,960 B1 (“the ’960 patent”),3 the parent of the ’968 patent, in their
`
`arguments regarding the proper interpretation of the “inside surface” claim
`
`limitations. See PO Resp. 8-9; Pet. Reply 1-3.
`
`Xilinx cites the following statement made by the applicant during
`
`prosecution of the ’960 patent:
`
`The Applicant refers the Examiner to FIG. 10, which
`shows a die 1011 inside a package 1012. The package 1012
`completely surrounds the die 1011, and hence the die 1011 is
`inside the package 1012. Further[,] Applicant’s specification
`states “[a]n integrated circuit die 1011 is mounted within an
`integrated circuit package 1012.” (Applicant’s specification,
`para. 0089).
`
`Ex. 2001 at 31; see PO Resp. 8. According to Xilinx, this indicates that the
`
`applicant meant “inside” to mean “completely surrounded” or “within.” PO
`
`Resp. 8-9.
`
`As explained in the Decision on Institution, we do not view the cited
`
`statement as an explicit definition of the claim language used in the ’968
`
`patent or an express and clear disclaimer of a broader definition. See Dec.
`
`on Inst. 10-12; In re Trans Texas Holdings Corp., 498 F.3d 1290, 1298 (Fed.
`
`Cir. 2007) (finding “nothing in the specification or the prosecution history
`
`that requires” a particular narrower interpretation proposed by a patent
`
`owner in a reexamination proceeding); In re Bigio, 381 F.3d 1320, 1325
`
`(Fed. Cir. 2004) (“Absent claim language carrying a narrow meaning, the
`
`PTO should only limit the claim based on the specification or prosecution
`
`history when those sources expressly disclaim the broader definition.”).
`
`
`3 The ’960 patent is the subject of related Case IPR2012-00018.
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`Also, the cited statement refers to the relationship between die 1011 and
`
`package 1012, and was made in response to a 35 U.S.C. § 112 rejection to
`
`show that the claims are “clear and definite.” Ex. 2001 at 31-32. According
`
`to the applicant, the statement specifically responds to the Examiner’s
`
`request that the applicant “explain the claimed structure as it relates to the
`
`drawings and specification.” Id.; see also id. at 39 (Office Action with 35
`
`U.S.C. § 112 rejection). The statement, therefore, describes related structure
`
`in the “drawings and specification.” See Ex. 2001 at 31-32, 39. It does not
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`represent a limit on the claims or a disavowal of claim scope. As another
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`example, the applicant vaguely explains that “one skilled in the art would
`
`understand that a die and interposing structure can be positioned within or
`
`inside [a] surrounding structure, such as an integrated circuit package.” Id.
`
`at 31 (emphasis added). This statement of what “can be” included within the
`
`claim scope can be read as an attempt to maintain a reasonably broad scope
`
`that would encompass other (i.e., non-surrounding integrated circuit
`
`package) structures.
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`Moreover, Xilinx’s argument that the prosecution history limits the
`
`claims is contradicted by another statement in the prosecution history of the
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`parent patent. During prosecution of the ’960 patent, the Examiner rejected
`
`claim 1 and claim 12 (which became issued claim 9 in the ’960 patent) as
`
`anticipated by Chakravorty ’362, citing Figure 2 of Chakravorty ’362. Id. at
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`126-39.
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`15
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`Case IPR2012-00019
`Patent 8,062,968 B1
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`Figure 2 of Chakravorty ’362 is reproduced below.
`
`Figure 2 depicts solder bumps 58 on top of primary substrate 60. Ex. 1009,
`
`col. 4, ll. 64-66. During prosecution of the ’960 patent, the applicant argued
`
`the following as to Chakravorty ’362:
`
`
`
`The bumps (58) of the primary substrate in Chakravorty
`are disposed on the inside surface thereof, not the outside
`surface. In particular, the Examiner cited the landing pads
`(61-67) on the primary substrate as being an “array of landing
`pads disposed on an inside surface of the integrated circuit
`package.” (Office Action, p. 4). Since these landing pads are
`coupled to the bumps (58), the bumps (58) of Chakravorty are
`on the inside of the substrate, not the outside.
`
`Ex. 2001 at 121 (emphasis added). Thus, the applicant took the position
`
`during prosecution of the ’960 patent that solder bumps 58 in
`
`Chakravorty ’362 are on an “inside surface” of, and “inside,” primary
`
`substrate 60, even though Figure 2 does not depict primary substrate 60 as
`
`completely surrounding or encapsulating solder bumps 58. This position is
`
`in line with the other statements discussed above showing that the applicant
`
`did not intend to limit the claims during prosecution, and contrary to
`
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`16
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`Case IPR2012-00019
`Patent 8,062,968 B1
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`Xilinx’s current position that “inside surface” requires complete surrounding
`
`or encapsulation. See PO Resp. 11-12 (arguing that Chakravorty ’362 does
`
`not have an interposing structure disposed between an integrated circuit die
`
`and “inside surface” of an integrated circuit package), 9-10 (making a
`
`similar argument as to Siniaguine), 12-15 (arguing that Chakravorty ’362
`
`and Siniaguine do not teach fabricating an interposing structure above an
`
`array of landing pads on an “inside surface” of an integrated circuit
`
`package).
`
`We are not persuaded by Xilinx’s arguments regarding the
`
`prosecution history of the ’960 patent. At best, the statements cited above
`
`are inconsistent, and do not indicate that the applicant was disclaiming a
`
`broader definition of the “inside surface” claim limitations in the claims of
`
`the ’968 patent as Xilinx contends.
`
`
`
`Other Evidence
`
`Xilinx also relies on the declaration of Dean Neikirk, Ph.D. (Exhibit
`
`2007) in support of its proposed interpretation. PO Resp. 9. Dr. Neikirk
`
`testifies that the purpose of an integrated circuit package is to “encapsulate
`
`and protect the fragile circuitry of an integrated circuit die” from potentially
`
`destructive substances and physical damage during manufacturing and use.
`
`Ex. 2007 ¶ 25. Therefore, according to Dr. Neikirk, a structure “inside” an
`
`integrated circuit package must be “within” the package. Id. We give
`
`Dr. Neikirk’s testimony little weight as to this point, as it is not supported by
`
`evidence in the record and is not tied to the actual language of the claims.
`
`See 37 C.F.R. § 42.65(a) (“Expert testimony that does not disclose the
`
`underlying facts or data on which the opinion is based is entitled to little or
`
`
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`17
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`Case IPR2012-00019
`Patent 8,062,968 B1
`
`no weight.”). Further, the fact that there may be benefits to completely
`
`surrounding or encapsulating a structure in an integrated circuit package
`
`does not mean necessarily that the “inside surface” claim limitations should
`
`be interpreted to require such a structure. We see no reason why the claimed
`
`methods would require complete surrounding or encapsulation to be
`
`performed.
`
`
`
`Conclusion
`
`Applying the broadest reasonable interpretation of the claims in light
`
`of the Specification, we interpret “inside surface” to mean the surface of the
`
`integrated circuit package facing in from the package toward the integrated
`
`circuit die (as opposed to the outside surface, which is the surface of the
`
`package facing outward from the package away from the integrated circuit
`
`die). We do not interpret the claims as requiring the interposing structure to
`
`be completely surrounded by or encapsulated within the integrated circuit
`
`package.
`
`
`
`2. “Micro-Bump”
`
`In the Decision on Institution, we also interpreted “micro-bump” in
`
`claims 1 and 9 to mean a small bump of electrically conductive material,
`
`such as solder. Dec. on Inst. 12-13. Neither party disputes this
`
`interpretation, and we apply it in this decision, for the reasons stated in the
`
`Decision on Institution.
`
`
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`18
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`Patent 8,062,968 B1
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`
`B. Claims 1, 2, 4, 5, 7, and 8 are Anticipated by Chakravorty ’362,
`and Claims 3, 9-12, 14, and 15 are Unpatentable Over
`Chakravorty ’362 and Siniaguine
`
`With respect to the alleged anticipation of claims 1, 2, 4, 5, 7, and 8
`
`by Chakravorty ’362, and the alleged obviousness of claims 3, 9-12, 14, and
`
`15 over Chakravorty ’362 and Siniaguine, we have reviewed IVM’s Petition,
`
`Xilinx’s Patent Owner Response, and IVM’s Reply, as well as the evidence
`
`discussed in each of those papers. We are persuaded, by a preponderance of
`
`the evidence, that claims 1, 2, 4, 5, 7, and 8 are anticipated by Chakravorty
`
`’362 under 35 U.S.C. § 102(e), and claims 3, 9-12, 14, and 15 are
`
`unpatentable over Chakravorty ’362 and Siniaguine under 35 U.S.C.
`
`§ 103(a). See Pet. 49-58; Ex. 1002 ¶¶ 126-53.
`
`Xilinx’s sole argument regarding the asserted grounds is that
`
`Chakravorty ’362 does not teach “disposing an interposing structure between
`
`the integrated circuit die and the inside surface of the integrated circuit
`
`package,” as recited in independent claim 1, or “fabricating an interposing
`
`structure above the array of landing pads on the inside surface of the
`
`integrated circuit package,” as similarly recited in independent claim 9.
`
`PO Resp. 11-15. For the reasons explained below, Xilinx’s argument is not
`
`persuasive.
`
`Chakravorty ’362 is directed to an “electronic assembly that includes
`
`an interposer having one or more embedded capacitors to reduce switching
`
`noise in a high-speed integrated circuit, and to manufacturing methods
`
`related thereto.” Ex. 1009, col. 1, ll. 17-21.
`
`
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`19
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`Case IPR2012-00019
`Patent 8,062,968 B1
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`Figure 3 of Chakravorty ’362 is reproduced below.
`
`
`
`Figure 3 depicts an assembly comprising integrated circuit (IC) die 300,
`
`solder balls 301, lands 302, interposer 310 (with embedded capacitors),
`
`lands 312, solder balls 311, and primary substrate 320. Id. at col. 5,
`
`ll. 30-60. IVM identifies IC die 300 as the claimed “integrated circuit die,”
`
`primary substrate 320 as the claimed “integrated circuit package,” interposer
`
`310 as the claimed “interposing structure,” and the signal terminals/bumps
`
`below solder balls 311 as the claimed “landing pads” of claims 1 and 9. Pet.
`
`50, 55. According to IVM, interposer 310 is disposed between IC die 300
`
`and the “inside surface” of primary substrate 320 above the signal
`
`terminals/bumps in primary substrate 320. Id; see Ex. 1002 ¶ 128.
`
`Xilinx argues that interposer 310 is coupled to an “outside surface,”
`
`not an “inside surface,” of primary substrate 320. PO Resp. 11-12.
`
`Similarly, Xilinx asserts that the signal terminals/bumps below solder balls
`
`311 are not on an “inside surface” of primary substrate. Id. at 13-14. As
`
`explained above, however, “inside surface” means the surface of the
`
`
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`20
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`Case IPR2012-00019
`Patent 8,062,968 B1
`
`integrated circuit package facing in from the package toward the integrated
`
`circuit die. See supra Section II.A.1. Although interposer 310 is not shown
`
`in Figure 3 as completely surrounded by or encapsulated within primary
`
`substrate 320, such surrounding or encapsulation is not required by the
`
`claims. See id. The inside surface of primary substrate 320 is the top of the
`
`substrate shown in Figure 3, which has signal terminals/bumps immediately
`
`below solder balls 311. See Ex. 1009, col. 4, ll. 15-21; col. 5, ll. 20-25; Figs.
`
`2-3. This surface faces in from primary substrate 320 toward IC die 300, in
`
`contrast to the bottom of the substrate shown in Figure 3, which faces
`
`outward away from IC die 300. Interposer 310 is disposed between the
`
`inside surface of primary substrate 320 and IC die 300.
`
`Further, as explained above, Xilinx’s position as to what is on an
`
`“inside surface” of an integrated circuit package (between the integrated
`
`circuit die and inside surface) and what is not is contradicted by arguments
`
`the applicant made during prosecution of the ’960 patent. Specifically, the
`
`applicant characterized solder bumps 58 in Figure 2 of Chakravorty ’362 as
`
`on an “inside surface” of primary substrate 60, but Xilinx now argues that
`
`interposer 310 in Figure 3 is not on an “inside surface” of primary substrate
`
`320 between IC die 300 and primary substrate 320.
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