`Entered: February 11, 2014
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`Trials@uspto.gov
`Tel: 571-272-7822
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
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`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
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`v.
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`XILINX, INC.
`Patent Owner
`_______________
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`Case IPR2012-00023
`Patent 7,994,609 B2
`_______________
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`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`JUSTIN T. ARBES, Administrative Patent Judges.
`
`EASTHOM, Administrative Patent Judge.
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`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`Case IPR2012-00023
`Patent 7,994,609
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`I. BACKGROUND
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`
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`Petitioner, Intellectual Ventures Management, LLC (“IVM”), filed a Petition
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`to institute an inter partes review of claims 1–19 of U.S. Patent No. 7,994,609 B2
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`(“the ’609 Patent”), owned by Xilinx, Inc. Paper 3 (“Pet.”). See 35 U.S.C. § 311.
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`As set forth in this Final Written Decision, see 35 U.S.C. § 318(a), based on the
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`record presented, IVM has shown “by a preponderance of the evidence,” 35 U.S.C.
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`§ 316(e), that claims 1–19 of the ’609 Patent are unpatentable under 35 U.S.C.
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`§ 103(a). In addition, Xilinx has failed to show that proposed amended claims are
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`patentable under 35 U.S.C. § 103(a). See Paper 17 (“Mot. to Amend”).
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`After IVM filed its Petition, Xilinx filed a Preliminary Response opposing
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`the institution of the inter partes review. Paper 9 (“Prelim. Resp.”). The Board
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`granted the Petition, concluding that IVM’s Petition demonstrated a reasonable
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`likelihood that claims 1–19 are unpatentable under 35 U.S.C. § 103(a) for
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`obviousness, and instituted trial. Paper 11 (“Inst. Dec.”).
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`After the Institution Decision, Xilinx filed a Response. Paper 15 (“PO
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`Resp.”). Xilinx also filed a Motion to Amend, contingent upon the Board
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`ultimately determining that challenged claims 1–19 are unpatentable. See Paper 17
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`(“Mot. to Amend”). IVM then filed a Petitioner Reply to Xilinx’s Response,
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`maintaining that the challenged claims are unpatentable. Paper 22 (“Pet. Reply”).
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`IVM also filed an Opposition to Xilinx’s Motion to Amend, Paper 21 (“Opp.”),
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`and Xilinx filed a Patent Owner Reply to the Opposition, Paper 24 (“PO Reply”).
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`Both parties requested an oral hearing, which occurred on November 7, 2013. A
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`transcript of the oral hearing appears in the record. Paper 33 (“Tr.”).
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`In its Response––i.e., in “response to the [P]etition [and] addressing any
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`ground for unpatentability not already denied,” 37 C.F.R. § 42.120––Xilinx argues
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`that claims 2, 8, 9, 18, and 19, “are valid.” PO Resp. 5. Xilinx does not argue that
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`Patent 7,994,609
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`claims 1, 3–7, and 10–17 are patentable. Claims 2, 8, and 9 depend from
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`independent claim 1, and claim 19 depends from independent claim 18. Therefore,
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`as Xilinx acknowledged during the oral hearing, Xilinx concedes that claims 1,
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`3–7, and 10–17 are unpatentable based on the applicable grounds listed in the
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`Institution Decision. Tr. 48, ll. 5–9; accord Office Patent Trial Practice Guide,
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`77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012) (“The [patent owner] response should
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`identify all the involved claims that are believed to be patentable and state the basis
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`for that belief.”); Inst. Dec. 13 (determining that IVM’s Petition “sufficiently
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`demonstrates a reasonable likelihood that claims 1–19 are unpatentable based on
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`Grounds 1–6”).
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`A. The ’609 Patent
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`The ’609 Patent describes a shielded capacitor in an integrated circuit (IC)
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`having a core capacitor portion that includes multiple layers of conductive
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`elements. Shields, including a shield capacitor portion and a capacitor reference
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`shield, surround the core capacitor portion. The shield capacitor portion includes
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`multiple conductive elements in different metal layers. According to claim 1, the
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`shield capacitor portion forms part of a capacitor node and lies partially between
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`the reference shield and the core capacitor portion. The shields reduce electronic
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`noise. See Ex. 1001, col. 2, l. 40 – col. 3, l. 3; col. 5, ll. 1–4; col. 6, ll. 24–31;
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`Abstract.
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`To identify disclosed structure that corresponds to certain elements recited in
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`claims 1 and 2, IVM annotates Figures 2A and 2B from the ’609 Patent, which are
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`reproduced below:
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`
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`IVM’s annotated figures above show a centrally located core capacitor,
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`including a first (T1, T2) and second (B1, B2) plurality of node elements,
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`numbered conductive layers, one capacitor node (B, B’, B1–B5), the other
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`capacitor node (T, T1–T5), and shields. See Pet. 4-5.
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`With respect to independent claim 1 (which follows), layer T corresponds to
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`a second part of a first capacitor node, layers B and B’ correspond to a shield
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`capacitor portion and a second part of a second capacitor node, and the VDD shield
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`corresponds to a reference shield.
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`B. Exemplary Claims
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`Claims 1 and 2 are reformatted and annotated with bracketed information
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`added to claim 1 to help illustrate example structure and with limitations at issue in
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`claim 2 emphasized, as follows:
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`1. A capacitor in an integrated circuit (“IC”) comprising:
`a core capacitor portion having a first plurality of conductive
`elements [see T1,T2] electrically connected to and forming a first part
`of a first node of the capacitor formed in a first conductive layer of the
`IC and a second plurality of conductive elements [see B1, B2]
`electrically connected to and forming a first part of a second node of
`the capacitor formed in the first conductive layer,
`the first plurality of conductive elements alternating with the
`second plurality of conductive elements in the first conductive layer,
`and a third plurality of conductive elements [see T] electrically
`connected to and forming a second part of the first node formed in a
`second conductive layer adjacent to the first conductive layer, at least
`portions of some of the second plurality of conductive elements
`overlying and vertically coupling to at least portions of some of the
`third plurality of conductive elements;
`a shield capacitor portion [see B, B’] having a fourth plurality
`of conductive elements formed in at least the first conductive layer of
`the IC, the second conductive layer of the IC, a third conductive layer
`of the IC, and a fourth conductive layer of the IC, the first conductive
`layer and the second conductive layer each being between the third
`conductive layer and the fourth conductive layer, the shield capacitor
`portion being electrically connected to and forming a second part of
`the second node of the capacitor and surrounding the first plurality of
`conductive elements and the third plurality of conductive elements;
`and
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`a reference shield [see VDD Shield] electrically connected to a
`reference node of the IC other than the second node of the capacitor,
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`the shield capacitor portion being disposed between the reference
`shield and the core capacitor portion.
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`2. The capacitor of claim 1 wherein the third conductive layer is a
`metal layer of the IC and the fourth conductive layer is a poly layer of
`the IC, the shield capacitor portions including a first node shield plate
`formed in the metal layer from a plurality of metal stripes and a
`second node shield plate formed in the poly layer.
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`
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`See ’609 Patent, col. 12, l. 55 – col. 13, l. 25 (emphases added); see also PO Resp.
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`5 (discussing disputed limitations in claim 2).
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`C. Grounds of the Trial
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`The prior art references applied to the claims follow:
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` May 18, 2004 (Ex. 1006)
`U.S. Patent 6,737,698
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`Paul
` Oct. 21, 2008 (Ex. 1007)
`Anthony U.S. Patent 7,439,570
`Hsueh
`U.S. Patent 7,286,071 Oct. 23, 2007 (Ex 1008)
`Brennan
`U.S. Patent 6,903,918 June 7, 2005 (Ex 1009)
`Bi
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`U.S. Pub. 2008/0128857 June 5, 2008 (Ex 1010)
`Marotta U.S. Patent 7,238,981
` July 3, 2007 (Ex. 1011)
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`The Board instituted trial based upon the following grounds of
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`unpatentability under 35 U.S.C. § 103:
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`Reference[s]
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`Paul
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`Paul and Anthony
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`Paul and Hsueh
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`Paul and Brennan
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`Anthony and Marotta
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`Anthony and Bi
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`Basis
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`§ 103
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`§ 103
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`§ 103
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`§ 103
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`§ 103
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`§ 103
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`6
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`Claims challenged
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`1, 3, 5, 6, and 10–12
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`2 and 13–17
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`4
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`7–9
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`18 and 19
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`1 and 13
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`II. ANALYSIS
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`A. Claim Interpretation
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`Consistent with the statute and legislative history of the Leahy-Smith
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`America Invents Act, Pub. L. No. 112-29, 125 Stat. 284, 329 (2011) (“AIA”), the
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`Board interprets claims using the “broadest reasonable construction in light of the
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`specification of the patent in which [they] appear[].” 37 C.F.R. § 42.100(b); see
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`also Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14,
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`2012).
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`Plate
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`The parties do not define the term plate, which appears in claims 2 and 18.
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`In addition to capacitor node plates such as B, T, B’, Ex. 1001, col. 5, ll. 58-60, the
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`’609 Patent also refers to “ground plate 287,” and “shield plate 260,” id. at col. 8, l.
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`25, l. 36, as part of the capacitor, but not necessarily as nodes of a capacitor. See
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`id. at Fig. 2C (ground plate 287 and shield plate 260 not electrically connected to
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`capacitor nodes B and T). In other words, according to the ’609 Patent claims and
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`disclosure, a “plate” does not imply necessarily a capacitor node.
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`In terms of the physical structure of a plate, the ’609 Patent generally
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`discloses that “an arbitrary number of layers may be used in accordance with
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`embodiments of the invention,” id. at col. 11, ll. 25–27, and that a “plate layer [can
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`be] made up of strips, rather than a continuous sheet,” id. at col. 5, ll. 5–6. The
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`’609 Patent also refers to “silicide plates or strips,” id. at col. 3, l. 59, indicating
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`that a “plate” signifies structure that is distinct from a strip. The ’609 Patent
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`implies that, in addition to being discontinuous, a plate may have multiple layers:
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`“The bottom plate conductive matrix [see B, B’ and conductive curtains, Fig. 2C]
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`of the integrated capacitor loosely surrounds the top plate conductive matrix [T,
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`T1, T2 . . . T8] of the integrated capacitor so that the top plate couples with the
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`bottom plate on the top, bottom, right side, and left side.” Ex. 1001, col. 6, ll. 3–7
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`(emphases added), Fig. 2C. This reference to the “bottom plate conductive matrix”
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`that “surrounds” the top plate, and the description that the “top plate couples with
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`the bottom plate on the top, bottom, right side, and left side,” implies that the
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`“bottom plate” may have multiple layers in order to couple to the top plate on all
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`sides and to surround the top plate.
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`Accordingly, based on the ’609 Patent disclosure, a “plate” is a conductive
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`structure that is part of a capacitor, as either a shield, a node, or a node that also
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`functions as a shield, which may be continuous, as a sheet, or discontinuous, as
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`electrically connected strips, and which may or may not comprise plural
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`electrically connected layers.
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`B. Claim 2
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`Poly Node Shield Plate
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`Xilinx argues that the combination of Paul and Anthony does not render
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`obvious a poly node shield plate as set forth in dependent claim 2. See PO Resp.
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`5–10. According to Xilinx, “neither Paul nor Anthony teach[es] or suggest[s] a
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`‘shield plate’ that is ‘formed in the poly layer’ and is ‘part of the second node of
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`the capacitor.” Id. at 6.
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`To illustrate the disputed limitation in claim 2, Xilinx annotates Figure 2B
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`from the ’609 Patent, as follows:
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`Xilinx’s annotated Figure 2B from the ’609 Patent shows a disclosed poly
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`shield plate, near the bottom, as capacitor node layer B’, which connects to
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`capacitor node layer B (the other capacitor node includes layer T). See id.
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`According further to Xilinx’s annotated Figure 2B, the capacitor nodes are
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`not connected electrically (i.e., conductively) to the reference shield. Xilinx
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`maintains that claim 2, by virtue of dependency from claim 1, requires “the shield
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`capacitor portion [to be] ‘electrically connected to and form a second part of the
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`second node of the capacitor.’” Id. (brackets by Xilinx omitted).
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`IVM and Xilinx agree that Paul does not disclose a poly node shield plate.
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`See id.; Pet. 24; Ex. 1002 ¶ 50. The parties also agree that Anthony discloses a
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`poly capacitor bottom shield layer 36 as an alternative to a metal layer. PO Resp.
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`7; Ex. 1002 ¶ 50 (discussing and quoting Ex. 1007, col. 4, ll. 49–52). However,
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`Xilinx reasons that bottom layer 36 of Anthony “is a reference shield, and is never
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`shown or suggested as being connected to or part of the capacitor node.” PO Resp.
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`9 (footnote omitted). In other words, Xilinx stresses that Anthony only teaches a
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`bottom reference poly shield plate 36, as opposed to a bottom node poly shield
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`plate. Id.
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`Xilinx’s arguments separately attack the references and fail to rebut IVM’s
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`obviousness showing that relies on the combination, as IVM states. See Pet. Reply
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`4. IVM asserts, and the record shows, that “Paul’s [bottom] shield plate 810
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`[constitutes] a [metal] shield plate connected to a capacitor node.” See Pet. Reply
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`4; Ex. 1006, Fig. 8; Inst. Dec. 11. Both experts agree that Anthony discloses
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`bottom shield layer of poly 36. See Pet. Reply 2–5 (discussing testimony by Mr.
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`Johnson and Dr. Blanchard); Ex. 1007, Fig. 3B. Xilinx’s arguments imply that
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`Anthony’s teaching that poly can be used in place of metal as a capacitor shield
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`does not apply to capacitor nodes or node shields. See PO Resp. 9. Xilinx’s
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`arguments effectively reduce to the assertion that it would have been unobvious to
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`replace one known type of capacitor conductor layer for another.
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`To the contrary, Anthony specifically teaches that “[a]s an alternative to the
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`use of a metal layer as shown in FIG. 3B (which may be needed for interconnect
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`purposes) the bottom shield plate 36 can be implemented with a polysilicon or
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`diffusion layer.” Ex. 1007, col. 4, ll. 49–52 (italics emphases added). As skilled
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`artisans would have recognized, the sentence shows that poly and metal constitute
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`suitable electrical conductors for capacitors. The sentence instructs that metal
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`layers may be “needed for interconnect purposes,” which implies or suggests that
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`metal necessarily would not be needed to create nodes or shields. See id. It
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`follows that Anthony’s teaching is not restricted to metal capacitor shields and
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`applies generally to metal layers, including metal capacitor nodes.
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`IVM further relies on its expert, Mr. Johnson, and reasons that “one skilled
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`in the art would have been motivated to make this substitution [i.e., to substitute
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`the poly of Anthony for the metal of Paul] to, for example, save a metal layer for
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`another purpose or as a matter of convenience depending on where a signal may be
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`coming from.” Pet. Reply 6 (citing Ex. 1013 ¶ 20). IVM also points to the
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`corroborative testimony of Xilinx’s expert, Dr. Blanchard, who reasons that
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`“‘sometimes you need to get from A to B’” and describes
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`“one of a couple of reasons [for using poly instead of metal], one
`having to do with layout, because all the other conductive layers were
`used up, so you need something here, or just out of convenience, a
`signal might be going to or coming off the poly layer associated with
`a gate or something else.”
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`Pet. Reply 6 (quoting Ex. 1014, 52, ll. 15–25).
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`The record shows that choosing a poly layer to replace a metal layer would
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`have amounted to a matter of convenience involved in a circuit layout, where, for
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`example, a poly layer is planned for other circuit components or connections on the
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`same layer, or metal layer constraints exist. Replacing a metal capacitor layer with
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`a poly capacitor layer would have resulted in a predictable result, a capacitor with a
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`similar conductor. “The Court recognized that when a patent claims a structure
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`already known in the prior art that is altered by the mere substitution of one
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`element for another known in the field, the combination must do more than yield a
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`predictable result.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (citing
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`United States v. Adams, 383 U.S. 39 (1966)).
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`Therefore, based on the record evidence in light of the arguments presented,
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`IVM has shown “by a preponderance of the evidence,” 35 U.S.C. § 316(e), that
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`claim 2 would have been obvious over the combination of Paul and Anthony.
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`C. Claims 8 and 9
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`Claim 8 depends from claim 7, which depends from claim 1. Claim 8
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`follows: “The capacitor of claim 7 wherein each of the conductive elements in the
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`third plurality of conductive elements is adjacent to a conductive element
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`electrically connected to and forming a third part of the first node.”
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`Figure 2A from the ’609 Patent, annotated by Xilinx, appears below:
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`Annotated Figure 2A above depicts one view of a third plurality of
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`conductive elements (at node T) corresponding to those elements as recited in
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`claim 8, according to Xilinx. PO Resp. 11.
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`Adjacent Conductive Elements
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`Xilinx argues that the prior art combination does not satisfy the limitation
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`that involves “adjacent” conductive elements in claim 8, essentially, according to
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`Xilinx, because “adjacent” conductive elements imply a “plate” layer, and the ’609
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`Patent discloses advantages to having a “plate” layer. See PO Resp. 11–13 (citing
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`Ex. 1001, col. 5, ll. 57–58, as describing a “plate” layer). According to Xilinx, a
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`“plate” layer has non-alternating nodes, which Paul does not disclose, and claim 8
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`requires “a specific lateral capacitance and vertical capacitance.” Id. at 11–12
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`(citing Ex. 1001, col. 6, ll. 33-38).
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`In Paul, the outer shield layers, A and B, do include non-alternating
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`conductor strips, while the middle layers do not, because they have alternating
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`nodes, A and B. See, e.g., Ex. 1006, Figs. 4, 8, 12. Paul’s figures also show
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`vertical and horizontal capacitive field coupling that occurs between opposite node
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`strips A and B, see Ex. 1006, Figs. 2, 4. Xilinx does not assert that Paul’s
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`alternating node strip layers fail to produce the unclaimed horizontal and vertical
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`capacitance.
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`As discussed in the claim construction section, the ’609 Patent refers to
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`“silicide plates or strips,” Ex. 1001, col. 3, l. 59, and indicates that “a plate layer is
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`made up of strips,” id. at col. 5, l. 5. Although the ’609 Patent indicates that node
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`plate layers have non-alternating strips, claim 8 does not recite a “plate” layer.
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`See id. at col. 6, ll. 57-60 (“The plate layers B, T, B’ do not have alternating
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`conductive strips, but rather all the conductive strips in these layers are connected
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`to either the top node or bottom node.”) Claim 8 also does not recite “non-
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`alternating” node strips (that may imply or require a “plate” layer). Further, the
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`recited term “adjacent” in claim 8 does not imply a plate layer of non-alternating
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`nodes, as IVM argues. See Pet. Reply 8–9. In other words, Xilinx’s arguments fail
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`to show a claim distinction over the prior art, as explained further below.
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`As noted, IVM asserts obviousness of claim 8 based on the combination of
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`Paul and Brennan. See Pet. Reply 8; Pet. 40–41. IVM relies on Paul’s teachings
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`for most of the structure recited in claim 8, and relies on Brennan’s teaching of
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`layers having orthogonal strips, as recited in claim 7, from which claim 8 depends.
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`IVM also relies on Paul’s and Brennan’s teachings that suggest any number of
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`capacitive strips and layers. See Pet. 38–43 (discussing dependent claims 7 and 8);
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`id. at 40 (quoting Ex. 1009, col. 7, ll. 43–46: “traces . . . may be aligned
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`orthogonal to each other”); id. at 42 (quoting Ex. 1006, col. 4, ll. 51–52: “using
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`any number of layers of conductive strips,” and relying on Figure 4 in which
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`“Brennan discloses a multi-layer capacitor”). In light of these and other teachings,
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`IVM reasons that “[a] person of ordinary skill in the art would appreciate that the
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`third plurality of conductive strips of Paul could be arranged to be orthogonal to
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`the first and second pluralities of conductive strips as suggested by Brennan.” Pet.
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`40.
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`Annotated Figure G, which represents a modified version of Paul’s figures,
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`according to Mr. Johnson’s first Declaration and the Petition, appears below:
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`Annotated Figure G above depicts the third plurality of conductive elements,
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`B, which are orthogonal to adjacent first, second, fourth, and fifth pluralities of
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`conductive elements, generally as recited in claims 7 and 8, according to IVM’s
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`Petition. See Ex. 1002 ¶ 77; Pet. 43.
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`IVM points out that the parties’ two experts, Dr. Blanchard and
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`Mr. Johnson, agree that the term “adjacent” in claim 8, based on the ’609 Patent
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`disclosure, allows conductive elements to be above or below one another. See Pet.
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`Reply 8–9 (discussing adjacent capacitor elements B1, B2, B5 as disclosed in the
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`’609 Patent at Fig. 2B, discussing Figure G of the first Johnson Declaration, and
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`citing Ex. 1013 ¶ 21; Ex. 1014, 88, l. 15 – 89, l. 12). Claim 1 corroborates this
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`meaning of “adjacent” by reciting “a second conductive layer adjacent to the first
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`conductive layer.” Therefore, claim 8 is broad enough to include “a conductive
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`element . . . forming a third part of a first node” in a layer “adjacent” to, i.e., above
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`or below, the layer having “the third plurality of conductive elements.” In other
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`words, contrary to Xilinx’s argument, “adjacent” in claim 8 does not signify,
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`necessarily, a single layer plate or non-alternating node strips in a single plate
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`layer.
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`Stated differently, although the “third plurality of conductive elements”
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`recited in claim 8 is in a “the second layer” and also forms a “second part of the
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`second node,” according to independent claim 1, the “conductive element
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`electrically connected to and forming a third part of the first node” need not be in
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`that “second layer.” Rather, that conductive element, which forms a third part of
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`the first node, is broad enough to be either in the “second layer” of claim 1, as a
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`“single layer,” or in a layer adjacent to, i.e., above or below, that second layer, as a
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`“double layer.”
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`As to the former “single layer” situation, conductive elements adjacent to a
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`conductive element and all in the same second layer, Paul suggests non-alternating
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`adjacent conductive strips in the same layer (i.e., a plate layer) as follows: “the
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`conductive strips 404 and 406 alternate, although other configurations may also be
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`used.” Ex. 1006, col. 3, ll. 16–17 (italics emphasis added). Such “other
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`configurations” suggest the opposite of alternating nodes––non-alternating nodes,
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`such as Paul depicts in the form of a side shield of node elements A in Figure 8.
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`Ex. 1006. In addition, Brennan explicitly discloses such non-alternating
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`conductive strips in the form of multiple slotted plate layers in a capacitor. See Ex.
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`1009, Fig. 4. As IVM and Mr. Johnson point out, Paul teaches that a capacitor
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`may have any number of conductive strip layers, further suggesting a modification
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`that employs slotted or non-alternating layers, as Paul and Brennan suggest. See
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`Pet. Reply 7 (citing Ex. 1006, col. 4, ll. 51–52; Ex. 1002 ¶ 77). Employing non-
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`alternating strips in a layer results in more nodes of one type (A) than another (B)
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`and accordingly results in an unequal area, or number, of opposite nodes. This
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`nodal inequality creates an “unbalanced” capacitor that is distinct from a
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`“balanced” capacitor, according to another of Xilinx’s arguments, as discussed
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`further below. See PO Resp. 14–15.
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`Alternatively, as to the latter “double layer” situation, adjacent conductive
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`strip elements in layers adjacent to the second layer, Paul discloses conductive strip
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`elements B, which IVM annotates in Figure G above as a “1st [or 4th] plurality of
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`conductive elements.” The “1st plurality” in the first layer is depicted as being
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`immediately above, or adjacent to, the “3rd plurality” of conductive node elements
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`B in the second layer. See supra annotated Fig. G. Based on this alternative
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`reason, it follows that Paul’s structure, as modified, or not, by Brennan, includes an
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`adjacent “conductive element electrically connected to and forming a third part of
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`the first node,” as set forth in claim 8. See Pet. Reply 8–9; Pet. 38–44 (discussing
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`adjacent layers and strip elements).
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`A subset of the other conductive strips of the “1st [or 4th] plurality of
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`conductive elements” depicted in Figure G correspond to other claim limitations
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`that claim 1 recites and that Xilinx does not challenge. See supra annotated Fig. G.
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`Although Figure G does not depict explicitly more than two conductive node strips
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`B in each layer, Paul and Brennan suggest a plurality of such conductive strips––
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`i.e., including a number greater than two.1
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`1 In other words, Paul and Brennan, individually or collectively, suggest any
`number of conductive strips in a layer. Compare Ex. 1006, Figure 7 with Figure 8;
`see Ex. 1009, Fig. 4. According to claim 1, “a second part of the first node” must
`be in the second conductive layer, and “a first part of a first node” must be in a first
`conductive layer. Claim 8 does not specify the location of the third part of the first
`node. Accordingly, claim 8 is broad enough to encompass two or more node strips
`B of Paul (as modified by Brennan), on one side of a layer to form “a first part of a
`first node”; two or more node strips on one side of an adjacent layer to form “a
`second part of the first node,” as claim 1 recites; and one or more node strips B on
`another side of either one of those layers to form “a third part of the first node,” as
`claim 8 recites. See Pet. 42-43 (discussing “adjacent” conductive elements recited
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`With respect to both “adjacent” alternatives described above (i.e., the single
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`and double layer alternatives), as Xilinx, IVM, and the experts discuss, Brennan’s
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`slotted non-alternating layers provide distinct advantages, such as improving the Q
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`factor and filtering noise in a capacitor by reducing eddy currents that otherwise
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`flow in continuous sheet plate layers. See PO Resp. 13–14 (acknowledging
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`Brennan’s benefits); Ex. 1009, col. 6, l. 61 – col. 7, l. 9; Ex. 2006 ¶¶ 23, 26; Ex.
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`1002 ¶ 75; Pet. 40–41. Brennan’s slotted conductors are similar to Paul’s strip
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`conductors, in comparison to wide continuous sheets that would carry the eddy
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`currents more readily as discussed by Brennan. See Ex. 1009, col. 6, l. 61 – col. 7,
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`l. 9. Logically, according to Brennan’s discussion, based on structural similarities,
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`ordinarily skilled artisans would have recognized that Brennan’s described benefits
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`of non-continuous capacitor node layers would flow to non-continuous orthogonal
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`conductor strips in Paul’s modified structure. See id.
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`Balanced versus Unbalanced Capacitors
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`Turning to Xilinx’s argument, mentioned above, that concerns a distinction
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`between “balanced” and “unbalanced” capacitors, Xilinx asserts that “both Paul
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`and Brennan are directed to balanced capacitors. Paul teaches a capacitor in which
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`the layers of conducting elements are always balanced. . . . Likewise, Brennan
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`teaches a capacitor with equal number of plate layers (balanced).” PO Resp. 14.
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`According to Xilinx, employing one of Brennan’s capacitor layers in Paul’s
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`balanced capacitor structure “is not merely adding another set of nodes to perform
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`their known function, but . . . is changing the functional operation of the resulting
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`capacitor in a way not previously described.” PO Resp. 15. Dr. Blanchard makes
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`the same statement. See Ex. 2006 ¶ 35. Citing In re Gordon, 733 F.2d 900 (Fed.
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`Cir. 1984), Xilinx implies that IVM’s proposed modification would render Paul’s
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`in claim 8).
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`disclosed capacitors unsatisfactory for their intended purpose. See PO Resp. 15.
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`On the other hand, IVM characterizes this dispute about “balanced”
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`capacitors as follows: “Xilinx still does not dispute that the combination of Paul
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`and Brennan disclose[s] all the features of claim 8. Rather, Xilinx relies on an
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`illusory difference between ‘balanced’ and ‘unbalanced’ capacitors to attack the
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`combination of Paul and Brennan.” Pet. Reply 8.
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`On this record, IVM’s position is more persuasive. Claim 8 does not recite
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`the term “balanced.” IVM responds to Xilinx under the above-discussed
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`assumption that the term “unbalanced” roughly corresponds to a capacitor that has
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`more nodes, or nodal surface area, of one polarity (for example, A) relative to a
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`node of the other polarity (for example, B). See Pet. Reply 10; Ex. 1013 ¶ 22; Ex.
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`1014, 86, 20–24 (discussing unbalanced capacitor in the ’609 Patent at Figure 1 in
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`capacitor 104 due to the greater plate surface area of nodes 112, 120 as compared
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`to the plate surface area of node 108). According to the “BACKGROUND”
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`section of the ’609 Patent, “[p]roviding an equal number of conductive strips in a
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`layer for each node balances the coupling of each node to the substrate which is
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`desirable in some applications, but undesirable in others, such as switching
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`applications where it is desirable to have less coupling at one node.” Ex. 1001, col.
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`1, ll. 63–67 (emphasis added).
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`In light of this understanding, and addressing Xilinx’s position, Mr. Johnson,
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`IVM’s expert, testifies that Figure 8 of Paul depicts an unbalanced capacitor, with
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`“more conductive elements coupled to Node A than to Node B by virtue of side
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`shield 812.” Ex. 1013 ¶ 22.
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`Figure 8 of Paul follows:
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`Figure 8 of Paul, reproduced above, depicts a capacitor having a greater
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`number of node strips A than B. Ex. 1006. According to Mr. Johnson, “[i]f side
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`shield 812 is sufficiently close to elements 804 and 806 located to its right so as to
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`contribute to the total capacitance of the capacitor, then FIG. 8 is an ‘unbalanced
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`capacitor.’” Ex. 1013 ¶ 22.
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`Temporarily setting aside the question of whether Paul’s Figure 8 represents
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`an unbalanced capacitor, Xilinx’s argument that the proposed combination
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`impermissibly results in an unbalanced capacitor that destroys the function of
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`Paul’s capacitor apparently applies to the single layer alternative––wherein the
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`combined structure results in an unbalanced middle plate layer that only has node
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`strip elements B (thereby forming a large number of node strips B relative to node
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`strips A). See supra IVM’s annotated Figure G. The other alternative, the double
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`layer alternative, which results in, according to Brennan’s orthogonal conductor
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`teachings, rotating one of Paul’s balanced layers that has both types of node strip
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`elements A and B, would not result in an unbalanced structure, according to
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`Xilinx’s definition of “balanced” and its characterization of Paul. Therefore, based
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`at least on this latter alternative, Xilinx’s argument is unpersuasive, as it does not
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`account for the full teachings of Paul and Brennan.
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`Apparently assuming that the obviousness ground only includes the double
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`layer alternative, a balanced middle layer, in related arguments pertaining to
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`proposed amended claim 20, which Xilinx characterizes as “includ[ing] limitations
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`previously recited in dependent claim 8,” Xilinx maintains that Paul’s Figure 8
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`capacitor is b