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` Paper 48
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` Entered: November 4, 2016
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`AMERICAN MEGATRENDS, INC., MICRO-
`STAR INTERNATIONAL CO., LTD, MSI COMPUTER CORP.,
`GIGA-BYTE TECHNOLOGY CO., LTD., and G.B.T., INC.,
`Petitioners,
`
`v.
`
`KINGLITE HOLDINGS INC.,
`Patent Owner.
`_______________
`
`Case IPR2015-01094
`Patent 6,401,202 B1
`____________
`
`
`
`Before TREVOR M. JEFFERSON, BRIAN J. McNAMARA, and
`J. JOHN LEE, Administrative Patent Judges.
`
`JEFFERSON, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`37 C.F.R. § 318(a) and 37 C.F.R. § 42.73
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`Case IPR2015-01094
`Patent 6,401,202 B1
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`
`INTRODUCTION
`I.
`On November 6, 2015, we instituted inter partes review of claims 1,
`9–11, 19–21, 29–31, 39, and 40 of U.S. Patent No. 6,401,202 B1 (Ex. 1001,
`“the ’202 patent”). Paper 16 (“Dec.”). Patent Owner, Kinglite Holdings
`Inc., filed a Patent Owner Response, Paper 28 (“PO Resp.”), to the
`Corrected Petition (Paper 9, “Pet.”) filed by American Megatrends, Inc.,
`Micro-Star International Co., Ltd, MSI Computer Corp., Giga-Byte
`Technology Co., Ltd., and G.B.T., Inc. (collectively “Petitioner”). Petitioner
`filed a Reply. Paper 36 (“Pet. Reply”). Patent Owner filed a Contingent
`Motion to Amend (Paper 29, “Mot. to Amend”), and Petitioner filed an
`Opposition to Patent Owner’s Motion to Amend (Paper 35, “Pet. Opp.
`Amend”). Patent Owner filed a Motion to Exclude. Paper 24 (“PO Mot. to
`Exclude”). Petitioner also filed a Motion to Exclude. Paper 39 (“Pet. Mot.
`To Exclude”). A transcript of an oral hearing held on August 1, 2016 (Paper
`47, “Tr.”) has been entered into the record.
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. §318(a). We base our decision on
`the preponderance of the evidence. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d).
`Having reviewed the full record, we conclude that Petitioner has
`demonstrated by a preponderance of the evidence that the challenged claims
`are unpatentable for the reasons set forth below. For the reasons discussed
`below, we also deny Patent Owner’s Motion to Amend and both Patent
`Owner’s Motion to Exclude and Petitioner’s Motion to Exclude.
`
`A. Related Proceedings
`The parties state that the ’202 patent has been asserted in Kinglite
`Holdings Inc. v. Giga-Byte Techn. Co. Ltd., Case No. 1:14-cv-04989 (C.D.
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`Cal.); Kinglite Holdings Inc. v. Micro-Star International Co. Ltd., Case No.
`1:14-cv-03009 (C.D. Cal.); Kinglite Holdings, Inc. v. EliteGroup Comput.
`Sys. Co., Ltd. et al., Case No. 3:16-cv-00912 (N.D. Cal.); Kinglite Holdings,
`Inc. v. Giga-Byte Tech. Co., Ltd., Case No. 2:15-cv-009615 (C.D. Cal.); and
`Kinglite Holdings, Inc. v. Micro-Star Int’l. Co., Ltd., Case No. 2:15-cv-
`009612 (C.D. Cal.). Paper 32, 2; Paper 11, 1.
`
`B. The ʼ202 Patent
`The ’202 patent discloses “a method and apparatus to perform
`multitasking in a basic input and output system (BIOS).” Ex. 1001,
`Abstract. “Interrupt signals are enabled at predetermined interrupt times”
`such that “[a] first task is performed in response to the interrupt signals at
`the interrupt times” and “[a] second task is performed between the
`successive interrupt times.” Id. Figure 5, provided below, “illustrat[es] an
`architecture to perform multitasking in a [BIOS].” Id. at 2:22–23.
`
`
`Figure 5 shows architecture 500 to perform multitasking in a BIOS,
`interrupt generator 530, first task interrupt service routine (ISR) 540, and
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`first task data 550. Id. at 11:10–27. “BIOS includes an initial code 510, and
`interrupt configuration 512, a normal second task 514, an interrupt disable
`code 516, and an operating system (OS) boot-up code 518.” Id. at 11:17–20.
`The Specification states further that
`[t]he ISR 540 is executed each time the interrupt generator 530
`generates an interrupt signal such as when the timer reaches a
`specified value. When the ISR 540 is complete, the program
`control is returned to the normal second task 514 which will
`continue to perform the normal second task in the BIOS. The
`ISR 540 may use data provided by the first task data 550. The
`ISR 540 may operate upon the graphics engine in performing the
`first task. For example, the first task may be a graphics animation
`that display[s] animated
`sequence of banners and/or
`advertisements.
`Id. at 12:2–12.
`
`C. Illustrative Claims
`Independent claims 1, 11, 21, and 31 are reproduced below (Ex. 1001,
`14:33–42, 15:1–12, 15:45–57, 16:23–34):
`1. A method to perform multitasking in a basic input
`and output system (BIOS) by a processor, the method
`comprising:
`enabling interrupt signals at predetermined interrupt
`times;
`performing a first task in response to the interrupt
`signals at the interrupt times; and
`performing a second task between the successive
`interrupt times.
`
`11. A computer program product comprising:
`a computer usable medium having computer
`program code embodied therein to perform multitasking in
`a basic input and output system (BIOS) by a processor, the
`computer program product having:
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`computer readable program code for enabling
`interrupt signals at predetermined interrupt times;
`computer readable program code for performing a
`first task in response to the interrupt signals at the interrupt
`times; and
`computer readable program code for performing a
`second task between the successive interrupt times.
`
`21. A computer data signal embodied in a carrier wave
`comprising:
`to perform
`segment
`code
`a multitasking
`multitasking in a basic input and output system (BIOS) by
`a processor, the multitasking code segment having:
`an interrupt enable code segment for enabling
`interrupt signals at predetermined interrupt times;
`a first task code segment for performing a first task
`in response to the interrupt signals at the interrupt times;
`and
`
`a second task code segment for performing a second
`task between the successive interrupt times.
`
`31. A system comprising;
`a processor; and
`a memory coupled to the processor, the memory
`containing a program code, the program code when
`executed by the processor causing the processor to:
`enable interrupt signals at predetermined interrupt
`times,
`perform a first task in response to the interrupt
`signals at the interrupt times, and
`perform a second task between the successive
`interrupt times.
`D. Grounds of Unpatentability Instituted
`We instituted inter partes review on following grounds of
`unpatentability (Dec. 18–19):
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`Claims 1, 9–11, 19–21, 29–31, 39, and 40 of the ’202 patent under 35
`U.S.C. § 102 as anticipated by AMIBIOS1; and
`Claims 1, 9–11, 19–21, 29–31, 39, and 40 of the ’202 patent under 35
`U.S.C. § 102 as anticipated by Pearce2.
`
`II. ANALYSIS
`A. Claim Interpretation
`
`In the Decision to Institute, we applied the following claim
`constructions.
`We determined that “task” does not require further construction, but
`as recited in the ’202 patent claims does not exclude “the functions of setting
`up a programmable timer and determining which task to run.” Dec. 7.
`We determined that “interrupt controller” is construed as “a circuit or
`other device that generates or handles interrupts.” Id. at 8.
`The parties do not dispute these constructions, and we adopt them in
`this Decision for the reasons given in the Decision to Institute. Id. at 7–8.
`
`B. Level of Skill in the Art
`Petitioner contends that a person of ordinary skill in the art would be
`“a person holding a Bachelor of Science degree or its equivalent in electrical
`engineering or a related technical field such as computer science or software
`engineering, having at least one year of experience in computer
`programming.” Pet. 7. Patent Owner does not object to Petitioner’s
`
`
`1 American Megatrends, AMIBIOS 98 TECHNICAL REFERENCE (1998) (Ex.
`1003, “AMIBIOS”).
`2 U.S. Patent No. 5,694,582 to Pearce, filed Jan. 26, 1996, and issued Dec. 2,
`1997 (Ex. 1005, “Pearce”).
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`contention. Prelim. Resp. 4–5. We agree with Petitioner regarding the
`applicable level of ordinary skill.
`
`C. Anticipation by AMIBIOS (Ex. 1003)
`1. AMIBIOS (Ex. 1003)
`AMIBIOS is a technical manual that describes the technical details of
`“BIOS (Basic Input/Output System)[, which] is a collection of routines
`between the hardware and the systems software. The BIOS ROM contains
`hard disk utilities, device drivers, interrupt service routines, and other code
`and data between the system hardware and the systems software.” Ex. 1003,
`7. AMIBIOS states that “BIOS is the software layer between the systems
`software and the hardware” and “works in two directions.” Id. at 8. “One
`part of the BIOS receives and processes requests from programs to perform
`the standard BIOS I/O services” where the “mechanism for these requests is
`called an interrupt.” Id. “Interrupts are invoked by software programs.” Id.
`“The other side of the BIOS communicates with the hardware (video
`display, disk drives, keyboard, serial and parallel ports, and so on) in the
`language and codes used by each device. This side of the BIOS also handles
`any hardware device-generated interrupts.” Id.
`The AMIBIOS “Type of Interrupts” Figure is reproduced below. Id.
`at 89.
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`The Type of Interrupts Figure above depicts various interrupts that are
`reserved in BIOS. Id.
`The Types of Interrupts Figure shows various hardware interrupts,
`such as a keyboard interrupt (IRQ1). Id. AMIBIOS discloses that “every
`time a key is pressed on the keyboard, the keyboard hardware generates a
`hardware interrupt (IRQ)” that are “vectored to Interrupt Service Routines
`(ISRs) that generally reside in the BIOS.” Id. The Types of Interrupts
`Figure also shows System Timer IRQ0 as an interrupt. The “Timer Interrupt
`(IRQ0)” Figure is depicted below. Id. at 102.
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`The Timer Interrupt (IRQ0) Figure depicts how the system timer is
`used with the BIOS. Id.
`The Time Interrupt (IRQ0) Figure illustrates how the Intel 8254 Timer
`is used with the BIOS and INT 08h. Id. “INT 08h can be used to measure
`time increments independent of the system clock frequency. INT 08h is
`called approximately 18.2 times per second.” Id. “INT 08h increments the
`system time count . . . every time it is called.” Id. In addition, AMIBIOS
`states that “[p]rogrammers can revector INT 1Ch to their own routines and
`use the clock feature for timed events.” Id.
`2. Printed Publication and Patent Owner’s Motion to Exclude
`Patent Owner objected to AMIBIOS on evidentiary grounds (Paper
`21), but now seeks exclude AMIBIOS because it does not qualify as a
`printed publication and cannot form the basis of a challenge to the
`patentability of the claims under 35 U.S.C. § 102(b) (PO Mot. to Exclude
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`2).3 Patent Owner contends that Petitioner’s evidence is insufficient to
`support the date of publication and public accessibility of the reference. PO
`Mot. to Exclude 2–4. Furthermore, Patent Owner states that the Petitioner’s
`supplemental exhibits and Declaration of S. Shankar (Ex. 1015) should be
`excluded as improper supplemental information based on the timing of the
`submission. Id. at 7–8. In addition, Patent Owner contends that the
`proprietary information marking that limited further distribution of
`AMIBIOS is “mutually exclusive with the AMI reference as prior art” and
`cannot be relied on as a “body of knowledge held by the hypothetical person
`of skill in the art.” PO Resp. 2–3 (citing Motionless Keyboard Co. v.
`Microsoft Corp., 486 F.3d 1376 (Fed. Cir. 2007)). Accordingly, Patent
`Owner contends that there is no evidence in the record supporting a
`publication date and public accessibility of AMIBIOS prior to June 18,
`1998, the application date of the ’202 patent. PO Mot. to Exclude 4–5. At
`best, Patent Owner avers, “[t]he earliest shipment [of AMIBIOS] to an AMI
`‘customer’ reflected on Exhibit B to Mr. Shankar’s declaration (Ex. 1015)
`was August 26, 1998.” PO Mot. to Exclude 3.
`
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`3 Although Patent Owner objected to AMIBIOS on the basis of its
`authenticity (Paper 21, 4–5), the substance of Patent Owner’s Motion to
`Exclude addresses whether AMIBIOS is a printed publication. Patent
`Owner improperly attempts to raise new arguments regarding this issue in
`Patent Owner’s Motion to Exclude (Paper 24) that should have been
`included in the Patent Owner Response. PO Resp. 2 (stating that “[f]or the
`reasons set forth in Kinglite’s motion to exclude, there are evidentiary issues
`surrounding the AMIBIOS reference as a prior art publication”).
`Nonetheless, as explained herein, even if we consider Patent Owner’s
`improperly raised arguments, we conclude that AMIBIOS qualifies as a
`prior art printed publication and is admissible evidence.
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`For AMIBIOS to qualify as a printed publication, the document “must
`have been sufficiently accessible to the public interested in the art.” In re
`Lister, 583 F.3d 1307, 1311 (Fed. Cir. 2009). “A given reference is
`‘publicly accessible’ upon a satisfactory showing that such document has
`been disseminated or otherwise made available to the extent that persons
`interested and ordinarily skilled in the subject matter or art exercising
`reasonable diligence, can locate it.” SRI Int’l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186, 1194 (Fed. Cir. 2008) (quoting Bruckelmyer v. Ground
`Heaters, Inc., 445 F.3d 1374, 1378 (Fed. Cir. 2006)); see Kyocera Wireless
`Corp. v. Int’l Trade Comm’n, 545 F.3d 1340, 1350 (Fed. Cir. 2008) (stating
`that a reference is publicly accessible “upon a satisfactory showing that such
`document has been disseminated or otherwise made available to the extent
`that persons interested and ordinarily skilled in the subject matter or art
`exercising reasonable diligence, can locate it.”)
`Petitioner did not file an opposition to Patent Owner’s Motion to
`Exclude, but addresses this issue in its Reply to the Patent Owner Response,
`where the issue also is raised. PO Resp. 2–3; Pet. Reply 18–23. Petitioner
`responds, and we agree, that the evidence cited in Exhibit 1015 supports that
`AMIBIOS was publically accessible at least as early as June 1998. Id. at 20.
`Petitioner’s declarant, Subramonian Shankar, provides credible and
`convincing evidence establishing that 300 copies of AMIBIOS were printed
`for distribution, that AMIBIOS was made available to customers and the
`interested public, and that it was distributed on June 5, 9, and 15 of 1998.
`Ex. 1015 ¶¶ 2, 4, 12. Patent Owner’s arguments based on the sale of the
`AMIBIOS on August 25, 1998 do not undermine the testimony and evidence
`that AMIBIOS was checked out of AMI’s stockroom and distributed to
`
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`customers. Ex. 1015 ¶¶ 7, 12, (stating that AMIBIOS was checked out of
`the stockroom as part of the shipping process). Thus, contrary to Patent
`Owner’s contentions (PO Mot. to Exclude 3), we are persuaded that
`Petitioner’s evidence supports the contention that AMIBIOS was publicly
`accessible and distributed in June 1998.
`Also, Patent Owner’s arguments focus on actual dissemination of
`AMIBIOS and fail to address Petitioner’s evidence that AMIBIOS was
`made available to the public to the extent that persons interested and
`ordinarily skilled in the subject matter could locate it. See SRI Int’l, 511
`F.3d at 1194; Kyocera Wireless, 545 F.3d at 1350. We determine that
`Petitioner’s declarant and supporting evidence provides convincing support
`by a preponderance of the evidence that AMIBIOS was made available to
`the interested public as of at least June 1998.
`We are also not persuaded by Patent Owner’s argument based on the
`testimony of Mr. Sartori that the proprietary markings on AMIBIOS indicate
`it was subject to nondisclosure agreements. PO Resp. 2–3 4; see Ex. 2006,
`26:16–27:7 (Deposition of Gabriele Sartori). We determine that Mr.
`Sartori’s testimony that “normally we receive those documents [with a
`proprietary information notice] on the NDA [non-disclosure agreement]” is
`insufficient to support a finding that AMIBIOS was not publically
`accessible. Mr. Sartori also testified that such documents were normally
`disclosed to the public, stating “it’s not a guarantee that inside the document
`[is] information that you cannot disclose to third parties . . . it’s also true that
`
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`4 This argument was raised in the Patent Owner Response and not in the
`Motion to Exclude. PO Resp. 2–3. We address Patent Owner’s arguments
`here as they relate to the printed publication status of AMIBIOS.
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`we’ll produce those document[s] normally.” Ex. 2006, 26:23–27–4.
`Instead, we credit the testimony of Mr. Shankar, president and founder of
`AMI, that AMI did not restrict the availability of AMIBIOS and that it was
`accessible without such an agreement. Ex. 1015 ¶¶ 1, 3, 4.
`We are equally unpersuaded by Patent Owner’s argument that the
`timing of Petitioner’s submission of supplemental information and its effect
`on the publication date of AMIBIOS warrants the remedy of exclusion
`Patent Owner seeks. PO Mot. to Exclude 7. With respect to timing, we note
`that Patent Owner’s motion fails to provide any citations establishing the
`allegedly untimely service of Petitioner’s evidence in response to Patent
`Owner’s Objections to Evidence Pursuant to 37 C.F.R. § 42.64(b)(1) (Paper
`21). PO Mot. to Exclude 2, 7–8. As such, Patent Owner has not shown that
`Petitioner’s evidence served in response to Patent Owner’s objection is
`untimely. See id. Petitioner served the Shankar Declaration (Ex. 1015) in
`response to Patent Owner’s objections (Paper 21). Patent Owner
`subsequently noticed the deposition of Mr. Shankar (Paper 38), deposed him
`(Ex. 2010), and submitted a Motion for Observations on Cross Examination
`of Mr. Shankar (Paper 41). Patent Owner also acknowledges that the
`supplemental evidence served by Petitioner was in response to Patent
`Owner’s objection regarding the admissibility of AMIBIOS. PO Mot. to
`Exclude 2, 7–8. We find that Petitioner has offered insufficient basis for us
`to exclude Petitioner’s evidence based on its timing or substance.
`For the above reasons, we deny Patent Owner’s motion to exclude
`AMIBIOS and Mr. Shankar’s Declaration (Exhibit 1015). We also
`determine that Petitioner has shown by a preponderance of the evidence that
`AMIBIOS is a printed publication under 35 U.S.C. § 102(b).
`
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`3. Analysis of Prior Art Challenge based on AMIBIOS
`Petitioner contends that AMIBIOS anticipates claims 1, 9–11, 19–21,
`29–31, 39, and 40. Pet. 13–18. Petitioner provides citations to the
`Declaration of Gabriele Sartori5 (Ex. 1010) to support its contention that
`AMIBIOS discloses the limitations of the challenged claims. Id. at 16–24
`(citing Ex. 1010 ¶¶ 45, 91, 93–94, 96, 98, 102, 105, 107, 113, 161, 164).
`Petitioner also provides claim charts showing the limitations of claims 1, 9,
`10, 11, 19, 20, 21, 29, 30, 31, 39, and 40, and the corresponding disclosures
`of AMIBIOS. Pet. 18–23.
`Petitioner contends that AMIBIOS discloses “enabling interrupt
`signals at predetermined interrupt times,” as recited in claim 1, via the INT
`08h interrupt. Pet. 14–15. Similar limitations are found in independent
`claims 11, 21, and 31. Petitioner argues persuasively that the system
`disclosed in AMIBIOS enables the interrupts, performs a task during the
`interrupt, and returns to normal BIOS operations for the second task
`involving the CPU. Pet. 14–18.
`Petitioner provides sufficient support for its contention that AMIBIOS
`discloses “performing a first task in response to the interrupt signals at the
`
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`5 We are unpersuaded by Patent Owner’s argument that we should ignore
`information in the Declaration of Dr. Sartori not discussed by Petitioner
`because they are improper incorporation by reference in violation of
`37 C.F.R. § 42.6(a)(3). PO Resp. 3–4. First, we note that Patent Owner has
`not provided any examples or references to Dr. Sartori’s testimony that
`allegedly exceeds the Petition’s arguments. We also note that on the full
`record before us, Patent Owner had the opportunity to cross-examine Dr.
`Sartori on the full scope of his Declaration. See Ex. 2006. Accordingly, we
`decline Patent Owner’s request that we ignore citations to Dr. Sartori’s
`Declaration not explicitly discussed by Petitioner.
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`interrupt times” as recited in claim 1 and related claims 11, 21, and 31. Pet.
`16–17. Similarly, Petitioner provides sufficient supporting evidence that
`AMIBIOS discloses “performing a second task between the successive
`interrupt times.” Pet. 17; Ex. 1001, 14:40–41. Petitioner acknowledges that
`the ’202 patent describes the second task as “any normal BIOS operation.”
`Pet. 17 (citing Ex. 1001, 11:35–38). Petitioner identifies multiple BIOS-
`related tasks that are performed between the successive INT 08h interrupts.
`Pet. 18 (citing Ex. 1003, 10, 89; Ex. 1010 ¶¶ 96, 161).
`With respect to claims 9, 19, and 29, Petitioner has shown
`persuasively that AMIBIOS discloses “[t]he method of claim 1 wherein
`enabling the interrupt signals comprises: configuring an interrupt controller
`to generate the interrupt signals at the predetermined interrupt times,” as
`recited in claim 9 and related claims 19 and 29. Pet. 15, 20–22; Pet. Reply
`10. Petitioner has provided convincing evidence and testimony that the Intel
`8254 Programmable Interrupt Timer described in AMIBIOS discloses the
`limitations of dependent claim 9. Pet. 15, 20 (citing Ex. 1010 ¶ 98). We
`also find that Petitioner has provided persuasive evidence that dependent
`claims 10, 20, 30, 39, and 40 are disclosed in the AMIBIOS periodic
`scheduling of INT 08h. Pet. 20–23.
`For the reasons above, we find that Petitioner has presented
`convincing evidence and argument to show by a preponderance of the
`evidence that AMIBIOS discloses claims 1, 9–11, 19–21, 29–31, 39, and 40
`of the ’202 patent, as set forth in the Petition and Petitioner’s Reply. We
`address Patent Owner’s contentions regarding these challenged claims
`below.
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`Patent Owner argues that the preamble of the claims are limiting for
`independent claims 1, 11, and 21, and require “the performance of
`‘multitasking in a basic input and output system (BIOS) by a processor.’”
`PO Resp. 4. Patent Owner further argues that AMIBIOS fails to anticipate
`an interrupt that is generated or processed by the CPU as recited in the
`preamble. Id. at 5. Specifically, Patent Owner argues that INT 08h in
`AMIBIOS is generated by hardware devices and is not a processor based
`interrupt, because “‘[w]hen a hardware device or program needs the
`processor, it sends a signal or instruction to the processor, requesting a
`certain service or task.’” PO Resp. 5 (quoting Ex. 1003, 89).
`We agree with Patent Owner that the preamble of claim 1, which
`recites “multitasking in a basic input and output system (BIOS) by a
`processor” is limiting. We determine that, when read in the context of the
`claims and the patent Specification the preamble of claim 1 “give[s] life,
`meaning, and vitality” to the claims, “indicat[ing] a reliance on both the
`preamble and the claim body to define the invention.” Catalina Mktg. Int’l,
`Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) (citing
`Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868 F.2d 1251, 1257
`(Fed. Cir. 1989)); see also Boehringer Ingelheim Vetmedica, Inc. v.
`Schering-Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003) (stating that
`preamble language limits claim when it recites “the essence of the invention
`without which performance of the recited steps is nothing but an academic
`exercise”).
`With respect to the processor limitations in independent claims 1, 11,
`and 21, we agree with Petitioner that AMIBIOS discloses that INT 08H is
`enabled by a processor. Pet. Reply 3–4. We agree with Petitioner that
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`AMIBIOS discloses “a system timer hardware interrupt (IRQ0) from a
`system timer to the Intel processor” that is vectored to “Interrupt Service
`Routines (ISRs) that generally reside in the BIOS.” Pet. Reply 3–4 (citing
`Ex. 1003, 89) (emphasis omitted). We also credit the testimony of Patent
`Owner’s witness, Dr. Shahin Nazarian, who testified that the hardware
`interrupts and ISRs in AMIBIOS are executed in the processor. Ex. 1016,
`25:8–10 (agreeing that ISRs are code executed by the processor), 150:2–13
`(same), 161:15–163:17 (agreeing that “the processor would execute the INT
`08h system timer ISR” and that the hardware interrupts prompts the
`processor to execute tasks in BIOS). Accordingly, Petitioner has shown by a
`preponderance of the evidence that AMIBIOS discloses to a person of
`ordinary skill in the art that the hardware interrupt prompts the processor to
`execute tasks in BIOS, and discloses enabling “by a processor.” See Ex.
`1016, 161:15-163:18; Ex. 2006, 32:2–7; Pet. 14.
`In contrast to the preamble of independent claims 1, 11, and 21, claim
`31 does not recite “BIOS” or “multitasking” in either the preamble or the
`body of the claim. Dec. 13–14; see Ex. 1001, 14:33–42, 15:1–12, 15:45–57,
`16:23–34. At the oral hearing, Patent Owner admitted that claim 31 has a
`fatal deficiency as it does not recite the BIOS and multitasking limitations.
`Tr. at 24:14–19 (stating that “[claim 31] ha[s] a fatal deficiency of not
`specifying the BIOS. So [Patent Owner is] limiting our argument today to 1,
`11, and 21). We agree with Patent Owner’s admission that claim 31, which
`is not limited to BIOS, is anticipated by AMIBIOS. Accordingly, based on
`Patent Owner’s admission, we find that independent claim 31 and its
`dependent claims, 39 and 40, are anticipated by AMIBIOS.
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`Patent Owner further argues that Petitioner has failed to show that
`AMIBIOS discloses “performing a first task in response to the interrupt
`signals at the interrupt timers” as recited in independent claims 1, 11, 21,
`and 31. PO Resp. 5–7. Specifically, Patent Owner contends that “[t]he
`subject claims require that a first task be performed in response to the
`interrupt signals—not that the [INT 08h] signal itself performs such task.”
`PO Resp. 6.
`We are not persuaded by Patent Owner’s arguments, which fail to
`address the four tasks Petitioner describes that meet the “first task” as recited
`in the claims. Pet. Reply 5–6 (citing Pet. 16–17). For example, we agree
`with Petitioner that AMIBIOS discloses incrementing the system timer and
`running user-supplied routines as first tasks in response to the interrupt. See
`Pet. 16, 17 (citing Ex. 1003, 102); Ex. 1016, 122:15–22, 127:21–128:7,
`158:2–5. Patent Owner’s arguments are based on a requirement that
`AMIBIOS disclose directly “performing a first task in response to the
`interrupt signals at the interrupt timers,” such that there are no intermediate
`steps between the interrupt and the performance of the task. Tr. 38:7–39:11,
`40:1–42:3. We disagree that “performing a first task” as claimed is so
`limited. Indeed, Patent Owner admits the claim requires “that a first task be
`performed in response to the interrupt signals.” PO Resp. 6. We find that
`Petitioner has convincingly shown that AMIBIOS discloses tasks performed
`in response to an interrupt signal. Specifically, Petitioner demonstrates by a
`preponderance of the evidence that the INT 08h interrupt vectors to user-
`supplied routines and increments a timer, both of which disclose the claimed
`“first task” limitation of claims 1, 11, 21, and 31. Pet. Reply 6–7, 11–12;
`Pet. 17; Ex. 1003, 102; Ex. 1004, 1; Ex. 1010 ¶ 93; Ex. 1016, 163:4–17.
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`Contrary to Patent Owner’s arguments, we also do not understand
`Petitioner to assert that tasks associated with setting up the timer in
`AMIBIOS are the claimed “first task.” Petitioner argues instead that setting
`up the timer discloses “enabling interrupt signals at predetermined times” as
`recited in the claims. Pet. Reply 5. We agree with Petitioner on this point,
`finding persuasive the cross examination testimony of Patent Owner’s
`witness, Dr. Nazarian, that supports the argument that AMIBIOS discloses
`“enabling interrupt signals at predetermined times,” as recited in the
`challenged independent claims, because it discloses a programmable interval
`timer that generates system timer hardware interrupt IRQ0. Ex. 1016,
`160:15–24 (interval timer programmed by CPU), 170:15–172:4 (interval
`timer generating hardware interrupts).
`We are also not persuaded by Patent Owner’s argument that
`“housekeeping tasks” that are “unalterable, mandatory and uninterruptable”
`are not the claimed “first tasks.” PO Resp. 7. Patent Owner’s argument is
`neither persuasive nor commensurate with the scope of the claims, which
`broadly recite tasks and do not exclude the type of tasks run based on such
`attributes.
`Petitioner has also presented convincing argument and evidence that
`AMIBIOS discloses “performing a second task between successive interrupt
`times” as recited in independent claims 1, 11, and 21. Pet. 17–20; Ex. 1003,
`89; Ex. 1010 ¶ 96; Reply 9–10. We note that a preferred embodiment in the
`’202 patent describes the second task as “normal BIOS operations.”
`Ex. 1001, 11:35.6 Patent Owner’s expert agrees that POST (Power On Self
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`6 Specifically, the ’202 patent states that:
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`Test)7 is a normal BIOS operation that takes place before loading the
`operating system, and is disclosed in AMIBIOS. Ex. 1016, 185:22–186:3;
`Pet. Reply 9. Thus, Petitioner has shown by a preponderance of evidence
`that AMIBIOS discloses “the performing a second task” limitation of the
`challenged claims.
`With respect to dependent claims 10, 20, 30 and 40, which recite
`“wherein enabling the interrupt signals comprises scheduling an interval
`timer to generate the interrupt signals at the predetermined interrupt times”
`(Ex. 1001, 14:64–67), Patent Owner contends that the hardware interrupt is
`unalterable and is not scheduled or configured by AMIBIOS (PO Resp. 7–
`8). We disagree, finding that Patent Owner misreads the requirements of
`dependent claims 10, 20, 30 and 40. These dependent claims do not require
`that the hardware interrupt is alterable or configurable. Based on the record,
`we find that Petitioner has provided persuasive evidence that AMIBIOS
`schedules an interval timer (e.g., Intel 8254) to generate interrupt signals at
`the predetermined interrupt time of 18.2 times per second. Ex. 1003, 102;
`Ex. 1010 ¶ 100; Ex. 1016, 158:14–159:6; Ex. 2006, 32:5–7. The
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`The normal second task 514 includes code to perform the
`normal BIOS operations. These normal BIOS operations usually
`take longer to complete than the initial BIOS operations
`performed by the initial code 510. Examples of these normal
`BIOS operations include complete memory tests, initialization of
`peripheral devices
`such as mass
`storage controllers,
`communication interface devices.
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`Ex. 1001, 11:34–40.
`7 The ’202 patent states that “Power On Self Test (POST) refers to the
`instructions that are executed to configure and test the system hardware prior
`to loading an OS.” Ex. 1001, 3:26–28.
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`preponderance of the evidence also shows th