Trials@uspto.gov
`571.272.7822
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` Paper No. 13
`
` Filed: June 21, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., AMAZON.COM, INC.,
`SONY CORP., SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB,
`SONY MOBILE COMMUNICATIONS (USA) INC.,
`LG ELECTRONICS, INC., LG ELECTRONICS USA, INC., and
`LG ELECTRONICS MOBILECOMM USA, INC.,
`Petitioner,
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-001591
`Patent 7,296,121 B2
`____________
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and KERRY BEGLEY,
`Administrative Patent Judges.
`
`BEGLEY, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`1 Sony Corp., Sony Electronics Inc., Sony Mobile Communications AB,
`Sony Mobile Communications (USA) Inc., LG Electronics, Inc.,
`LG Electronics USA, Inc., and LG Electronics Mobilecomm USA, Inc., who
`filed a Petition in IPR2015-01376, have been joined as petitioners in the
`instant proceeding.
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`Apple Inc., HTC Corporation, HTC America, Inc., Samsung
`Electronics Co. Ltd., Samsung Electronics America, Inc.,2 and Amazon.com,
`Inc. (collectively, “Initial Petitioners”) filed a Petition requesting inter partes
`review of claims 1–3, 8, and 11–25 of U.S. Patent No. 7,296,121 B2
`(Ex. 1001, “the ’121 patent”). Pet. Pursuant to 35 U.S.C. § 314(a), we
`determined the Petition showed a reasonable likelihood that Petitioner would
`prevail in establishing the unpatentability of claims 1–3, 8, 11, and 15–25,
`and instituted an inter partes review of these claims. Paper 12 (“Inst.
`Dec.”). We, however, did not institute review of claims 12–14, because we
`determined the Petition did not show a reasonable likelihood that Petitioner
`would prevail with respect to these claims. Id. at 23–30.
`After institution, Sony Corp., Sony Electronics Inc., Sony Mobile
`Communications AB, Sony Mobile Communications (USA) Inc.,
`LG Electronics, Inc., LG Electronics USA, Inc., and LG Electronics
`Mobilecomm USA, Inc. (collectively, “Subsequent Petitioners”; and with
`Initial Petitioners, “Petitioner”) filed a Petition in IPR2015-01376,
`requesting inter partes review of claims 1–3, 8, 11, 12,3 and 15–25 of the
`
`
`2 The Petition also lists Samsung Telecommunications America, LLC
`(“STA”) as a petitioner. Paper 6 (“Pet.”), 1. After the filing of the Petition,
`however, STA merged with and into Samsung Electronics America, Inc.
`Paper 10. Thus, STA no longer exists as a separate corporate entity. Id.
`3 Subsequent Petitioners represented that they included claim 12 “merely to
`conform” to the Petition and motion for rehearing of the Institution
`Decision, regarding claim 12, that was pending before the Board and that if
`the motion was denied, they requested joinder on “all claims except
`claim 12.” IPR2015-01376, Paper 3 (“IPR2015-01376 Pet.”), 1 n.1, 33 n.5.
`Because we denied the motion, we understood Subsequent Petitioners to no
`longer maintain their challenge of claim 12 and to the extent they did, we
`determined they had not shown the IPR2015-01376 Petition warranted
`institution of review of the claim. IPR2015-01376, Paper 12, at 12–15.
`2
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`’121 patent on the same grounds as those instituted in this proceeding.
`IPR2015-01376 Pet. Subsequent Petitioners also filed a motion for joinder
`with this proceeding, which we granted. IPR2015-01376, Papers 4, 12.
`Patent Owner Memory Integrity, LLC (“Patent Owner”) filed a Patent
`Owner Response (Paper 25 (“PO Resp.”)) and a Motion to Amend (Paper 26
`(“Mot.”)). Petitioner filed a Reply to Patent Owner’s Response (Paper 35,
`“Reply”) and an Opposition to Patent Owner’s Motion to Amend (Paper 36,
`“Opp.”). Patent Owner then filed a Reply in support of its Motion to Amend
`(Paper 37, “Mot. Reply”). Petitioner also filed a Motion for Observations on
`the deposition testimony of Patent Owner’s expert. Paper 41. An oral
`hearing was held before the Board. Paper 45 (“Tr.”).
`We issue this Final Written Decision pursuant to 35 U.S.C. § 318(a)
`and 37 C.F.R. § 42.73. Having considered the record before us, we
`determine Petitioner has shown by a preponderance of the evidence that
`claims 1–3, 8, and 15–25 of the ’121 patent are unpatentable. See 35 U.S.C.
`§ 316(e). Petitioner, however, has not demonstrated by a preponderance of
`the evidence that claim 11 is unpatentable.
`I. BACKGROUND
`A. RELATED PROCEEDINGS
`The parties indicate Patent Owner has asserted the ’121 patent in
`
`numerous cases filed in the U.S. District Court for the District of Delaware.
`Pet. 1–2; Paper 8, 1–2. In addition, the ’121 patent was the subject of
`several petitions for inter partes review before the Office—IPR2015-00158,
`IPR2015-00161, IPR2015-00163, IPR2015-00172, and IPR2015-01353.
`See Paper 8, 4; IPR2015-00163, Paper 34. Of these proceedings, only
`IPR2015-00163 is ongoing and a final written decision in IPR2015-00163 is
`being issued concurrently with this Decision.
`3
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`
`B. THE ’121 PATENT
`The ’121 patent relates to techniques to reduce memory transaction
`traffic and to improve data access and cache coherency in systems with
`multiple processors connected using point-to-point links. Ex. 1001, 1:22–
`25, 2:39–51. The ’121 patent explains that cache coherency problems can
`arise in a system with multiple processors, each with an individual cache
`memory, because the system may contain multiple copies of the same data.
`Id. at 1:26–45.
`
`The ’121 patent discloses a computer system with processing nodes,
`each with a cache memory, connected by a point-to-point architecture. Id. at
`[57], 2:48–62. The system also includes a “probe filtering unit” that can
`receive a probe from a processing node. Id. at [57], 2:52–65, 5:45–47. The
`’121 patent defines a probe as “[a] mechanism for eliciting a response from a
`node to maintain cache coherency in a system.” Id. at 5:45–47.
`The probe filtering unit then can evaluate the probe based on probe
`filtering information and transmit the probe to selected processing nodes. Id.
`at [57], 2:52–3:5, 14:50–52; see id. at 28:29–58, 29:43–46. The ’121 patent
`explains that probe filtering information is “[a]ny criterion that can be used
`to reduce the number of clusters or nodes probed.” Id. at 14:50–52.
`The probe filtering unit also may be operable to accumulate responses
`from the selected processing nodes and to respond to the node from which
`the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51. Figure 18 of the
`patent is reproduced below.
`
`
`
`4
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`
`
`Figure 18 is a diagrammatic representation of a multiple processor system
`with a probe filtering unit. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`Specifically, Figure 18 depicts multiple processor system 1800 with
`processing nodes 1802a–d interconnected by point-to-point communication
`links 1808a–e. Id. at 26:58–27:1. System 1800 also includes probe filtering
`unit 1830. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`Claims 1, 16, and 25 of the ’121 patent are independent claims.
`Claim 1 is illustrative of the claimed subject matter and recites:
`1. A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated
`therewith,
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`Id. at 30:65–31:7 (line breaks added).
`
`
`
`5
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`C. INSTITUTED GROUNDS OF UNPATENTABILITY
`We instituted inter partes review of the ’121 patent on the following
`grounds of unpatentability asserted in the Petition. Inst. Dec. 30.
`Claims
`Basis
`Reference[s]
`1–3, 8, 11,
`§ 1024 U.S. Patent Application Pub. No. 2002/0053004 A1
`15, 16, 25
`(published May 2, 2002) (Ex. 1003, “Pong”)
`17–24
`§ 103 Pong and MICHAEL JOHN SEBASTIAN SMITH,
`APPLICATION-SPECIFIC INTEGRATED CIRCUITS (1997)
`(Ex. 1008, “Smith”)
`Petitioner supports its challenge with Declarations executed by Dr. Robert
`Horst on October 28, 2014 (Ex. 1014) and on December 1, 2015 (Ex. 1025).
`Patent Owner relies on a Declaration executed by Dr. Vojin Oklobdzija on
`August 11, 2015 (Ex. 2016).
`II. UNPATENTABILITY ANALYSIS
`A. LEVEL OF ORDINARY SKILL IN THE ART
`We begin our analysis by addressing the level of ordinary skill in the
`
`art. Dr. Horst and Dr. Oklobdzija agree that a person of ordinary skill in the
`art would have had at least a “bachelor’s degree in electrical engineering,
`computer engineering, or computer science” and “two years of experience in
`the design of multiprocessor systems.” Ex. 1014 ¶ 8; Ex. 2016 ¶ 8. We
`adopt this proposal as the level of ordinary skill in the art, based on the
`testimony of the parties’ experts as well as our review of the ’121 patent and
`the prior art involved in this proceeding.
`
`
`4 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112–29
`(2011), revised 35 U.S.C. §§ 102–103, effective March 16, 2013. Because
`the ’121 patent has an effective filing date before this date, we refer to the
`pre-AIA versions of §§ 102 and 103.
`
`
`
`6
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`
`B. CLAIM INTERPRETATION
`We next address the meaning of the claims. We interpret claims in an
`unexpired patent using the “broadest reasonable construction in light of the
`specification of the patent.” 37 C.F.R. § 42.100(b); see Cuozzo Speed
`Techs., LLC v. Lee, No. 15–446, slip op. at 12–20 (S.C. June 20, 2016)
`(holding that 37 C.F.R. § 42.100(b) “represents a reasonable exercise of the
`rulemaking authority that Congress delegated to the . . . Office”). Under this
`standard, we presume a claim term carries its “ordinary and customary
`meaning,” which “is the meaning that the term would have to a person of
`ordinary skill in the art” at the time of the invention. In re Translogic Tech.,
`Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). This presumption is rebutted
`when the patentee acts as a lexicographer by giving the term a particular
`meaning in the specification with “reasonable clarity, deliberateness, and
`precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`Petitioner and Patent Owner each proffer proposed constructions of
`various claim terms. Pet. 4–15; PO Resp. 1–17; Reply 1–7. In the
`Institution Decision, we construed several terms, including “states associated
`with selected ones of the cache memories.” Inst. Dec. 5–14. The parties’
`post-institution briefing presents arguments regarding our construction of
`“states” (independent claims 1, 16, and 25), in addition to the proper
`construction of “programmed” (claim 11), “accumulate responses to each
`probe” (claim 15), and “accumulating probe responses” (claim 25). See
`PO Resp. 1–17; Reply 1–7, 23. We address below the parties’ arguments
`regarding these terms. We otherwise maintain our constructions from the
`Institution Decision.
`
`
`
`7
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`1. “[S]TATES” (CLAIMS 1, 16, AND 25)
`Independent claims 1, 16, and 25 recite “probe filtering information”
`“representative of states associated with selected ones of the cache
`memories.” Ex. 1001, 31:5–7, 32:14–15, 32:51–55 (emphasis added).
`Before our Institution Decision, each party proposed a construction of the
`term “states associated with selected ones of the cache memories.” Pet. 9–
`10; IPR2015-00159, Paper 11 (“Prelim. Resp.”), 13–24. Petitioner argued
`that the term is “broad enough to encompass ‘any modes or conditions of
`selected ones of the cache memories.’” Pet. 10. Patent Owner proposed that
`the term means “‘cache coherence protocol states associated with data
`blocks stored in selected ones of the cache memories’” and that a “‘cache
`coherence protocol state’ means ‘the current state of a data block in a
`protocol used to maintain the coherency of caches, in which a data block can
`only be in one current state at a time, and in which the current state can
`transition to a different state upon one or more triggering events or
`conditions.’” Prelim. Resp. 13–14. In the Institution Decision, we did not
`adopt either party’s proposed construction, but found that “the term is not
`limited to cache coherence protocol states and is broad enough to include the
`condition of presence—i.e., what is stored in cache memory.” Inst. Dec. 10.
`In its Response, Patent Owner continues to argue that “the appropriate
`construction of states is limited to cache coherence states, and does not
`include mere presence.” PO Resp. 2. Petitioner does not agree that the term
`should be so limited. Reply 1–4. In particular, Petitioner asserts that the
`broadest reasonable construction of the term “states” is not limited to cache
`coherency states, id. at 2–4, and is “broad enough to encompass the
`condition of presence,” id. at 4.
`
`
`
`8
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`
`a. CACHE COHERENCE STATES
`The language of the independent claims “states associated with
`selected ones of the cache memories” plainly links the “states” to “cache
`memories.” Ex. 1001, 31:5–7, 32:14–15, 32:52–55. In addition, in these
`claims, the term “representative of states associated with selected ones of the
`cache memories” modifies “probe filtering information” (id. (emphasis
`added)), which the patent defines as “[a]ny criterion that can be used to
`reduce the number of clusters or nodes probed” (id. at 14:50–52). Thus, the
`recited “states” relate, not just to any aspect of the cache memory, but to the
`contents of that memory. See Inst. Dec. 7–8.
`For the reasons discussed below, however, despite the arguments and
`evidence in Patent Owner’s Response, we remain unpersuaded that the
`’121 patent supports limiting the broadest reasonable construction of “states”
`solely to cache coherence protocol states. A claim term will be interpreted
`more narrowly than its ordinary and customary meaning only under two
`circumstances: (1) the “patentee sets out a definition and acts as [its] own
`lexicographer,” or (2) the “patentee disavows the full scope of a claim term
`either in the specification or during prosecution.” Aventis Pharma S.A. v.
`Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012). To disavow claim
`scope, the specification or prosecution history must “make[] clear that the
`invention does not include a particular feature” and the feature is then
`“deemed to be outside the reach of the claims of the patent, even though the
`language of the claims, read without reference to the specification” or
`prosecution history, “might be considered broad enough to encompass the
`feature in question.” SciMed Life Sys., Inc. v. Advanced Cardiovascular
`Sys., Inc., 242 F.3d 1337, 1341 (Fed. Cir. 2001); see Aventis, 675 F.3d at
`1330. To disavow claim scope, the patentee may “includ[e] in the
`9
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`specification expressions of manifest exclusion or restriction, representing a
`clear disavowal of claim scope.” Aventis, 675 F.3d at 1330 (internal
`quotations omitted). In this context, it is not sufficient “that the only
`embodiments, or all of the embodiments, contain a particular limitation.” Id.
`Here, the relevant language in the independent claims, “states
`associated with selected ones of the cache memories,” expressly recites
`“states” alone—not cache coherency states, to which Patent Owner seeks to
`limit the term. As Petitioner points out, Patent Owner’s proposed
`construction seeks to add additional narrowing descriptive language to the
`term “states.” See Reply 2.
`Moreover, the claims do not recite “cache coherence states” or “cache
`coherence protocol states.” Dependent claim 3, which depends indirectly
`from claim 1, however, recites “a cache coherence controller” and “a cache
`coherence directory.” Ex. 1001, 31:12–14. Similarly, claim 5, another
`claim that depends indirectly from claim 1, requires a “cache coherence
`controller.” Id. at 31:24. Thus, had the patentees intended to limit “states,”
`as recited in the independent claims of the ’121 patent, to cache coherence
`states, they demonstratively could have done so by explicitly modifying the
`disputed term with “cache coherence”—but did not.5 See Reply 2–3.
`
`
`5 Patent Owner notes that the Institution Decision “preliminarily determined
`that ‘states’ in the claims of the ’121 Patent are not limited to ‘cache
`coherence protocol states,” “despite the fact that the Board determined that
`the term ‘probe’ . . . should be construed as a ‘mechanism for eliciting a
`response from a node to maintain cache coherency in a system.’”
`PO Resp. 1–2. We do not agree with Patent Owner’s implication that our
`construction of “probe” conflicts with our construction of “states.” The two
`words recite different parts of the claimed invention. Also, the ’121 patent
`expressly defines “probe” (see Ex. 1001, 5:45–47; Inst. Dec. 6), but not
`“states.” If “states” were intended to be limited to cache coherency protocol
`10
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`Turning to the written description, we do not find persuasive Patent
`Owner’s arguments that the remainder of the specification supports limiting
`“states” to cache coherency states. Rather, we agree with Petitioner that the
`’121 patent uses broad language in describing “states,” explaining that
`“particular implementations may use a different set of states” and “[t]he
`techniques of the present invention can be used with a variety of different
`possible memory line states.” Ex. 1001, 14:30–36; see Inst. Dec. 9; Pet. 9;
`Reply 2.
`Patent Owner asserts that the teachings of the ’121 patent make clear
`that its inventions are directed to the specific field of cache coherency and
`the term “state” has “a specific meaning in the field of cache coherency—a
`cache coherency state.” PO Resp. 3–4; see Tr. 63:13–64:2. As to the field
`of the ’121 patent, we find that it is directed, generally, to “data access and
`cache coherency in systems having multiple processors.” E.g., Ex. 1001,
`2:39–42. The ’121 patent explains that data access, and the disclosed
`invention, involve techniques for reducing probe traffic as well as cache
`coherency techniques. See, e.g., id. at 1:21–27 (“The present invention
`relates to accessing data in a multiple processor system. More specifically,
`the present invention provides techniques for reducing memory transaction
`traffic in a multiple processor system. Data access in multiple processor
`systems can raise issues relating to cache coherency.”); see also, e.g., id. at
`[54] (title) (“Reducing Probe Traffic in Multiprocessor Systems”); id. at
`2:45–48 (“According to the present invention, various techniques are
`
`
`states, the ’121 patent could have provided an express definition for “states,”
`as it does for “probes.” Patent Owner does not provide evidence or
`reasoning persuading us that one of ordinary skill would find the express
`definition of “probes” as somehow limiting the term “states.”
`11
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`provided for reducing traffic relating to memory transactions in multi-
`processor systems.”). Although we agree with Patent Owner that the field of
`the ’121 patent includes cache coherency, we are not persuaded that this fact
`alone limits the term “state” to “cache coherence states.”
`Patent Owner, in fact, concedes that the term “state” “may have many
`broad and different meanings . . . in the general field of computers.”
`PO Resp. 3 (citing Ex. 2016 ¶ 15). Indeed, in our Institution Decision, we
`relied on a dictionary definition of “state” from the MICROSOFT COMPUTER
`DICTIONARY (5th ed. 2002): “[t]he condition at a particular time of any of
`numerous elements of computing—a device, a communications channel, a
`network station, a program, a bit, or other element—used to report on or to
`control computer operations.” Ex. 3001, 497–98. Patent Owner agrees that
`this dictionary is directed “to the entire field of computing.” PO Resp. 3;
`Reply 4. And as Petitioner points out, Patent Owner relies on this same
`dictionary when proposing a construction for another term in the
`’121 patent—“programmed.” See PO Resp. 13; Reply 4. We disagree with
`Patent Owner’s contention that a person of ordinary skill in the art would not
`base its definition of the term “states” on the field of computers generally,
`but instead would rely on a meaning specific to the “field of cache
`coherency.”
`To begin with, Patent Owner agrees that a person of ordinary skill in
`the art would have a degree in electrical engineering, computer engineering,
`or computer science and at least two years of experience in the design of
`multiprocessor systems. Ex. 1014 ¶ 8; Ex. 2016 ¶ 8. Nothing in this
`definition points to a specific field, known as cache coherency, with its own
`terminology displacing the more general terminology used by those in the
`field of computing.
`
`
`
`12
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`Patent Owner relies on a few excerpts of the ’121 patent, which
`allegedly “demonstrate that the use of the term ‘state’ in the patent is
`directed to cache coherence protocol states.”6 PO Resp. 5–6. For example,
`Patent Owner points to the following passage as “mak[ing] it clear that the
`relevant state is a cache coherence protocol state” (id. at 5):
`It should be noted that a coherence protocol can contain several
`types of messages. In one example, a coherence protocol
`includes four types of messages; data or cache access requests,
`probes, responses or probe responses, and data packets. Data or
`cache access requests usually target the home node memory
`controller. Probes are used to query each cache in the system.
`The probe packet can carry information that allows the caches
`to properly transition the cache state for a specified line.
`
`Ex. 1001, 9:21–29 (emphases added); see PO Resp. 5 (quoting Ex. 1001,
`9:21–29). Similarly, Patent Owner cites to the specification’s statement that
`“[b]y using a coherence directory, global memory line state information
`(with respect to each cluster) can be maintained and accessed by a memory
`controller or a cache coherence controller in a particular cluster,” asserting
`
`6 We note that in IPR2015-00163, Patent Owner’s arguments addressing
`Exhibit 1009 (“Koster”) belie its position that “state” necessarily refers to a
`cache coherency state in the context of the ’121 patent. In IPR2015-00163,
`Patent Owner argues that the “mere fact” that Koster refers to his shadow tag
`memory as ‘local state memory’ does not mean that it contains ‘information
`representative of states associated with selected ones of the cache
`memories,’” as used in the ’121 patent. IPR2015-00163, Paper 31, 23.
`Patent Owner concludes that the tags “are not representative of cache
`coherency states.” Id. Essentially, Patent Owner argues in its proposed
`construction of “states” in IPR2015-00163 and this case that a person of
`ordinary skill in the art would understand the term “state” alone means
`“cache coherency state” in the context of the ’121 patent. PO Resp. 2–6;
`IPR2015-00163, Paper 31, 2–7. Yet, in IPR2015-00163, when analyzing
`Koster, which involves the same field as the ’121 patent, Patent Owner
`asserts that the same person would understand the term “state” alone does
`not mean cache coherency state, but instead means something broader.
`13
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`that this statement only makes sense if the coherence directory concerns
`solely cache coherence states. PO Resp. 5–6 (quoting Ex. 1001, 13:4–7)
`(emphases added by Patent Owner).
`We are not persuaded that these passages of the ’121 patent limit the
`term “states” as asserted by Patent Owner. Neither of the passages relied
`upon by Patent Owner actually uses the term “state” as recited in the
`challenged claims. Instead, the first passage uses the term “cache state” and
`the second uses the term “global memory line state information.” Thus,
`even if the passages describe a concept narrower than “states associated with
`selected ones of the cache memories,” as recited in the challenged claims,
`this difference can be attributed to the fact that different terms are used.
`More importantly, these passages do not expressly disclaim or disavow the
`broader scope of the claim language, particularly given the expansive
`language used elsewhere in the specification allowing states to include “a
`variety of different possible memory line states.” Ex. 1001, 14:30–36.
`Patent Owner also points to Figures 7 and 8 of the ’121 patent as
`allegedly “strongly illustrative that the ’121 patent uses ‘state’ to mean cache
`coherence protocol states.” PO Resp. 6. According to Patent Owner, the
`specification equates the word “state” with cache coherence states by
`disclosing that “the coherence directory 701 [of Figure 7] includes state
`information 713” and by stating “[i]n some embodiments, the memory line
`states are modified, owned, shared, and invalid.” Id. (quoting Ex. 1001,
`13:55–59) (emphasis added by Patent Owner). In other words, Patent
`Owner argues that because Figure 7 shows a column labeled “state,” and
`describes this column as including in some embodiments the states used in
`common cache coherence protocols, such as MOESI and MOSI, the term
`
`
`
`14
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`“state” must be equivalent to cache coherence protocol states. See
`Tr. 77:20–78:18.
`Figures 7 and 8, however, also are not persuasive as defining or
`limiting the term “state” because they are clearly described as exemplary
`embodiments. See, e.g., Ex. 1001, 3:15–18, 4:11–35, 13:44–59 (describing
`Figure 7 using the term “example” or “embodiment” at least five times),
`14:48–50, 30:57–64. We are not persuaded that Figure 7 shows anything
`more than what it purports to show—one example with a column labeled
`“state,” that may refer to “memory line states” of “modified, owned, shared,
`and invalid.” Again, nothing in this example expressly disclaims or
`disavows the broad claim language, particularly in light of other statements
`in the specification allowing states to include “a variety of different possible
`memory line states.” Id. at 14:30–36.
`Patent Owner also proffers extrinsic evidence to support its proposed
`construction of the term “state.” Extrinsic evidence is “less significant than
`the intrinsic record in determining the legally operative meaning of claim
`language.” Phillips v. AWH Corp., 415 F.3d 1303, 1317 (Fed. Cir. 2005)
`(internal citations and quotations omitted). For example, Patent Owner
`points to “one of the treatises on cache coherency,” DANIEL J. SORIN ET AL.,
`A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE (2011)
`(Ex. 2010, “Sorin”), as equating the term “state” with cache coherence
`protocol states. PO Resp. 4 (citing Ex. 2010, 88–89; Ex. 2016 ¶ 15). We do
`not find this evidence persuasive. Evidence of the use of shorthand within
`one section in one publication does not indicate that that same shorthand will
`be recognized, by a person of ordinary skill, as necessarily having the same
`meaning in other contexts.
`
`
`
`15
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`Patent Owner also points to another article, where the authors—three
`of whom are the authors of Sorin, discussed above—state that “[a]
`processor’s access to a cache block is determined by the state of that block
`in its cache, and this state is generally one of the five MOESI (Modified,
`Owned, Exclusive, Shared, Invalid) states.” PO Resp. 4–5 (citing
`Ex. 2003, 1) (emphasis added); see Reply 3–4. Again, this isolated use of a
`shorthand of “states” in a publication, with several of the same authors as the
`other cited publication, does not persuade us that this shorthand is
`universally accepted to have a particular meaning whenever a particular type
`of software is being discussed. Moreover, the use of the term “generally” in
`this statement shows that it is not limiting the term “states” to cache
`coherency states, or more specifically, MOESI states.
`Dr. Oklobdzija’s testimony, which cites and relies on this article and
`Sorin, also does not persuade us that “states” necessarily means cache
`coherency states. See Ex. 2016 ¶¶ 15–16 (citing Ex. 2010, 88–91; Ex. 2003,
`1). Thus, we are not persuaded that Patent Owner’s extrinsic evidence
`regarding ordinary meaning overcomes the intrinsic record of this case. See
`Phillips, 415 F.3d at 1318 (“[A] court should discount any expert testimony
`that is clearly at odds with the claim construction mandated by the claims
`themselves, the written description, and the prosecution history, in other
`words, with the written record of the patent.”) (internal citations and
`quotations omitted).
`In summary, we conclude that the “states” in the claim language
`“states associated with selected ones of the cache memories,” as recited in
`independent claims 1, 16, and 25 of the ’121 patent, relate to the contents of
`cache memory, but are not limited to cache coherence protocol states.
`
`
`
`16
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`
`b. PRESENCE
`Even if we agreed with Patent Owner’s assertion that the term “states”
`is limited to cache coherence states, we are persuaded by Petitioner’s
`assertions that within the field of cache coherency, a “state” may refer to a
`lack of presence, see Pet. 10; Reply 4, and that the ’121 patent and extrinsic
`evidence cited by Patent Owner demonstrate that “not present” is a cache
`coherency state and the invalid cache coherency state may signify a lack of
`presence, see Reply 4; Tr. 51:5–52:17; Ex. 1025 ¶ 25. We find unpersuasive
`Patent Owner’s arguments to the contrary. See PO Resp. 6–10.
`Patent Owner asserts that the ’121 patent teaches “‘state’ provides
`additional information about ‘a particular cached line’ that is known to
`already be ‘somewhere’ (i.e. it is alre[a]dy known to be present).’” Id. at 7.
`Patent Owner bases this assertion on a passage of the ’121 patent stating
`“because the cache coherence directory provides information about where”
`“memory lines are cached as well as their states, probes only need be
`directed toward the clusters in which the requested memory line is cached”
`and “[t]he state of a particular cached line will determine what type of
`probe is generated.” Id. (quoting Ex. 1001, 19:36–43 (emphases added by
`Patent Owner)). According to Patent Owner, this passage “plainly
`indicates” that the state of a memory line is different from where it is located
`and that a “state” only exists for a cached line. Id.
`Patent Owner also points to the ’121 patent’s discussion of an
`“occupancy vector” as demonstrating that the patent does not consider
`presence to be a state. Id. at 8–9. According to Patent Owner, the
`’121 patent’s statement that “[a]ny mechanism for tracking what clusters
`hold a copy of the relevant memory line in cache is referred to herein as an
`occupancy vector” (Ex. 1001, 14:2–4), and its treatment of the “occupancy
`17
`
`
`
`

`
`IPR2015-00159
`Patent 7,296,121 B2
`vector” differently than the “state” field in Figure 7, indicate that the
`’121 patent “understands presence and ‘state’ to be different.” PO Resp. 8–9
`(citing Ex. 1001, 13:55–57, 13:67–14:2, Fig. 7); Ex. 2016 ¶ 24.
`Intrinsic and extrinsic evidence contradicts Patent Owner’s and
`Dr. Oklobdzija’s suggestion that a cache coherency state necessarily needs
`to indicate more than whether or not a memory line is present in cache
`memory. Starting with the intrinsic evidence, as Petitioner argues, the
`’121 patent itself directly touches on the subject of presence when discussing
`cache coherency states. See Reply 4. For example, when describing ce