Trials@uspto.gov
`571-272-7822
`
`
`
`
` Paper 10
`Entered: January 3, 2018
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
`and GLOBALFOUNDRIES U.S. INC.,
`Petitioners,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`Patent 7,126,174 B2
`____________
`
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a)
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`GlobalFoundries U.S. Inc.’s motions for joinder in Cases IPR2017-00925
`and IPR2017-00926 were granted.
`
`

`

`IPR2016-01246
`Patent 7,126,174 B2
`
`
`I. BACKGROUND
`Petitioner Taiwan Semiconductor Manufacturing Company, Ltd. filed
`two Petitions requesting inter partes review of claims 1–12 and 14–18 of
`U.S. Patent No. 7,126,174 B2 (Ex. 1001, “the ’174 patent”) pursuant to
`35 U.S.C. § 311(a), as listed in the following chart.
`Case Number
`Challenged Claims Petition
`
`IPR2016-01246 1–3, 5–7, 9–12,
`and 14–18
`IPR2016-01247 1, 4, 5, 8–12, 14,
`and 16
`
`Paper 2 (“Pet.”)
`
`Paper 2
`(“-1247 Pet.”)
`
`On January 4, 2017, we instituted an inter partes review of claims
`1–12 and 14–18 on four grounds of unpatentability and consolidated
`Case IPR2016-01247 with Case IPR2016-01246 (Paper 8, “Dec. on Inst.”).2
`Patent Owner Godo Kaisha IP Bridge 1 filed a Patent Owner Response
`(Paper 14, “PO Resp.”), Petitioner filed a Reply (Paper 21, “Reply”), and
`Patent Owner filed a Sur-Reply (Paper 37, “Sur-Reply”), pursuant to our
`authorization (Paper 28). Petitioner filed a Motion to Exclude (Paper 29,
`“Pet. Mot.”) certain evidence submitted by Patent Owner. Patent Owner
`filed an Opposition (Paper 39, “PO Mot. Opp.”) and Petitioner filed a Reply
`(Paper 42, “Pet. Mot. Reply”). Patent Owner filed a Motion to Exclude
`(Paper 32, “PO Mot.”) certain evidence submitted by Petitioner. Petitioner
`
`
`2 On June 9, 2017, we granted motions for joinder filed by GlobalFoundries
`U.S. Inc. (“GlobalFoundries”) in Cases IPR2017-00925 and
`IPR2017-00926, and authorized GlobalFoundries to participate in this
`proceeding only on a limited basis. See Paper 20; IPR2017-00925,
`Paper 13; IPR2017-00926, Paper 12. Although the papers referenced herein
`were filed by Taiwan Semiconductor Manufacturing Company, Ltd., we
`refer to both entities as “Petitioner” throughout this Decision.
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`IPR2016-01246
`Patent 7,126,174 B2
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`filed an Opposition (Paper 40, “Pet. Mot. Opp.”) and Patent Owner filed a
`Reply (Paper 41, “PO Mot. Reply”). An oral hearing was held on August 7,
`2017, and a transcript of the hearing is included in the record (Paper 46,
`“Tr.”).3
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 1–12 and 14–18 are unpatentable.
`
`
`A. The ’174 Patent
`The ’174 patent discloses a “semiconductor device including
`transistors and connection[s] between the transistors for constituting
`[a large-scale integration (LSI) integrated circuit (IC)] with high integration
`and a decreased area.” Ex. 1001, col. 1, ll. 13–16. At the time of the
`’174 patent, various improvements had been made in semiconductor
`manufacturing due to “increasing demands for more refinement of the
`semiconductor device.” Id. at col. 1, ll. 17–22. The ’174 patent describes
`one known method of forming an isolation structure (for shielding devices
`from each other on a substrate) known as Local Oxidation of Silicon
`(LOCOS), which was “conventionally adopted in view of its simpleness and
`low cost.” Id. at col. 1, ll. 22–25. The LOCOS isolation method involves
`selective oxidation of a silicon substrate, but has a disadvantage in that it
`results in a “bird’s beak” overhanging area of silicon dioxide. Id. at col. 1,
`ll. 29–31. “As a result, the dimension of a transistor is changed because an
`
`
`3 Pursuant to our authorization provided to the parties by email, the parties
`filed a joint errata to the hearing transcript (Paper 47).
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`Patent 7,126,174 B2
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`insulating film of the isolation invades [the] transistor region against the
`actually designed mask dimension.” Id. at col. 1, ll. 31–34. According to
`the ’174 patent, compared to LOCOS, “trench buried type isolation” (or
`“trench isolation”) was determined to be “more advantageous for
`manufacturing a refined semiconductor device.” Id. at col. 1, ll. 25–28.
`The ’174 patent describes a “conventional semiconductor device”
`with a trench isolation structure “whose top surface is flattened so as to be at
`the same level as the top surface of the silicon substrate” (as shown in
`Figure 17) or whose top surface is higher than the surface of the silicon
`substrate (as shown in Figure 20(e)). Id. at col. 1, l. 52–col. 2, l. 6 (structure
`2b), col. 4, l. 16–col. 5, l. 11 (trench isolation 105a). By using the
`“conventional trench isolation” structure, “the dimensional change of the
`source/drain region can be suppressed because the bird’s beak” created using
`LOCOS is avoided. Id. at col. 4, ll. 16–19, col. 5, ll. 12–17. According to
`the ’174 patent, using the trench isolation method caused various problems
`of its own due to the etching required. Id. at col. 5, ll. 21–58.
`The ’174 patent describes various embodiments of semiconductor
`devices and methods of manufacturing the same. The manufacturing
`process for Embodiment 10 is depicted in the sequence of Figures 12,
`13(a)–(e), and 15(a)–(f). Id. at col. 21, ll. 33–34, col. 26, ll. 36–45 (referring
`to the previously described process of Embodiment 8).
`
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`
`Petitioner provides on page 13 of the Petition a colored and annotated
`version of Figure 15(f) of the ’174 patent, reproduced below, which is
`consistent with the ’174 patent’s disclosure.
`
`
`The figure above depicts a device including isolation 2b, which is the result
`of forming a trench in silicon substrate 1 and filling it with insulating
`material. Id. at col. 21, ll. 39–50, col. 22, ll. 34–44. “[E]lectrode sidewalls
`32a, interconnection sidewalls 32b and a step sidewall 32c each having an
`L-shape remain on the sides of the gate electrode 4a, the gate
`interconnection 4b and the step portion, respectively.” Id. at col. 27, ll. 4–8.
`The ’174 patent describes various advantages of forming “L-shaped
`sidewalls” in the manner disclosed. Id. at col. 27, ll. 34–47.
`
`
`B. Illustrative Claim
`Claim 1 of the ’174 patent recites:
`1. A semiconductor device, comprising:
`a trench isolation surrounding an active area of a
`semiconductor substrate;
`a gate insulating film formed over the active area;
`a gate electrode formed over the gate insulating film;
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`
`first L-shaped sidewalls formed over the side surfaces of
`the gate electrode;
`first silicide layers formed on regions located on the sides
`of the first L-shaped sidewalls within the active area
`an interconnection formed on the trench isolation; and
`second L-shaped sidewalls formed over the side surfaces
`of the interconnection.
`
`
`C. Prior Art
`The pending grounds of unpatentability in the instant inter partes
`review are based on the following prior art:
`U.S. Patent No. 4,506,434, issued Mar. 26, 1985
`(Ex. 1010, “Ogawa”);
`U.S. Patent No. 5,021,353, issued June 4, 1991 (Ex. 1017,
`“Lowrey”);
`U.S. Patent No. 5,153,145, issued Oct. 6, 1992 (Ex. 1002,
`“Lee”); and
`U.S. Patent No. 5,539,229, filed Dec. 28, 1994, issued July
`23, 1996 (Ex. 1015, “Noble”).
`
`
`D. Pending Grounds of Unpatentability
`The instant inter partes review involves the following grounds of
`unpatentability:
`References
`Lee and Noble
`
`Claims
`Basis
`35 U.S.C. § 103(a)4 1–3, 5–7, 9–12,
`and 14–18
`
`
`4 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
`challenged claims of the ’174 patent have an effective filing date before the
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`Patent 7,126,174 B2
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`
`References
`Lee and Ogawa
`
`Claims
`Basis
`35 U.S.C. § 103(a) 1–3, 5–7, 9–12,
`and 14–18
`35 U.S.C. § 103(a) 1, 4, 5, 8–12, 14,
`and 16
`Lowrey and Ogawa 35 U.S.C. § 103(a) 1, 4, 5, 8–12, 14,
`and 16
`
`Lowrey and Noble
`
`
`II. ANALYSIS
`A. Claim Interpretation
`The ’174 patent expired on July 24, 2016 (after the filing of the
`Petitions). We previously granted Patent Owner’s motions requesting a
`district court-type claim interpretation approach under 37 C.F.R.
`§ 42.100(b). Dec. on Inst. 6, 28. In district court, claim terms are given
`their plain and ordinary meaning as would be understood by a person of
`ordinary skill in the art at the time of the invention and in the context of the
`entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed.
`Cir. 2005) (en banc). “There are only two exceptions to this general rule:
`1) when a patentee sets out a definition and acts as his own lexicographer, or
`2) when the patentee disavows the full scope of a claim term either in the
`specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am.
`LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`Patent Owner proposes various interpretations that were adopted by
`the district court in a related case where Patent Owner asserted the
`’174 patent against another party. PO Resp. 41–43; see Ex. 3001, 7–11,
`
`
`effective date of the applicable AIA amendments, we refer to the pre-AIA
`versions of 35 U.S.C. §§ 102 and 103.
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`App’x A. Patent Owner, however, does not base any of its arguments in its
`Response on those interpretations or explain how they impact the analysis of
`the challenged claims. As in the Decision on Institution, we conclude that
`no claim terms require explicit interpretation. See Dec. on Inst. 7.
`Nevertheless, we have reviewed the district court’s interpretations and
`conclude that they are both reflective of the plain and ordinary meaning of
`the terms and consistent with our analysis of the prior art herein.
`
`
`B. Principles of Law
`To prevail in challenging claims 1–12 and 14–18 of the ’174 patent,
`Petitioner must demonstrate by a preponderance of the evidence that the
`claims are unpatentable. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d). A claim
`is unpatentable for obviousness if, to one of ordinary skill in the pertinent
`art, “the differences between the subject matter sought to be patented and the
`prior art are such that the subject matter as a whole would have been obvious
`at the time the invention was made.” KSR Int’l Co. v. Teleflex Inc., 550 U.S.
`398, 406 (2007) (quoting 35 U.S.C. § 103(a)). The question of obviousness
`is resolved on the basis of underlying factual determinations, including “the
`scope and content of the prior art are to be determined; differences between
`the prior art and the claims at issue are to be ascertained; and the level of
`ordinary skill in the pertinent art resolved.”5 Graham v. John Deere Co.,
`383 U.S. 1, 17–18 (1966).
`
`
`5 Additionally, secondary considerations, such as “commercial success, long
`felt but unsolved needs, failure of others, etc., might be utilized to give light
`to the circumstances surrounding the origin of the subject matter sought to
`be patented. As indicia of obviousness or nonobviousness, these inquiries
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`Patent 7,126,174 B2
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`
`A patent claim “is not proved obvious merely by demonstrating that
`each of its elements was, independently, known in the prior art.” KSR,
`550 U.S. at 418. An obviousness determination requires finding “both ‘that
`a skilled artisan would have been motivated to combine the teachings of the
`prior art references to achieve the claimed invention, and that the skilled
`artisan would have had a reasonable expectation of success in doing so.’”
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
`1367–68 (Fed. Cir. 2016) (citation omitted); see KSR, 550 U.S. at 418
`(for an obviousness analysis, “it can be important to identify a reason that
`would have prompted a person of ordinary skill in the relevant field to
`combine the elements in the way the claimed new invention does”).
`A motivation to combine the teachings of two references can be “found
`explicitly or implicitly in market forces; design incentives; the ‘interrelated
`teachings of multiple patents’; ‘any need or problem known in the field of
`endeavor at the time of invention and addressed by the patent’; and the
`background knowledge, creativity, and common sense of the person of
`ordinary skill.” Plantronics, Inc. v. Aliph, Inc., 724 F.3d 1343, 1354 (Fed.
`Cir. 2013) (citation omitted). Further, an assertion of obviousness “cannot
`be sustained by mere conclusory statements; instead, there must be some
`articulated reasoning with some rational underpinning to support the legal
`conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn, 441
`F.3d 977, 988 (Fed. Cir. 2006)); In re Nuvasive, Inc., 842 F.3d 1376, 1383
`(Fed. Cir. 2016) (a finding of a motivation to combine “must be supported
`by a ‘reasoned explanation’” (citation omitted)).
`
`
`may have relevancy.” Graham, 383 U.S. at 17–18. The record, however,
`lacks any such evidence.
`
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`
`C. Level of Ordinary Skill in the Art
`Petitioner argues6 that a person of ordinary skill in the art at the time
`of the ’174 patent would have had “(1) the equivalent of a Master of Science
`degree from an accredited institution in electrical engineering, materials
`science, physics, or the equivalent; (2) a working knowledge of
`semiconductor processing technologies for integrated circuits; and (3) at
`least two years of experience in related semiconductor processing analysis,
`design, and development.” Pet. 16 (citing Ex. 1004 ¶ 72).7 Patent Owner
`argues that a person of ordinary skill in the art would have had “at least a
`Bachelor’s degree in Electrical, Materials, Mechanical, or Chemical
`Engineering, or a related degree, and at least two years of experience
`working in semiconductor processing and fabrication, semiconductor
`equipment manufacturing, or semiconductor materials.” PO Resp. 23 (citing
`Ex. 2012 ¶ 29). Patent Owner disputes Petitioner’s proposed definition as
`not requiring any experience with “semiconductor processing and
`fabrication.” Id. at 24. According to Patent Owner, “[d]esign is different
`from fabrication” and “actual fabrication experience is an important
`component to a [person of ordinary skill in the art’s] understanding of what
`can practically, rather than theoretically be fabricated.” Id.
`
`
`6 Petitioner makes a number of similar arguments in both of its Petitions. As
`to these arguments, we refer only to the papers filed in Case IPR2016-01246
`for ease of reference.
`7 We previously authorized the parties to file corrected versions of three
`declarations and expunged the original versions. See Dec. on Inst. 7 n.4;
`Paper 18. Accordingly, we refer herein to the versions of Exhibit 1004 filed
`by Petitioner on September 13, 2016 (now numbered as Exhibits 1004 and
`1024), and the version of Exhibit 2012 filed by Patent Owner on June 8,
`2017.
`
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`
`Based on the record developed during trial, including our review of
`the ’174 patent and the types of problems and solutions described in the
`’174 patent and cited prior art, we agree with Petitioner’s assessment of the
`level of ordinary skill in the art and apply it for purposes of this Decision.
`Patent Owner’s proposed definition is overly broad. For example, it requires
`experience with semiconductor processing and fabrication, equipment
`manufacturing, “or” materials. Id. Thus, an individual having only general
`experience with semiconductor materials would meet the requirement.
`Petitioner’s definition, on the other hand, is more specifically directed
`to the technology described in the ’174 patent, requiring both knowledge of
`“semiconductor processing technologies for integrated circuits” and
`“experience in related semiconductor processing analysis, design, and
`development.” Pet. 16 (emphases added); see Ex. 1001, col. 1, l. 13–col. 11,
`l. 9 (disclosing that “[t]he present invention relates to a semiconductor
`device including transistors and connection between the transistors” and
`describing previous designs of semiconductor devices with high integration
`and high performance, issues with previous designs, and potential solutions);
`Ex. 1004 ¶¶ 41–63 (testifying as to the state of the art of metal-oxide-
`semiconductor field-effect transistors (MOSFETs) and isolation structures,
`including the industry’s movement from LOCOS isolation to shallow trench
`isolation (STI), by the time of the ’174 patent). It also requires practical
`experience (“working knowledge” of processing technologies and
`experience in “related” analysis, design, and development), contrary to
`Patent Owner’s argument. See PO Resp. 24. Finally, given the disclosures
`in the ’174 patent and cited prior art, we agree with Petitioner that a Master
`of Science degree (or equivalent) in the relevant area better reflects the level
`
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`Patent 7,126,174 B2
`
`of education and training that an ordinarily skilled artisan would have
`possessed at the time than a Bachelor’s degree, as Patent Owner contends.
`
`
`D. Obviousness Ground Based on Lee and Noble
`(Claims 1–3, 5–7, 9–12, and 14–18)
`1. Lee
`Lee describes a “field effect transistor with a gate stack formed upon a
`semiconductor substrate.” Ex. 1002, col. 1, ll. 57–59. “During fabrication,
`three material layers are formed over the gate stack and upon the substrate.
`At least the outer two material layers are sequentially anisotropically etched,
`creating two spacers adjacent the gate stack (and gate runners).” Id. at
`col. 1, ll. 59–63. Lee describes a fabrication process depicted in Figures
`11–15. Figure 15 of Lee is reproduced below.
`
`
`The device shown above includes, inter alia, field oxide 113 formed on
`substrate 111, and spacer layer 121 of silicon nitride or silicon oxynitride.
`Id. at col. 6, ll. 47–51, col. 7, ll. 6–16.
`
`
`2. Noble
`Noble describes “shallow trench isolation (STI) in which the
`insulating material is raised above the surface of the semiconductor.”
`
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`Ex. 1015, col. 1, ll. 8–10. Noble describes a fabrication process depicted in
`Figures 9–13. Figure 13 of Noble is reproduced below.
`
`
`The device shown above includes, inter alia, raised STI 30, created by
`etching to form a trench that is filled with insulating material. Id. at col. 4,
`ll. 40–46, Figs. 3–4.
`
`
`3. Claim 1
`a. Whether Lee and Noble Collectively Teach
`All of the Limitations of Claim 1
`Petitioner explains in detail how Lee8 and Noble collectively teach
`every limitation of claim 1, relying on the testimony of Sanjay Kumar
`Banerjee, Ph.D., as support. Pet. 21, 30–44 (citing Ex. 1004 ¶¶ 98–126).
`Specifically, Petitioner relies on Lee as teaching all of the limitations other
`than a “trench isolation.” Id. Petitioner argues that Lee’s disclosed device
`has an isolation (i.e., field oxide 113) surrounding an active area of a
`semiconductor substrate (i.e., substrate 111), a “gate insulating film” (i.e.,
`gate oxide 115) formed over the active area, a “gate electrode” (i.e., layer
`117 above the source and drain) formed over gate oxide 115, “first L-shaped
`
`8 Lee was not considered during prosecution of the ’174 patent. See
`Ex. 1001, (56).
`
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`sidewalls” (i.e., layer 121) formed over the side surfaces of layer 117, “first
`silicide layers” (described in Lee but not shown explicitly in Figure 15)
`formed on the sides of the first L-shaped sidewalls within the active area, an
`“interconnection” (i.e., layer 117 above field oxide 113), and “second
`L-shaped sidewalls” (i.e., layer 121) formed over the side surfaces of the
`interconnection. Id. (citing Ex. 1002, col. 3, ll. 9–11, col. 7, ll. 5–16
`(disclosing that “spacers 19 and 21 (which are nested beneath spacer 23)
`have a generally ‘L-shaped’ appearance (in cross-section),” and layer 121 is
`formed “in a manner analogous to that depicted” in the figures depicting
`spacers 19 and 21)). Petitioner provides on page 18 of the Petition the
`following colored and annotated version of Figure 15 of Lee, which we find
`is consistent with Lee’s disclosure.
`
`
`The figure above depicts Lee’s device including field oxide 113, which is
`formed using LOCOS rather than trench isolation. Id. at 32–33.
`Petitioner relies on Noble as teaching a “trench isolation,” citing
`Noble’s description of STI 30. Id. at 32. Petitioner provides on page 19 of
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`the Petition the following colored and annotated version of Figure 13 of
`Noble, which we find is consistent with Noble’s disclosure.
`
`
`The figure above depicts Noble’s STI 30, as well as various components that
`are very similar to those of Lee, such as the gate electrode, interconnection,
`gate dielectric, source, drain, and silicide regions. Id. at 26–28 (describing
`the similar structures of Lee and Noble), 32–33.
`As to the combined teachings of the references, Petitioner’s position is
`that a person of ordinary skill in the art would have been motivated to
`replace Lee’s LOCOS isolation with Noble’s STI. Id. at 21 (arguing that a
`person of ordinary skill in the art “would have understood that Noble’s STI
`was a known substitute for Lee’s LOCOS isolation,” and “[t]he combined
`teachings discussed in [the Petition] refer to the teachings of Lee, with its
`LOCOS isolation replaced by Noble’s STI”), 31–33 (relying on Noble for
`the “trench isolation” limitation), 40–42 (arguing that Lee teaches an
`“interconnection” that would be on the “trench isolation” as taught by
`Noble). Although the references have numerous features in common,
`Petitioner’s obviousness ground is premised on only one change needing to
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`be made to Lee to render the claim obvious—replacing the LOCOS isolation
`in Lee’s device (field oxide 113) with the trench isolation of Noble (STI 30).
`See id. Petitioner’s arguments as to how Lee and Noble collectively teach
`every limitation of claim 1 are supported by the testimony of Dr. Banerjee
`and are persuasive. See Pet. 30–44; Ex. 1004 ¶¶ 98–126.
`Patent Owner makes four arguments regarding the combined
`teachings of the references. First, Patent Owner argues that the combined
`device based on the teachings of Lee and Noble would not have “second
`L-shaped sidewalls,” as recited in claim 1. PO Resp. 70–72. Patent Owner
`contends that the purpose of the alleged second sidewalls in Lee (layer 121
`shown in red in the figure above) is to insulate the “gate runner” (layer 117)9
`
`9 Lee refers to the portion of layers 115, 117, and 118 above field oxide 113
`as “gate level runner 203” or “runner 203”:
`Turning to FIG. 12, it may be noted that layers 118, 117,
`and 115 have been patterned to produce gates 201 and 205
`together with runner 203 which extends over field oxide 113.
`Thus, it will be noted that FIGS. 12–15 depict the formation of
`two adjacent
`transistors separated by field oxide 113.
`Furthermore, gate level runner 203 extends along field oxide
`113. Gate level runner 203 may be connected (although not
`shown in the particular cross-section of FIG. 12) to gate 201 or
`205 or to the gate, source, or drain of some other transistor (not
`shown).
`Ex. 1002, col. 6, l. 62–col. 7, l. 4; see also id. at col. 7, l. 40–col. 8, l. 5
`(“The presence of protective nitride layer 118 together with nitride layer 121
`which flanks runner 203 prevents electrical contact between patterned layer
`170 and the conductive polysilicon heart 117' of runner 203. . . . Thus, the
`inventive structure has facilitated the formation of a sub-gate level
`interconnection between junction regions of different transistors
`(i.e., a connection formed prior to passivation dielectric deposition and
`contact window opening) without the possibility of shorting to a gate
`runner.”).
`
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`so that conductive layer 170 can go over it without shorting, but “if the
`trench isolation of Noble is substituted for the LOCOS isolation of Lee, the
`necessary result is that there will be no gate runner on the trench isolation,
`and therefore no need for the second sidewalls on top of the trench
`isolation.” Id. (emphasis omitted). We are not persuaded. Petitioner relies
`on Lee, which discloses an “interconnection” (i.e., layer 117) and “second
`L-shaped sidewalls” (i.e., layer 121), not Noble. Pet. 21, 40–44. Regardless
`of whether there would be a “need” for the sidewalls, Lee discloses them.
`Patent Owner and Dr. Schubert also do not explain sufficiently why it would
`be “necessary” to remove layer 117 on top of the isolation if Lee’s LOCOS
`isolation were replaced with Noble’s STI. See PO Resp. 72; Ex. 2012
`¶¶ 215–222.
`Second, and similar to the preceding argument, Patent Owner asserts
`that any sidewalls on the side surfaces of the interconnection would not be
`“L-shaped” because Noble’s gate stack and interconnection stack have
`different heights, and fabricating “second L-shaped sidewalls” (i.e.,
`“sidewalls that substantially resemble a capital ‘L’ or its mirror image”) is
`“highly problematic and would require re-engineering of Lee’s sidewall
`fabrication module.” PO Resp. 73–78. Patent Owner contends that Lee’s
`sidewalls would not be L-shaped “[g]iven the necessarily shorter height of
`the interconnect on top of the trench isolation.” Id. at 78. Again, Petitioner
`relies on Lee, not Noble, for the “interconnection” and “second L-shaped
`sidewalls” limitations of claim 1. Pet. 40–44. Substituting Noble’s STI in
`place of Lee’s LOCOS isolation merely modifies what is below Lee’s
`interconnection.
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`Third, Patent Owner argues that Lee in combination with Noble does
`not teach “first silicide layers formed on regions located on the sides of the
`first L-shaped sidewalls within the active area,” as recited in claim 1.
`PO Resp. 79–81. Petitioner relies on Lee for this limitation. Pet. 38–40.
`Lee teaches “forming silicide regions 51 [and] 53, . . . respectively, above
`junctions 25 and 27,” shown in Figures 7–10, then states in connection with
`its second disclosed process that “[s]hould salicidation be desired over
`source/drain regions 300, 301, and 302 it may also be performed in a manner
`analogous to that depicted in FIG. 9.” Ex. 1002, col. 4, ll. 44–51, col. 7,
`ll. 22–25. Petitioner provides the following annotated versions of Figures 9
`and 15 (Pet. 39–40) showing the relevant silicide layers.
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`The annotated figures above depict silicide layers in red formed on the sides
`of the L-shaped sidewalls. Patent Owner acknowledges that Figure 9 has the
`recited silicide layers, but notes that it has no interconnection, and Figure 15
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`has an interconnection but no silicide layers. PO Resp. 79. According to
`Patent Owner, it is unclear where the silicide layers would be in Figures
`14 and 15 because Lee states that they are formed “over source/drain regions
`300, 301, and 302” but does not label those areas. Id. at 79–80. Patent
`Owner argues that
`because the exposed portions of the source/drain regions closest
`to the LOCOS isolation in Fig. 14 are much smaller than the
`exposed portions of the source/drain region farthest from the
`LOCOS isolation in Fig. 14, the inventors of Lee might have
`meant that only those two regions are intended to have silicide
`on them. In other words, a silicide layer would be formed on
`only one side of the gate electrode, and not on both sides of the
`gate electrode, while the claim requires silicide layers formed on
`both sides of the L-shaped sidewalls.
`Id. at 80–81 (citing Ex. 2012 ¶¶ 234–236). Patent Owner further argues that
`“it is impossible to know what the dimensions of the device proposed by
`Petitioner would be to determine where silicide layers would be appropriate
`without knowing exactly how the trench isolation of Noble would be
`inserted” in place of the LOCOS isolation of Lee. Id. at 81 (citing Ex. 2012
`¶ 237).
`We are not persuaded of any ambiguity in Lee. Figure 9 of Lee shows
`silicide layers 51 and 53 on the sides of L-shaped sidewalls (i.e., layer 21).
`Figure 15 need not depict such layers, as the textual description that they
`may be created “in a manner analogous to that depicted in FIG. 9” is
`sufficient. See Ex. 1002, col. 7, ll. 22–25; Seachange Int’l, Inc. v. C-COR
`Inc., 413 F.3d 1361, 1380 (Fed. Cir. 2005) (finding that a figure is not
`necessary because “disclosing the embodiment in textual form is enough”).
`Formed in an “analogous” manner, the silicide layers would be located on
`the sides of the L-shaped sidewalls (i.e., layer 121) above the source and
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`drain regions (shown as semicircles10 but not labeled) in Figure 15, just as
`they are located on the sides of the L-shaped sidewalls (i.e., layer 21) above
`junctions 25 and 27 in Figure 9. Further, we agree with Petitioner’s
`explanation that the dimensions of the combined device based on Lee and
`Noble would not impact where the silicide layers are located, as “the
`openings used to define the source/drain ion implant regions also define
`where the source/drain silicide forms” in a normal self-aligned silicide
`process. See Reply 44; Ex. 1057 ¶ 150 (citing Ex. 1045, 398).
`Fourth, pointing to Petitioner’s annotated version of Figure 15 above,
`Patent Owner argues that the figure “shows red-colored pinpoint spots of
`indeterminate size or dimension,” which “would run in a line (wire or
`cylinder) along the width of the device.” PO Resp. 81–82. According to
`Patent Owner, “[a] line is not a ‘layer.’” Id. at 82. We are not persuaded.
`Patent Owner does not explain in any detail what level of thickness would
`differentiate a “line” from a “layer.” Moreover, Lee does not describe
`components 51 and 53 in Figure 9 as “lines,” but rather “silicide regions,”
`and states that salicidation may be performed in an “analogous” manner in
`Figures 14 and 15. Ex. 1002, col. 4, ll. 44–51, col. 7, ll. 22–25; see
`PO Resp. 85 (agreeing that Figure 9 “shows a silicide layer”). We find that
`this is a sufficient disclosure of silicide “layers” as recited in claim 1.
`Thus, we are persuaded that Lee and Noble collectively teach every
`limitation of claim 1.
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`10 An annotated version of Figure 15 showing the source/drain regions in
`Figure 15 appears on page 49 of the Petition.
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`b. Whether a Person of Ordinary Skill in the Art Would Have Been
`Motivated to Combine Lee and Noble and Would Have Had a
`Reasonable Expectation of Success in Doing So
`Petitioner provides ample explanation as to why a person of ordinary
`skill in the art would have been motivated to replace Lee’s LOCOS isolation
`with a trench isolation, based on the teachings of Noble. Pet. 21–30.
`Petitioner’s assertions are supported by the references themselves, the state
`of the art at the time of the ’174 patent, and the testimony of Dr. Banerjee.
`See id. (citing Ex. 1004 ¶¶ 82–97).
`First, Petitioner explains the history of the art, where LOCOS was
`“cheaper and simpler” and the bird’s beak problem “was not a major
`detriment to device density yet” in October 1989 at the time that Lee was
`filed, but by the mid-1990s, the industry had begun moving away from
`LOCOS and toward trench isolation. Id. at 22; see Ex. 1004 ¶¶ 48–5