Inter Partes Review
`United States Patent No. RE41,980
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`Taiwan Semiconductor Manufacturing Company Limited
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`Patent Owner
`
`
`
`Inter Partes Review No. IPR2016-01331
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES
`PATENT NO. RE41,980
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`
`
`
`
`

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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF CONTENTS
`
`I.
`
`PRELIMINARY STATEMENT ................................................................... 1
`
`II. TECHNOLOGICAL BACKGROUND....................................................... 3
`
`A.
`
`Integrated Circuits ................................................................................. 3
`
`B. Dielectric Materials ............................................................................... 5
`
`C.
`
`Bonding Pads ......................................................................................... 9
`
`III. THE ’980 PATENT ......................................................................................11
`
`A. Overview of the ’980 Patent ................................................................11
`
`B.
`
`Challenged Claims ..............................................................................16
`
`IV. STATEMENT OF PRECISE RELIEF REQUESTED ...........................18
`
`A.
`
`B.
`
`C.
`
`D.
`
`Claims for Which Review is Requested ..............................................18
`
`Statutory Grounds of Challenge ..........................................................19
`
`Level of Ordinary Skill .......................................................................19
`
`Claim Construction..............................................................................19
`
`V. CLAIMS 18, 19, 30-36, AND 47-51 OF THE ’980 PATENT ARE
`UNPATENTABLE OVER THE PRIOR ART .........................................20
`
`A. Disclosures of the Prior Art .................................................................20
`
`1.
`
`2.
`
`Ting ...........................................................................................20
`
`Jeng ...........................................................................................22
`
`B.
`
`Ting anticipates claims 18, 19, 30-36, and 47-51 ...............................24
`
`1.
`
`2.
`
`3.
`
`Ting anticipates claims 18 and 35 .............................................24
`
`Ting anticipates claims 19 and 36 .............................................45
`
`Ting anticipates claims 30 and 47 .............................................46
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`Inter Partes Review
`United States Patent No. RE41,980
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`4.
`
`5.
`
`6.
`
`7.
`
`Ting anticipates claims 31 and 48 .............................................47
`
`Ting anticipates claims 32 and 49 .............................................48
`
`Ting anticipates claims 33 and 50 .............................................48
`
`Ting anticipates claims 34 and 51 .............................................50
`
`C.
`
`The combined teachings of Ting and Jeng render claims 18, 19,
`30-36, and 47-51 obvious ....................................................................51
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Claims 18 and 35 are obvious over the Ting-Jeng
`combination ...............................................................................52
`
`Claims 19 and 36 are obvious over the Ting-Jeng
`combination ...............................................................................59
`
`Claims 30 and 47 are obvious over the Ting-Jeng
`combination ...............................................................................63
`
`Claims 31 and 48 are obvious over the Ting-Jeng
`combination ...............................................................................64
`
`Claims 32-34 and 49-51 are obvious over the Ting-Jeng
`combination ...............................................................................64
`
`VI. MANDATORY NOTICES .........................................................................65
`
`A.
`
`B.
`
`C.
`
`D.
`
`Real Party-in-Interest ..........................................................................65
`
`Related Matters ....................................................................................65
`
`Lead and Back-Up Counsel .................................................................65
`
`Service Information .............................................................................66
`
`VII. CERTIFICATION UNDER 37 C.F.R. § 42.24(d) ....................................66
`
`VIII. PAYMENT OF FEES .................................................................................66
`
`IX. TIME FOR FILING PETITION ...............................................................66
`
`X. GROUNDS FOR STANDING ....................................................................67
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`XI. CONCLUSION ............................................................................................67
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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`American Calcar, Inc. v. American Honda Motor Co.,
`651 F.3d 1318 (Fed. Cir. 2011) .......................................................................... 38
`
`In re Crish,
`393 F.3d 1253 (Fed. Cir. 2004) .................................................................... 36, 47
`
`In re Cronyn,
`890 F.2d 1158 (Fed. Cir. 1989) ............................................................................ 7
`
`Godo Kaisha IP Bridge 1 v. Broadcom Limited et al.,
`Case No. 2-16-cv-00134 (E.D. Tex. February 14, 2016) ................................... 65
`
`In re Hall,
`781 F.2d 897 (Fed. Cir. 1986) .............................................................................. 7
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 51
`
`Ex parte Masham,
`2 U.S.P.Q.2d 1647 (Bd. Pat. App. & Inter. 1987) .............................................. 38
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 19
`
`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1997) .......................................................................... 37
`
`In re Spada,
`911 F.2d 705 (Fed. Cir. 1990) ...................................................................... 38, 47
`
`Upsher-Smith Labs., Inc. v. PamLab L.L.C.,
`412 F.3d 1319 (Fed. Cir. 2005) .......................................................................... 49
`
`Verdegaal Bros. v. Union Oil Co. of California,
`814 F.2d 628 (Fed. Cir. 1987) ............................................................................ 47
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`Inter Partes Review
`United States Patent No. RE41,980
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`Statutes
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`35 U.S.C. § 102 ...................................................................................... 19, 20, 22, 35
`
`35 U.S.C. § 103 ........................................................................................................ 19
`
`35 U.S.C. § 311 ........................................................................................ 2, 18, 19, 66
`
`35 U.S.C. §§ 312–319 ................................................................................................ 2
`
`Regulations
`
`37 C.F.R. § 42.15 ..................................................................................................... 66
`
`37 C.F.R. § 42.24 ..................................................................................................... 66
`
`37 C.F.R. § 42.100 ............................................................................................... 2, 20
`
`37 C.F.R. § 42.101 ................................................................................................... 67
`
`37 C.F.R. § 42.102 ................................................................................................... 66
`
`37 C.F.R. § 42.103 ................................................................................................... 66
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`Other Authorities
`
`M.P.E.P. § 2114(II) .................................................................................................. 38
`M.P.E.P. § 2143 ....................................................................................................... 51
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`iv
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`Inter Partes Review
`United States Patent No. RE41,980
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`U.S. Patent No. RE41,980 to Yabu et al.
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`File history of U.S. Patent No. 6,232,656 to Yabu et al.
`
`U.S. Patent No. 5,659,201 to Wollesen.
`
`U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Expert Declaration of Dr. Sanjay Banerjee.
`
`U.S. Patent No. 5,169,680 to Ting.
`
`U.S. Patent No. 5,527,737 to Jeng.
`
`U.S. Patent No. 5,300,461 to Ting.
`
`Excerpt of El-Kareh, “Fundamentals of Semiconductor
`Processing Technologies,” Kluwer Academic Publishers
`(1995).
`
`U.S. Patent No. 5,394,013 to Oku et al.
`
`Library of Congress Catalog Record of El-Kareh,
`“Fundamentals of Semiconductor Processing
`Technologies,” Kluwer Academic Publishers (1995).
`
`
`
`LIST OF EXHIBITS
`
`Exhibit 1001:
`
`Exhibit 1002
`
`Exhibit 1003:
`
`Exhibit 1004:
`
`Exhibit 1005:
`
`Exhibit 1006:
`
`Exhibit 1007:
`
`Exhibit 1008:
`
`Exhibit 1009:
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`Exhibit 1010:
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`Exhibit 1011:
`
`Exhibit 1012:
`
`Declaration of Dr. Li Jiang.
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`Inter Partes Review
`United States Patent No. RE41,980
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`PRELIMINARY STATEMENT
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`U.S. Reissue Patent No. 41,980 to Yabu et al. (Ex. 1001) is directed to
`
`
`
`I.
`
`structures for preventing moisture from being absorbed by insulating films formed
`
`in areas between metal wires in a semiconductor device. These structures were not
`
`novel or nonobvious; all of the limitations of the challenged claims were known and
`
`constitute prior art.
`
`When the ’980 patent application was filed, there were certain known
`
`properties of insulating materials used in semiconductor devices. In particular, it
`
`was known that:
`
`(1) Depositing an insulating material with a “small dielectric constant” in
`
`areas among metal wires could suppress the parasitic capacitance between
`
`those wires. Ex. 1005, ¶ 45; see also Ex. 1001, 1:50-51, 2:30-36.
`
`(2) Covering a device with a moisture-blocking insulating material could
`
`improve the device’s moisture-absorption resistance, but those films
`
`typically had a “large dielectric constant” that would increase the parasitic
`
`capacitance. Ex. 1005, ¶ 45; Ex. 1001, 1:51-52, 2:16-25, 2:30-36.
`
`In view of these well-known properties, it is unsurprising that films placing
`
`these different insulating materials together were already known in the prior art at
`
`the time the ’980 patent was filed. Ex. 1005, ¶ 46; see also Ex. 1001, 1:35-2:29,
`
`FIGS. 18-21. In other words, these prior art films included a first insulating material
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`United States Patent No. RE41,980
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`for purposes of controlling parasitic capacitance and placed on it a second
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`insulating material covering the first film to serve as moisture-blocking passivation
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`film. Ex. 1005, ¶ 46; Ex. 1001, 1:35-2:29, FIGS. 18-21.
`
`Just like the prior art, the challenged independent claims recite the same
`
`surface protecting film including a first dielectric film with a small dielectric
`
`constant (such as silicon oxide) for filling areas among metal wires, and a second
`
`dielectric film (such as silicon nitride) with a “higher moisture absorption
`
`preventing function” for covering the metal wire layer and first dielectric film. The
`
`’980 patent claims only add that the moisture-blocking film and a bonding pad
`
`cover the low-dielectric-constant film when the bonding pad is formed in an
`
`opening in the moisture-blocking film. But this limitation was well known in the art
`
`more than a year before the effective filing date of the ’980 patent.
`
`This petition, supported by the expert declaration of Sanjay Banerjee, Ph.D.,
`
`(Ex. 1005), establishes that each of the challenged claims 18, 19, 30-36, and 47-51
`
`is unpatentable over the prior art. Petitioner respectfully requests inter partes
`
`review under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.100 et seq. and cancellation
`
`of all challenged claims.
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`Inter Partes Review
`United States Patent No. RE41,980
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`II. TECHNOLOGICAL BACKGROUND
`Integrated Circuits
`A.
`An integrated circuit, which is often referred to as an IC, a chip, or a
`
`microchip, is an electronic circuit formed on a piece of semiconductor material and
`
`includes a plurality of electronic components, such as transistors, usually metal-
`
`oxide-semiconductor field-effect transistor (MOSFETs). Ex. 1005, ¶ 31. At the
`
`early time of integrated circuit technology, only a few (usually less than about 100)
`
`transistors were included in an integrated circuit, and such a level of integration is
`
`referred to as small-scale integration (SSI). Ex. 1005, ¶ 32. With the development
`
`of improved semiconductor processing technology, more and more transistors were
`
`integrated to form a single integrated circuit. Id. Depending on the number of
`
`transistors in the integrated circuit, later generations of integration technology are
`
`usually referred to as medium-scale integration (MSI, including about 100 to about
`
`1000 transistors), large-scale integration (LSI, including about 1000 to about
`
`10 thousand transistors), very-large-scale integration (VLSI, including about
`
`10 thousand to about 1 million transistors), and ultra-large-scale integration (ULSI,
`
`including about 1 million or more transistors)1. Id.
`
`
`1 There is no universal consensus about the number of transistors in each
`
`generation. These ranges are only for illustrative purposes. Ex. 1005 at 12, n.2.
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`United States Patent No. RE41,980
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`To form an integrated circuit, transistors need to be electrically coupled to
`
`each other by interconnections, which are electrical conductors that provide
`
`pathways for electrical signals. Id., ¶ 33. Interconnections can be made from a
`
`variety of conducting materials, such as metals, metal alloys, metal compounds,
`
`highly doped polycrystalline silicon (polysilicon), or combinations of these (e.g.,
`
`metal-silicon compounds, called “silicides”). Id.
`
`With increasing integration scales and decreasing sizes of individual
`
`transistors, multilevel interconnection structures were increasingly utilized for
`
`increasing both the circuit densities and operation speeds of integrated circuits. Id.,
`
`¶ 34; see also, e.g., Ex. 1001, 1:28-33; Ex. 1003, 1:42-45; Ex. 1006, 1:21-25; Ex.
`
`1007, 1:44-46. Such multilevel interconnection structures have existed for over
`
`50 years. Ex. 1005, ¶ 34. For example, U.S. Patent No. 3,617,824 to Shinoda et al.
`
`(“Shinoda,” Ex. 1004), which has an earliest priority date of 1965, discloses
`
`multilevel interconnections formed between transistors in an integrated circuit,
`
`including lower level interconnects (shown in the annotated figures below in blue)
`
`and upper level interconnects (in green) separated by insulating material (in red).
`
`Ex. 1004, FIGS. 6 and 7 (reproduced below); see also Ex. 1003, FIG. 1; Ex. 1006,
`
`FIG. 5; Ex. 1005, ¶ 34.
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`United States Patent No. RE41,980
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`Annotated FIG. 6 of Shinoda (Ex. 1004)
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`
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`Annotated FIG. 7 of Shinoda
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`
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`B. Dielectric Materials
`As mentioned above, the semiconductor industry has steadily moved towards
`
`packing more transistors onto one chip, by reducing the size of individual
`
`transistors and/or reducing the distance between individual transistors. Ex. 1005,
`
`¶¶ 32-34, 36; see also, e.g., Ex. 1001, 1:29-34. As a result, device densities in an
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`integrated circuit increase and interconnects, such as metal wires, within the
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`integrated circuits become packed closer together. Ex. 1005, ¶ 32-34, 36; see also,
`
`e.g., Ex. 1001, 1:29-34. However, various design restrictions limit further shrinking
`
`of the sizes of individual transistors and reducing distances between interconnects.
`
`Ex. 1005, ¶ 35.
`
`One major concern with scaling integrated circuits to smaller sizes and higher
`
`densities is the capacitance, also referred to as parasitic capacitance, between the
`
`interconnects. Id., ¶ 36. The parasitic capacitance increases with reduced distance
`
`(or “pitch”) between two interconnects, which is undesirable because increased
`
`parasitic capacitance can increase signal delay times, crosstalk, and power
`
`dissipation in the integrated circuit. Id., ¶ 36; see also, e.g., Ex. 1007, 1:50-57 (“As
`
`device geometries shrink and functional density increases, it becomes imperative to
`
`reduce the capacitance between the lines . . . Reducing the capacitance within these
`
`multi-level metallization systems will reduce the RC constant, crosstalk voltage,
`
`and power dissipation between the lines.”).
`
`The parasitic capacitance between two interconnects is also proportional to
`
`the dielectric constant of the material between the interconnects. Ex. 1005, ¶ 37.
`
`Therefore, one approach to reduce the parasitic capacitance is to use a dielectric
`
`material having a relatively small dielectric constant (also referred to as “low”
`
`dielectric constant or low-k) between the interconnects. Id.; see also, e.g., Ex. 1007,
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`1:66-67, 4:30-47, 2:5-6. Dielectric constants of materials, as would have been
`
`understood by a POSITA at the time the ’980 patent’s application was filed, are
`
`based on a relative scale, where 1.0 represents the dielectric constant of vacuum.
`
`Ex. 1005, ¶ 37; Ex. 1007, 1:64-66.
`
`Silicon dioxide (often referred to as “silicon oxide”) is a widely used
`
`dielectric material for separating different layers of interconnects in a
`
`semiconductor device and for isolating interconnects within the same layer. Ex.
`
`1005, ¶ 38. The dielectric constant of silicon oxide may depend on how dense it is.
`
`Id. For example, dense silicon oxide grown by thermal oxidation or chemical vapor
`
`deposition has a dielectric constant on the order of about 3.9. Id.; see also Ex. 1007,
`
`1:62-64; Badih El-Kareh, “Fundamentals of Semiconductor Processing
`
`Technology,” at 9, Table 2.1, Kluwer Academic Publishers (1995) (“El-Kareh,”
`
`Ex. 1009).2
`
`
`2 Exhibit 1009 was catalogued and available to the public in the Library of
`
`Congress in 1994. Ex. 1009 at 2 (showing Library of Congress stamp dated
`
`December 21, 1994); Ex. 1011 (catalogue entry); Ex. 1012 at ¶ 3 (linking Ex. 1009
`
`to Ex. 1011). Papers catalogued and available to the public in libraries, including
`
`the Library of Congress, are sufficiently “publicly accessible” to serve as prior art.
`
`See, e.g., In re Hall, 781 F.2d 897 (Fed. Cir. 1986); In re Cronyn, 890 F.2d 1158,
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`United States Patent No. RE41,980
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`Further decreasing distances between interconnects raises the need for
`
`dielectric materials having even smaller dielectric constants. Ex. 1005, ¶ 39. Such
`
`dielectric materials can be created by doping silicon oxide with another element,
`
`such as fluorine, carbon, or hydrogen, or by making silicon oxide porous. Id.; see
`
`also Ex. 1001, 2:32-33 (admitted prior art includes “silicon oxide film doped with
`
`fluorine . . . having a small dielectric constant” to suppress parasitic capacitance
`
`between metal wires); Ex. 1007, 2:1-4. Some organic materials with small dielectric
`
`constants, such as polyimide, polynorbornenes, and organic spin-on glass (SOG)
`
`material, can also be used. Ex. 1005, ¶ 39; see also Ex. 1001, 2:33.
`
`While low-dielectric-constant materials can reduce parasitic capacitance, they
`
`usually absorb moisture more easily than denser materials (which often also have
`
`higher dielectric constants), and such moisture absorption can reduce the reliability
`
`of the semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1001, 2:30-34. To prevent
`
`moisture from entering the semiconductor device through the low-dielectric-
`
`constant material, a passivation layer (sometimes also called a “protective”
`
`dielectric layer) can be formed over the upper-most layer of low-dielectric-constant
`
`material in a semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1003, 2:5-10. The
`
`passivation layer usually is formed, for example, using silicon nitride or silicon
`
`1161 (Fed. Cir. 1989). Accordingly, Exhibit 1009 qualified as prior art at least one
`
`year before the earliest priority date of the ’980 patent.
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`United States Patent No. RE41,980
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`oxynitride, which have higher moisture-blocking functions and higher dielectric
`
`constants than silicon oxide. Ex. 1005, ¶ 40; Ex. 1003, 2:5-7.
`
`C. Bonding Pads
`Bonding is often used to electrically couple an integrated circuit with its
`
`packaging or other electronic devices, where a conducting bonding material, e.g., a
`
`gold or aluminum wire, solder bump, copper pillar, or other external connection, is
`
`bonded to a bonding pad of the integrated circuit. Ex. 1005, ¶ 41. A bonding pad
`
`usually includes a metal area having an appropriate horizontal size to facilitate
`
`bonding to the bonding material, and is electrically coupled to other conducting
`
`parts, such as the interconnects, of the integrated circuit. Id. For example, FIG. 11
`
`(reproduced and annotated below) of U.S. Patent No. 5,394,013 to Oku et al.
`
`(“Oku,” Ex. 1010) schematically illustrates a bonding pad 11 (in pink) connected to
`
`a second aluminum film 45 (in red), which in turn is connected to a first aluminum
`
`film 43 (in brown). Ex. 1005, ¶ 41.
`
`Bonding pad
`
`First aluminum film
`
`Second aluminum film
`
`Annotated FIG. 11 of Oku (Ex. 1010)
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`United States Patent No. RE41,980
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`Usually, there are two types of bonding pads. The first type is formed directly
`
`using one of the interconnect layers, usually the uppermost interconnect layer, of
`
`the integrated circuit, i.e., a portion of the interconnect layer functions as the
`
`bonding pad. Ex. 1005, ¶ 42; Ex. 1003, FIG. 1 (showing an interconnect layer 10
`
`with two representative interconnect lines, where one of the interconnect lines has a
`
`top surface that also functions as a bonding pad 14).
`
`Interconnect layer
`
`Bonding pad
`
`Interconnect layer
`
`Annotated FIG. 1 of Wollesen (Ex. 1003)
`
`
`
`
`
`The second type of bonding pad includes conductive pads that are separately
`
`formed on one of the interconnect layers, usually the uppermost interconnect layer,
`
`of the integrated circuit. Ex. 1005, ¶ 43; Ex. 1006, FIG. 5 (showing a bonding pad
`
`46 that is formed in an opening on interconnect layer 35 and 36).
`
`10
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`United States Patent No. RE41,980
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`Bonding pad
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`
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`Interconnect layer
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`Annotated Fig. 5 of Ting (Ex. 1006)
`
`
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`For either type of bonding pad, an opening is formed in the uppermost
`
`dielectric layers (e.g., shown in FIG. 5 of Ting reproduced above), or merely
`
`through the passivation layer if it directly overlies an area of the interconnect layer
`
`used for forming the bonding pad (e.g., shown in FIG. 1 of Wollesen reproduced
`
`above), to either expose a portion of the interconnect layer that will function as a
`
`bonding pad, or to fill the opening with a metal that will function as the bonding
`
`pad. Ex. 1005, ¶ 44.
`
`III. THE ’980 PATENT
`A. Overview of the ’980 Patent
`The ’980 patent discloses “a semiconductor device which has a small
`
`parasitic capacitance in an area with a small pitch between metal wires and is free
`
`from a coverage defect as well as the moisture absorption through the opening for
`
`11
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`Inter Partes Review
`United States Patent No. RE41,980
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`the bonding pad.” Ex. 1001, Abstract. While seemingly complicated, the ’980
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`patent simply describes prior art. Ex. 1005, ¶ 47.
`
`Specifically, the ’980 patent acknowledges a prior-art technique where an
`
`“underlying insulating film 19 of a thin silicon film,” which refers to a silicon-based
`
`dielectric film (Ex. 1005, ¶ 47, noting silicon alone is not an insulator) is first
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`deposited between adjacent metal wires 12. Then, a “passivation film 14 of a silicon
`
`nitride film” is deposited over the top of the semiconductor device. Id., 1:35-2:29,
`
`FIGS. 18-21. The passivation film 14 is described as having “a large dielectric
`
`constant” (Ex. 1001, 2:15-17), implying the underlying insulating film 19 has a
`
`lower dielectric constant. Ex. 1005, ¶ 47.
`
`In further describing the prior art, the ’980 patent teaches that when the low
`
`dielectric film 19 is removed and the silicon-nitride passivation film 14 fills the
`
`areas between metal wires with a small pitch (e.g., as shown in FIG. 20(b)), the
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`moisture absorption resistance of the device improves but the parasitic capacitance
`
`between the metal wires increases. Id., 2:19-25, FIG. 20(b). In other words, while
`
`the low-dielectric-constant film 19 in prior-art devices has the advantage of
`
`reducing parasitic capacitance between the metal wires compared to a higher
`
`dielectric constant film, such as silicon nitride, the higher-dielectric-constant film
`
`14 is a better barrier for moisture absorption. Ex. 1005, ¶ 48.
`
`12
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`United States Patent No. RE41,980
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`The ’980 patent then purports to solve a problem by using a conventional
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`dual-layered low-dielectric/high-dielectric film. With reference to FIGS. 18 and 21
`
`(labeled prior art), the ’980 patent identifies a path through which moisture could
`
`enter a conventional semiconductor device having the same passivation film 14 and
`
`underlying insulating film 19 discussed above. In this device, a metal wiring layer
`
`contains metal wires 12 and “a bonding pad 15 formed out of the same metal film
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`as metal wires 12” for providing external electrical connections. Id., 1:52-57. The
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`’980 patent suggests that when an opening 21a for the bonding pad 15 is created
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`through the films 19 and 14, the low-dielectric-constant insulating film 19 would
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`become exposed along a side wall of the opening 21a, thereby providing a path for
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`moisture absorption. This path is shown in FIG. 21 (copied below). Ex. 1005, ¶ 49.
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`The proposed invention of the ’980 patent, then, is to merely close the
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`opening through which moisture could enter the low-dielectric insulating film 19
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`along the side wall of the opening 21a. The patent discloses various embodiments
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`where the top-most passivation film 14 and the bonding pad 15 completely cover
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`13
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`any potential ingress paths to the insulating layer 19. Ex. 1005, ¶ 50. For example,
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`FIG. 1 shows an embodiment where the bonding pad 15 fills the opening 20a and
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`partially overlaps the top surface of the passivation film 14, ensuring there is no
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`exposed surface of the underlying insulating layer 13 on the side wall of the
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`opening 20a. Ex. 1005, ¶ 51.
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`FIG. 1 of ’980 Patent
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`FIG. 5 shows another embodiment where the passivation film 14 covers the
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`top surface of the underlying insulating film 13 and the bonding pad 15 covers the
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`side walls of opening 20a, thereby preventing the insulating film 13 from being
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`exposed on the side wall of opening 20a. Ex. 1005, ¶ 52.
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`14
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`FIG. 5 of ’980 Patent
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`FIGS. 8 and 16 of the ’980 patent show yet other embodiments of the alleged
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`invention where the passivation film 14 partially overlaps the top surface of the
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`bonding pad 15, with the same result of ensuring there is no exposed surface of the
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`underlying insulating layer 13 on the side wall of opening 20a. Ex. 1005, ¶ 53.
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`FIG. 8 of ’980 Patent
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`15
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`FIG. 16 of ’980 Patent
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`B. Challenged Claims3
`The two challenged independent claims of the ’980 patent recite:
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`18. A semiconductor device comprising:
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`[18.1] a semiconductor substrate bearing semiconductor elements;
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`[18.2] an interlayer insulating film formed on said semiconductor
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`substrate;
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`[18.3] a metal wire layer including plural metal wires formed on said
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`interlayer insulating film;
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`[18.4a] a surface protecting film including a first dielectric film with a
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`small dielectric constant for filling at least a part of areas among
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`said metal wires in said metal wire layer and
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`3 The challenged claims are claims 18, 19, 30-36, and 47-51.
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`16
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`[18.4b] a second dielectric film with a higher moisture absorption
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`preventing function than said first dielectric film for covering
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`said metal wire layer and said first dielectric film, said second
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`dielectric film having a function of suppressing moisture
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`absorption of said first dielectric film;
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`[18.5] an opening for a bonding pad formed in said surface protecting
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`film; and
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`[18.6] a bonding pad formed in said opening for obtaining external
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`electrical connection,
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`[18.7] wherein said bonding pad in said opening and said second
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`dielectric film of said surface protecting film completely cover
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`said first dielectric film so as not to expose said first dielectric
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`film.
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`35. A semiconductor device comprising:
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`[35.1] a semiconductor substrate bearing semiconductor elements;
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`[35.2] an interlayer insulating film formed on said semiconductor
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`substrate;
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`[35.3] a metal wire layer including plural metal wires formed on said
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`interlayer insulating film;
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`[35.4a] a surface protecting film including a first dielectric film with a
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`small dielectric constant for filling at least a part of areas among
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`said metal wires in said metal wire layer and
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`[35.4b] a second dielectric film with a higher moisture absorption
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`preventing function than said first dielectric film for covering
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`said metal wire layer and said first dielectric film, said second
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`dielectric film having a function of suppressing moisture
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`absorption of said first dielectric film;
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`[35.5] an opening for a bonding pad formed in said surface protecting
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`film; and
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`[35.6] a bonding pad formed in said opening for obtaining external
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`electrical connection,
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`[35.7] wherein said bonding pad covers said opening and said second
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`dielectric film of said surface protecting film completely covers
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`said first dielectric film so as not to expose said first dielectric
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`film.
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`IV. STATEMENT OF PRECISE RELIEF REQUESTED
`A. Claims for Which Review is Requested
`Petitioner requests review under 35 U.S.C. § 311 of claims 18, 19, 30-36, and
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`47-51, and the cancellation of those claims as unpatentable.
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`18
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`Statutory Grounds of Challenge
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`B.
`Claims 18, 19, 30-36, and 47-51 are unpatentable based on 35 U.S.C. §§ 102
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`and 103 as follows:
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`Prior Art
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`Unpatentable Claims
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`Ting
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`Ting in view of Jeng
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`35 U.S.C.
`§§ 102, 103
`102
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`18, 19, 30-36, and 47-51
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`18, 19, 30-36, and 47-51
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`103
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`C. Level of Ordinary Skill
`A person of ordinary skill in the art (“POSITA”) at the time the application
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`leading to the ’980 patent was filed would have an equivalent of a Master of
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`Science degree from an accredited institution in electrical engineering, materials
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`science, or physics, or the equivalent, a working knowledge of semiconductor
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`processing technologies for integrated circuits, and at least two years of experience
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`in semiconductor processing analysis, design, and development. Ex. 1005, ¶ 55.
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`Additional graduate education could substitute for professional experience, and
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`significant work experience could substitute for formal education. Id.
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`D. Claim Construction
`Claim terms are given their ordinary and accustomed meaning as understood
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`by a POSITA. Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en
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`banc). Because the ’980 patent will expire on September 8, 2017, the Phillips
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`standard should be applied to claim terms construed in this proceeding. See, e.g., 37
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`C.F.R. § 42.100(b).
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`V. CLAIMS 18, 19, 30-36, AND 47-51 OF THE ’980 PATENT ARE
`UNPATENTABLE OVER THE PRIOR ART
`A. Disclosures of the Prior Art
`The inventors of the ’980 patent were not the first to use bonding pads and/or
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`moisture-blocking passivation layers in a multilayer wiring structur