Case IPR2016-1331 for
`U.S. Patent No. RE41,980
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`By: Michael J. Fink (mfink@gbpatent.com)
`Greenblum & Bernstein, P.L.C.
`1950 Roland Clarke Place
`Reston, Virginia 20191
`Tel: (703) 716-1191
`Fax: (703) 716-1180
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-01331
`U.S. Patent No. RE41,980
`____________
`
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. §42.107
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`

`
`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
`
`
`I.
`
`INTRODUCTION ....................................................................................... 1
`
`TABLE OF CONTENTS
`
`II.
`
`THE ‘980 PATENT ..................................................................................... 2
`
`A.
`
`Background........................................................................................ 2
`
`B.
`
`C.
`
`The ‘980 Patent .................................................................................. 3
`
`Prosecution History Of The ‘980 Patent ............................................. 6
`
`III. LEVEL OF ORDINARY SKILL ................................................................. 7
`
`IV. CLAIM CONSTRUCTION ......................................................................... 7
`
`A.
`
`B.
`
`C.
`
`The Proper Construction Of “An Interlayer Insulating Film” ............. 8
`
`The Proper Construction Of “A Metal Wire Layer Including
`Plural Metal Wires” ..........................................................................11
`
`The Proper Construction Of “At Least A Part Of Areas
`Among Said Metal Wires In Said Metal Wire Layer” .......................12
`
`V.
`
`PRIOR ART ...............................................................................................13
`
`A. U.S. Patent No. 5,169,680 (“Ting”)...................................................13
`
`B.
`
`U.S. Patent No. 5,527,737 (“Jeng”) .................................................18
`
`VI. ARGUMENT..............................................................................................19
`
`A.
`
`B.
`
`Summary Of Argument .....................................................................19
`
`The Petition Fails To Establish That There Is A Reasonable
`Likelihood That At Least One Of The Challenged Claims Is
`Unpatentable For Anticipation Under 35 U.S.C. §102 ......................20
`
`1.
`
`2.
`
`3.
`
`The Petition Fails To Establish That Ting Discloses The
`Claimed Interlayer Insulating Film .........................................22
`
`The Petition Fails To Establish That Ting Discloses The
`Claimed Metal Wire Layer Including Plural Metal Wires .......24
`
`The Petition Fails To Establish That Ting Discloses The
`Claimed Areas Among Said Metal Wires In Said Metal
`Wire Layer ..............................................................................27
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`C.
`
`The Petition Fails To Establish That There Is A Reasonable
`Likelihood That At Least One Of The Challenged Claims Is
`Unpatentable For Obviousness Under 35 U.S.C. §103 ......................29
`
`1.
`
`2.
`
`A Combination Of Ting And Jeng Would Not Have
`Arrived At The Features Of The Challenged Claims. ..............31
`
`The Petition Fails To Show How A POSITA Would
`Have Combined The Processes Of Ting And Jeng ..................40
`
`VII. CONCLUSION ..........................................................................................41
`
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`TABLE OF AUTHORITIES
`
`
`
`Cases
`
`Enfish, LLC v. Microsoft Corporation,
`822 F.3d 1327 (Fed. Cir. 2016) ..........................................................................21
`
`Finisar Corp. v. DirecTV Grp., Inc.,
`523 F.3d 1323 (Fed. Cir. 2008) ..........................................................................21
`
`In re Arkley,
`455 F.2d 586 (CCPA 1972) ...............................................................................20
`
`In re Kahn,
`441 F.3d 977 (Fed. Cir. 2006) ............................................................................30
`
`In re Rijckaert,
`9 F.3d 1531 (Fed. Cir. 1993) ........................................................................ 22, 26
`
`In re Robertson,
`169 F.3d 743 (Fed. Cir. 1999) ...................................................................... 22, 26
`
`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1997) ..........................................................................20
`
`In Re: Magnum Oil Tools International, Ltd.,
`__ F.3d __, Appeal No. 2015-1300 (Fed. Cir. July 25, 2016) ..................... 1, 2, 31
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ..................................................................................... 30, 31
`
`Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359 (Fed. Cir. 2008) ..........................................................................21
`
`Panasonic Corp., et al. v. Optical Devices, LLC,
`IPR2014-00302, Paper 9 ....................................................................................20
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ........................................................................ 7, 8
`
`iii
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`

`
`Symnatec Corp. v. RPost Comunications Ltd.,
`IPR2014-00357, Paper 14 ..................................................................................20
`
`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`
`
`
`Statutes
`
`35 U.S.C. §102 ........................................................................................... 1, 19, 20
`
`35 U.S.C. §103 ....................................................................... 19, 29, 30, 32, 39, 41
`
`35 U.S.C. §313 ...................................................................................................... 1
`
`35 U.S.C. §316(e) .................................................................................................30
`
`
`
`Regulations
`
`37 C.F.R. §42.1(d) ................................................................................................30
`
`37 C.F.R. §42.100(b) ............................................................................................. 8
`
`37 C.F.R. §42.107 .................................................................................................. 1
`
`37 C.F.R. §42.108 ....................................................................................... 1, 20, 31
`
`
`
`iv
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`EXHIBIT LIST
`
`“Inter.” Merriam-Webster.com. Accessed September 30, 2016.
`http://www.merriam-webster.com/dictionary/inter.
`
`“Intra.” Merriam-Webster.com. Accessed September 30, 2016.
`http://www.merriam-webster.com/dictionary/intra.
`
`U.S. Patent No. 6,432,811.
`
`“Layer.” OxfordDictionaries.com. Accessed September 28,
`2016. https://en.oxforddictionaries.com/definition/us/layer.
`
`“Electroless.” Merriam-Webster.com. Accessed September 30,
`2016. http://www.merriam-webster.com/ dictionary/electroless.
`
`
`Exhibit 2001:
`
`
`Exhibit 2002:
`
`
`Exhibit 2003:
`
`Exhibit 2004:
`
`
`Exhibit 2005:
`
`
`
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
`
`I.
`
`INTRODUCTION
`
`Patent Owner, Godo Kaisha IP Bridge 1 (“IP Bridge” or “Patent Owner”),
`
`submits this Preliminary Response to the Petition for Inter Partes Review
`
`(“Petition”) filed by Taiwan Semiconductor Manufacturing Company Limited
`
`(“TSMC” or “Petitioner”) on July 8, 2016, against U.S. Patent No. RE41,980
`
`(Exhibit 1001, “the ‘980 Patent”). The Petition challenges the patentability of
`
`claims 18, 19, 30-36, and 47-51 of the ‘980 patent (“the challenged claims”), but
`
`does not challenge claims 20-29 and 37-46. This Preliminary Response is timely
`
`filed under 35 U.S.C. §313 and 37 C.F.R. §42.107.
`
`The Petition asserts that the challenged claims are unpatentable over (1) U.S.
`
`Patent No. 5,169,680 (“Ting”)(Exhibit 1006) under 35 U.S.C. §102, or (2) Ting in
`
`view of U.S. Patent No. 5,527,737 (“Jeng”)(Exhibit 1007) under 35 U.S.C. §103.
`
`Petition, p. 19.
`
`As explained herein, the Petition fails to demonstrate that there is a
`
`reasonable likelihood that at least one of the claims challenged in the petition is
`
`unpatentable. 37 C.F.R. §42.108. The Federal Circuit has recently held that “the
`
`Board must base its decision on arguments that were advanced by a party.” In Re:
`
`Magnum Oil Tools International, Ltd., __ F.3d __, Appeal No. 2015-1300, p. 26
`
`(Fed. Cir. July 25, 2016). The Court stated further that “while the PTO has broad
`
`authority to establish procedures for revisiting earlier-granted patents in IPRs, that
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`Case IPR2016-1331 for
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`authority is not so broad that it allows the PTO to raise, address, and decide
`
`unpatentability theories never presented by the petitioner and not supported by
`
`record evidence.” Id. Accordingly, Patent Owner need not respond to arguments
`
`not raised in the Petition.
`
` As discussed herein, the Petition fails to establish that Ting discloses several
`
`of the limitations recited in the independent claims, i.e., claims 18 and 35, of the
`
`‘980 patent. Exhibit 1001. For example, the Petition fails to establish that the Ting
`
`discloses (1) the “interlayer insulating film”; (2) the “metal wire layer including
`
`plural metal wires”; or (3) the “areas among said metal wires in said metal wire
`
`layer.” Thus, Ting does not anticipate any of the challenged claims.
`
`Additionally, the Petition’s limited obviousness argument fails to
`
`demonstrate that there is a reasonable likelihood that at least one of the claims
`
`challenged in the petition is unpatentable. Thus, for at least the reasons set forth
`
`herein, the Board should deny institution of this IPR proceeding.
`
`II. THE ‘980 PATENT
`
`A. Background
`
`The subject matter of the ‘980 patent relates to semiconductor devices and
`
`maintaining their reliability and performance. More particularly, the ‘980 patent
`
`relates to improvement in the structures of a bonding pad and a surface protective
`
`film, and decreasing parasitic capacitance between metal wires with a small pitch.
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`Parasitic capacitance is undesirable because it can “increase signal delay
`
`times, crosstalk, and power dissipation in the integrated circuit.” Petition, p. 6.
`
`Parasitic capacitance can be caused by filling in the areas between the metal wires
`
`with a small pitch with a material having a large dielectric constant. Moisture
`
`absorption is also is undesirable because it can cause a similar wiring delay
`
`problem. The ‘980 patent discloses novel solutions to overcome these problems,
`
`i.e., to reduce parasitic capacitance and suppress moisture absorption.
`
`B. The ‘980 Patent
`
`The semiconductor device disclosed in the ‘980 patent comprises a
`
`semiconductor substrate bearing semiconductor elements; an interlayer insulating
`
`film formed on the semiconductor substrate; a metal wire layer including plural
`
`metal wires formed on the interlayer insulating film; a surface protecting film
`
`including a first dielectric film with a small dielectric constant for filling at least a
`
`part of areas among the metal wires in the metal wire layer and a second dielectric
`
`film with a higher moisture absorption preventing function than the first dielectric
`
`film for covering the metal wire layer and the first dielectric film; the second
`
`dielectric film having a function of suppressing moisture absorption of the first
`
`dielectric film; an opening for a bonding pad formed in the surface protecting film;
`
`and a bonding pad formed in and/or covering the opening for obtaining an external
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`Case IPR2016-1331 for
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`electrical connection, wherein the bonding pad and the second dielectric film
`
`completely cover the first dielectric film to suppress moisture absorption.
`
`An embodiment of the claimed invention is depicted in Fig. 1 (reproduced
`
`below):
`
`
`
`As shown above, metal wires 12 on top of interlayer insulating film 11
`
`comprise a metal wire layer. The wires are formed by stacking and then patterning
`
`a Ti film and the like. See Exhibit 1001, 7:29-48. A surface protecting film 20 is
`
`formed so as to cover the interlayer insulating film 11 and the metal wires 12. Id.
`
`The surface protecting film 20 is a composite film including a buried insulating
`
`film 13 with a small dielectric constant and a passivation film 14 with a large
`
`dielectric constant and high moisture absorption resistance (such as a silicon nitride
`
`film). Id. In areas among the metal wires 12 directly below the surface protecting
`
`film 20, the buried insulating film 13 with a small dielectric constant is formed at
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`Case IPR2016-1331 for
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`least in an area with the smallest wire pitch. Id. A bonding pad 15 covers opening
`
`20a of the surface protecting film 20 of the composite film. Id. The bonding pad
`
`15 in this embodiment completely covers the side faces of the buried insulating
`
`film 13 with a small dielectric constant within the opening 20a and is drawn above
`
`the passivation film 14. Id. An alternative embodiment of the claimed invention is
`
`depicted in Fig. 5. In Fig. 5 (reproduced below), the top surface of the bonding
`
`pad is at the same level as the passivation film 14 and extends across the opening
`
`20a:
`
`Another alternative embodiment of the claimed invention is depicted in Fig.
`
`
`
`7 (reproduced below):
`
`5
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`Case IPR2016-1331 for
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`In the above embodiment, there is an opening 20a in the composite film 20
`
`and the top surface of the bonding pad 15 is placed “at a lower level than the top
`
`surface of the passivation film 14.” Id., 11:51-55.
`
`Each of the above embodiments of the ‘980 patent have an interlayer
`
`insulating film, a metal wire layer including plural metal wires formed on the
`
`interlayer insulating film, a surface protecting film comprising first and second
`
`dielectric films, and a bonding pad, arranged such that the bonding pad and second
`
`dielectric film completely cover the first dielectric film. The first dielectric film
`
`has a small dielectric constant and the second dielectric film has a higher dielectric
`
`constant than the first dielectric layer. The second dielectric film also has a higher
`
`moisture absorption preventing function than the first dielectric film and functions
`
`to suppress moisture absorption of the first dielectric film.
`
`C. Prosecution History Of The ‘980 Patent
`
`The ‘980 patent is a reissue of U.S. Patent No. 6,232,656 (“the ‘656 patent”).
`
`More than one reissue application has been filed for the ‘656 patent. The reissue
`
`applications are application numbers Ser. No. 11/984,551 (the present application)
`
`and Ser. No. 10/438,348 (now RE39,932). Reissue application Ser. No.
`
`11/984,551 is a continuation reissue application of reissue application Ser. No.
`
`10/438,348 filed May 15, 2003, which is a reissue application of 09/387,834, filed
`
`September 1, 1999 (now the ‘656 patent), which is a divisional application of
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`U.S. Patent No. RE41,980
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`08/925,442, filed September 8, 1997 (now U.S. Patent No. 5,989,992). As such,
`
`the claimed subject matter of the ‘980 patent has been examined several times.
`
`Included in the prior art before the Examiner and identified on the ‘980
`
`patent is U.S. Patent No. 5,527,737 (“Jeng”). Exhibit 1001, Certificate of
`
`Correction, p.36.
`
`III. LEVEL OF ORDINARY SKILL
`
`A person of ordinary skill in the art (“POSITA”) at the time the application
`
`leading to the ‘980 patent was filed would have at least a Bachelor’s degree in
`
`Electrical, Materials, Mechanical, or Chemical Engineering, or a related degree,
`
`and at least two years of experience working in semiconductor processing and
`
`fabrication, semiconductor equipment manufacturing, or semiconductor materials.
`
`As explained further herein, the Petition does not provide adequate
`
`reasoning based on rational underpinnings for why a POSITA would have
`
`modified the alleged prior art to arrive at the features of the challenged claims.
`
`IV. CLAIM CONSTRUCTION
`
`The ‘980 patent will expire on September 8, 2017, which is within 18
`
`months from the entry of the Notice of Filing Date Accorded to Petition, entered
`
`on July 21, 2016 (Paper No. 5). As such, a district court-type claim construction
`
`approach under the standard provided by Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005) should be applied in this IPR in accordance with 37 C.F.R.
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`§42.100(b)(effective May 2, 2016). Under the “Phillips standard,” claim terms are
`
`given “the meaning that [a] term would have to a person of ordinary skill in the art
`
`in question at the time of the invention.” Id. Patent Owner timely filed a Motion
`
`For District Court-Type Claim Construction Under 37 C.F.R. § 42.100(b) on
`
`August 2, 2016 (Paper No. 6).
`
`The Petition does not provide definitions for any of the claim terms. There
`
`are two independent claims within the set of challenged claims, i.e., claims 18 and
`
`35. For purposes of this preliminary response, three claim limitations in particular
`
`need to be construed, and each should be construed consistent with its ordinary and
`
`accustomed meaning. The claim limitations are (1) “interlayer insulating film;” (2)
`
`“a metal wire layer including plural metal wires;” and, (3) “at least a part of areas
`
`among said metal wires in said metal wire layer.” These limitations appear in
`
`independent claims 18 and 35, and therefore apply to all of the challenged claims.
`
`A. The Proper Construction Of “An Interlayer Insulating Film”
`
`The claim limitation “interlayer insulating film” should be accorded its
`
`ordinary and accustomed meaning, i.e., “an insulating film located between but not
`
`within layers.” This construction is supported by the specification. See Exhibit
`
`1001, Abstract; 1:39-47; 1:58-65; 2:52-53; 3:18-20; 4:26-30; 7:15-28; 12:24-33;
`
`Figs. 1-17.
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`Case IPR2016-1331 for
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`Every figure in the ‘980 patent depicting the interlayer insulating film shows
`
`that it is below the metal wire layer and not within the metal wire layer. Exhibit
`
`1001, Figs. 1-17. For example, Fig. 1 (reproduced below) shows that interlayer
`
`insulating film 11 has a substantially smooth top surface and does not fill the
`
`spaces between the metal wires 12 that are formed on the interlayer insulating film:
`
`
`
`Similarly, every figure in the ‘980 patent depicts the interlayer insulating
`
`film entirely above, and not within, any other adjacent layer. For example, Fig. 1
`
`(reproduced above) shows that the insulating film 11 has a substantially smooth
`
`bottom surface and does not fill any areas in an adjacent layer.
`
`Additionally, the specification uses a different term, “buried insulating
`
`film,” when describing a film that is located within the metal wire layer. Exhibit
`
`1001, 8:4-9; 10:44-49; 13:39-47; 15:7-16; 15:52-57; Fig. 1 (element 13). This
`
`term, which describes a film that is buried within a metal wire layer, contrasts with
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`Case IPR2016-1331 for
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`the claim term “interlayer insulating film,” which describes a film that is located
`
`between layers and not buried within another layer.
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`This claim interpretation is further supported by dictionary definitions and
`
`extrinsic evidence. The dictionary provides several definitions for the prefix
`
`“inter,” the most applicable in context of the ‘980 patent being “located between”
`
`or “between the limits of.”1 The prefix “intra” means within, in, or into
`
`something.2 Thus, a POSITA would have understood an interlayer insulation film
`
`to be different from an intralayer dielectric, the interlayer insulating film located
`
`between but not within an adjacent layer. See also U.S. Patent No. 6,432,811, filed
`
`December 20, 2000 (“The term intralayer dielectric as used in this field is
`
`understood to refer to the dielectric material disposed between interconnect lines
`
`on a given interconnect level. That is, an intralayer dielectric is found between
`
`adjacent interconnect lines, rather than vertically above or below those
`
`interconnect lines.” Exhibit 2003, 3:48-53.
`
`Accordingly, the claim limitation “interlayer insulating film” should be
`
`construed to mean “an insulating film located between but not within layers.”
`
`
`
`1 http://www.merriam-webster.com/dictionary/inter; Exhibit 2001.
`
`2 http://www.merriam-webster.com/dictionary/intra; Exhibit 2002.
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`The Proper Construction Of “A Metal Wire Layer Including
`Plural Metal Wires”
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`B.
`
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`The claim limitation “a metal wire layer including plural metal wires”
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`should be accorded its ordinary and accustomed meaning, i.e., “a metal wire layer
`
`including more than one metal wire.” As such, this claim limitation requires two
`
`or more wires located in the same layer.
`
`A layer is defined as “a sheet, quantity, or thickness of material, typically
`
`one of several, covering a surface or body.”3
`
`The ‘980 patent states that a “plurality of metal wires are formed on an
`
`underlying interlayer insulating film.” Exhibit 1001, Abstract. “In the manufacture
`
`of multiple conductive layer semiconductor devices, … a variety of processes for
`
`forming conductive patterns to interconnect various conducting layers of such a
`
`device is well-known in the technology.” Exhibit 1006, 1:21-25. A conductive
`
`layer is not synonymous with a metal wire or a metal wire layer. A conductive
`
`layer may or may not contain metal wires, however, metal wires are not inherently
`
`present in a conductive layer.
`
`The phrase “metal wire layer” should also be accorded its ordinary and
`
`accustomed meaning to mean a layer containing one or more metal wires.
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`
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`3 http://www.oxforddictionaries.com/us/definition/american_english/layer; Exhibit
`
`2004.
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`As shown in Fig. 1 of the ‘980 patent (reproduced above), a plurality of
`
`metal wires 12 on top of interlayer insulating film 11 comprise a metal wire layer.
`
`Accordingly, the claim limitation “a metal wire layer including plural metal
`
`wires” should construed to mean a metal wire layer including more than one metal
`
`wire.
`
`C. The Proper Construction Of “At Least A Part Of Areas Among
`Said Metal Wires In Said Metal Wire Layer”
`
`As noted above, the challenged independent claims recite “a metal wire
`
`layer including plural metal wires.” The phrase “areas among said metal wires”
`
`appearing in the claim limitation “at least a part of areas among said metal wires in
`
`said metal wire layer” refers to plural “areas.” For there to be a plurality of “areas”
`
`among said metal wires, there must be at least three metal wires so that there can
`
`be a plurality of “areas” among said wires, i.e., at least two “areas” among three
`
`metal wires. This claim construction is consistent with the specification which
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`repeatedly refers to the plural “areas” among the metal wires. See Exhibit 1001,
`
`3:8-9; 3:54-55; 4:45-46; 7:39-40; 8:62-63; 10:57; 12:4-5; 13:42; 15:16-17; 16:42-
`
`43; 16:60; 17:2; 18:29. Additionally, Figs. 1 through 7 of the ‘980 patent (Exhibit
`
`1001) each depict more than three metal wires, such that each figure also depicts a
`
`plurality of areas among the metal wires.
`
`Accordingly, the phrase “areas among said metal wires” appearing in the
`
`claim limitation “at least a part of areas among said metal wires in said metal wire
`
`layer” should be construed to mean a plurality of areas.
`
`V.
`
`PRIOR ART
`
`Petitioner asserts that the challenged claims are anticipated by Ting (Exhibit
`
`1006), or in the alternative would have been obvious over the combination of Ting
`
`in view of Jeng (Exhibit 1007). Petition, p. 19. Although other documents are
`
`mentioned in the Petition, they are not considered part of the proposed rejections,
`
`and therefore not addressed. Ting and Jeng are discussed below.
`
`A. U.S. Patent No. 5,169,680 (“Ting”)
`
`Ting is entitled “Electroless deposition for IC fabrication.”4 Ting states that
`
`
`
`4 “Electroless” is defined as “being or involving deposition of metal by chemical
`
`means instead of by electrodeposition.” http://www.merriam-webster.com/
`
`dictionary/electroless; Exhibit 2005.
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`its disclosed invention is “a process for selectively depositing a conductive
`
`material by using an electroless deposition technique in the fabrication of
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`semiconductor devices.” Exhibit 1006, 2:66-3:1. The process is an “additive
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`process wherein the conductive material is deposited onto an underlying layer and
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`the electroless deposition continues to grow until a predetermined level is
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`reached.” Id., 2:3:1-5. Ting discloses that “[e]lectroless deposition provides a
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`selective and an additive process for forming conductive layers, filling window and
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`providing interconnections and terminals.” Id., Abstract (emphasis added). Ting
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`specifically discloses a “wet metal deposition technique” where the device “is
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`immersed in the wet solution.” Id., 4:65-66. “In this technique, a reducing agent
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`(Red), such as hypophosphite, boro hydride, hydrazine, dimethylamine-borane,
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`formaldehyde or dialkylanine borane, is used to enhance the process cycle and
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`reduce the deposition time period.” Id., 5:44-50. The electroless metallization
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`technique of the present invention selectively deposits a filling material by using a
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`reducing agent.” Id., 6:20-22.
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`Ting Fig. 5 (reproduced below) shows a “completed semiconductor device”
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`(Exhibit 1006, 9:3-10):
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`14
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`Case IPR2016-1331 for
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`Petitioner states that “[t]he figures in Ting only illustrate a single,
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`
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`representative portion of the integrated circuit with one representative interconnect
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`line (i.e., conductive layer 36 and its adhesive layer 35)…” Petition, p. 29. While
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`it is true that the figures in Ting depict conductive layers without plural metal wires
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`in the layers, the Petition’s identification of conductive layer 36 (with or without
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`adhesive layer 35) as an interconnection line is not supported by Ting’s
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`specification. Ting’s description of the completed semiconductor device depicted
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`in Fig. 5 differentiates the conducting layers from the interconnections, and
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`identifies the conducting layers and interconnections as separate and distinct
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`structures:
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`A completed semiconductor device 52 utilizing the deposition
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`techniques of the present invention is shown in FIG. 5, wherein
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`device 52 includes a first conducting layer 21, a second
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`conducting layer 36, contact interconnection 14 between the
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`substrate 10 and the first conductive layer 21, via connection 32
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`between the two conductive layers 21 and 36, and the
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`placement of a bonding pad 46 onto the second conductive
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`layer 36.
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`Exhibit 1006, 9:5-10 (emphasis added).5
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` Ting’s discloses forming both conducting layers and interconnections:
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`“The electroless deposition technique can be used to form any
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`or a combination of layers …, namely first and second
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`conducting layers, interconnection between the first layer and
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`the substrate, interconnection between the two conducting
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`layers and the interconnection pad above the second conducting
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`layer.”
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`Exhibit 1006, 4:29-36 (emphasis added).
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`Conductive layers and interconnections are identified as distinct structures
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`throughout Ting. E.g., see Exhibit 1006, 1:66-2:2; 2:22-27; 4:27-36. Ting
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`discloses that interconnections are located between the conductive layers:
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`However, where interconnections are required between the
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`various conducting layers, openings (vias, holes, windows) are
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`cut into the various insulating layers separating the conducting
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`
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`5 Via connection 32 is an interconnection between conductive layer 21 and
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`conductive layer 36. Exhibit 1006, Fig. 5; 9:5-10.
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`layers, so that interconnections can be formed between the
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`conducting layers.
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`Exhibit 1006, 1:66-2:2 (emphasis added).
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`The present invention describes a novel metallization process
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`which is both additive and selective to provide conducting
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`layers, as well as an interconnection between layers of a
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`multiple conducting layer semiconductor device for the
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`manufacture of LSI and VLSI circuits.
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`Exhibit 1006, 2:22-27 (emphasis added).
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`
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`Ting additionally discloses dielectric layers 25 and 40. “The dielectric layer
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`25 of the preferred embodiment has a lower region 27 comprised of silicon dioxide
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`(SiO2) and an upper region 26 comprised of silicon nitride (Si2N4) wherein the
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`oxide and nitride regions 26 and 27 are deposited by a well-known CVD
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`technique. Id., 7:9-14. Regarding dielectric layer 40, Ting states:
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`Another dielectric layer 40 is deposited to isolate the second
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`conductive layer 36. Again, as used in the preferred
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`embodiment, dielectric layer 40 is comprised of an upper
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`section 41 and a lower section 42, where SiO2 is used for a
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`lower section 42, and Si2N4 is used for upper section 41.
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`However, the composition of the two sections 41 and 42 can be
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`reversed also.
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`Id., 8:43-49 (emphasis added).
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`B. U.S. Patent No. 5,527,737 (“Jeng”)
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`Case IPR2016-1331 for
`U.S. Patent No. RE41,980
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`Jeng discloses a “method of selectively forming a low-density, low-
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`dielectric constant insulator between metal lines, which reduces the line-to-line
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`capacitance.” Exhibit 1007, 2:13-16. Specifically, Jeng discloses interconnect
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`lines 14a-d, applying a low-density, low-dielectric-constant layer between
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`interconnect lines 14a-14c, and then covering the lines and filling remaining space
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`between the interconnect lines with a dense silicon oxide layer to isolate the
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`interconnect lines 14a-d from subsequent formed elements. Id., 4:17; 4:21-26.
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`Jeng Fig. 2, reproduced below, depicts interconnect lines 14a-d:
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`As shown above, the dense silicon dioxide 18 covers the porous silicon
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`
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`dioxide 20.
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`Jeng discloses that “a dielectric material layer is coated over the
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`semiconductor body and the plurality of interconnect lines to a thickness sufficient
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`to more than fill the gaps between adjacent interconnect lines. The low dielectric
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`material is baked and then cured at an elevated temperature above the baking
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`18
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`temperature.” Exhibit 1007, 2:21-26 (emphasis added). Curing is an important
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`step in Jeng’s process. Id., 5:28-32; 5:66-67; 6:7-8.
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`Jeng does not disclose an opening for a bonding pad formed in the surface
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`protecting film, or a bonding pad formed in and/or covering the opening, or a
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`bonding pad and dielectric film together completely covering another dielectric
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`film to suppress moisture absorption.
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`VI. ARGUMENT
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`A.
`
`Summary Of Argument
`
`The Petition asserts that the challenged claims are unpatentable under 35
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`U.S.C. §102 as being anticipated by Ting, and in the alternative, the challenged
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`claims are unpatentable under 35 U.S.C. §103 for obviousness over Ting in view of
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`Jeng.
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`Ting does not anticipate the challenged claims for at least the following
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`reasons: Ting does not disclose (1) “an interlayer insulating film” recited in claims
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`18 and 35, (2) the “metal wire layer including plural metal wires” recited in claims
`
`18 and 35, or (3) the “areas among said metal wires in said metal wire layer,”
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`recited in claims 18 and 35. Additionally, the Petition fails to argue that a POSITA
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`would have modified Ting in view of Jeng to include the identified elements
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`missing from Ting, and the Petition further fails to provide a detailed description
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`and/or supporting evidence as to how or why the