Trials@uspto.gov
`571-272-7822
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` Paper 8
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` Date: January 5, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
`LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`
`Case IPR2016-01367
`Patent RE41,980 E
`
`
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`
`
`FITZPATRICK, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
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` Paper 8
`
`
`
` Date: January 5, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
`LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`
`Case IPR2016-01367
`Patent RE41,980 E
`
`
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`
`
`FITZPATRICK, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2016-01367
`Patent RE41,980 E
`
`
`I.
`
`INTRODUCTION
`
`Petitioner, Taiwan Semiconductor Manufacturing Company Limited,
`filed a Petition to institute an inter partes review of claims 18, 19, 30–32,
`34–36, 47–49, and 51 of U.S. Patent No. RE41,980 E (Ex. 1001, “the ’980
`patent”) pursuant to 35 U.S.C. § 311(a). Paper 2 (“Pet.”). Patent Owner,
`Godo Kaisha IP Bridge 1, filed a Preliminary Response under 35 U.S.C.
`§ 313. Paper 7 (“Prelim. Resp.”).
`We have authority to determine whether to institute an inter partes
`review. 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a). Upon consideration of the
`Petition and Preliminary Response, and for the reasons explained below, we
`determine that the information presented does not show a reasonable
`likelihood that Petitioner would prevail with respect to any claim challenged
`in the Petition. See 35 U.S.C. § 314(a); 37 C.F.R § 42.108. The Petition is
`denied.
`
`A. Related Matters
`
`The ’980 patent issued from Serial No. 11/984,551, which was a
`continuation reissue application of Serial No. 10/438,348 (now U.S. Patent
`No. RE39,932), which was a reissue application of Serial No. 09/387,834
`(now U.S. Patent No. 6,232,656), which was a divisional application of
`Serial No. 08/925,442 (now U.S. Patent No. 5,989,992), which was filed
`September 8, 1997. Ex. 1001, 1:10–20.
`Petitioner has filed a separate petition for an inter partes review of
`the ’980 patent, which petition challenges the same claims challenged in the
`
`2
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`IPR2016-01367
`Patent RE41,980 E
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`instant Petition and two additional claims. Pet. 64; Paper 4, 1; see also Case
`IPR2016-01331.
`Patent Owner has asserted the ’980 patent in Godo Kaisha IP Bridge 1
`v. Broadcom Ltd., No. 2-16-cv-00134 (E.D. Tex.). Pet. 64; Paper 4, 2.
`
`B. The ’980 Patent
`
`The ’980 patent “relates to a semiconductor device having a metal
`wire layer and a passivation film in the upper most layer” and, more
`particularly, to “improvement in the structures of a bonding pad and a
`surface protecting film.” Ex. 1001, 1:23–27. The stated “object” of the ’980
`patent is “providing a semiconductor device having high integration, high
`reliability, and high performance . . . by decreasing a parasitic capacitance
`between metal wires with a small pitch in a metal wire layer, by preventing a
`coverage defect in depositing a silicon nitride film used as a passivation
`film, and by suppressing moisture absorption through an opening for
`forming a bonding pad.” Id. at 2:40–48.
`Figure 1 of the ’980 patent is reproduced below.
`
`3
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`IPR2016-01367
`Patent RE41,980 E
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`Figure 1 shows a sectional view of a semiconductor device
`embodiment of the invention of the ’980 patent. Id. at 6:21–23. The
`embodiment includes interlayer insulating film 11 on which is formed a
`metal wire layer including a plurality of metal wires 12. Id. at 7:29–32.
`Surface protecting film 20 covers the interlayer insulating film and the metal
`wires. Id. at 7:33–35. The surface protecting film “is a composite film
`including a buried insulating film 13 of an insulating film with a small
`dielectric constant (such as a TEOS film) and a passivation film 14 of an
`insulating film with a large dielectric constant and high moisture absorption
`resistance (such as a silicon nitride film).” Id. at 7:35–40. Bonding pad 15
`is buried in opening 20a of the surface protecting film, completely covers the
`side faces of the buried insulating film, and is drawn above the passivation
`film. Id. at 7:43–49.
`
`4
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`IPR2016-01367
`Patent RE41,980 E
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`
`C. The Challenged Claims
`
`formed on
`
`said
`
`Of the challenged claims, claims 18 and 35 are independent. Claim
`18 is illustrative and reproduced below with emphasis on the limitation
`which is dispositive of the Petition.
`18. A semiconductor device comprising:
`a
`semiconductor
`substrate bearing
`semiconductor
`elements;
`insulating
`interlayer
`an
`semiconductor substrate;
`a metal wire layer including plural metal wires formed on
`said interlayer insulating film;
`a surface protecting film including a first dielectric film
`with a small dielectric constant for filling at least a part of areas
`among said metal wires in said metal wire layer and a second
`dielectric film with a higher moisture absorption preventing
`function than said first dielectric film for covering said metal
`wire layer and said first dielectric film, said second dielectric
`film having a function of suppressing moisture absorption of said
`first dielectric film;
`an opening for a bonding pad formed in said surface
`protecting film; and
`a bonding pad formed in said opening for obtaining
`external electrical connection,
`wherein said bonding pad in said opening and said second
`dielectric film of said surface protecting film completely cover
`said first dielectric film so as not to expose said first dielectric
`film.
`
`film
`
`
`
`
`
`5
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`IPR2016-01367
`Patent RE41,980 E
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`
`D. Asserted Grounds of Unpatentability
`
`Petitioner asserts the following grounds of unpatentability:
`Basis1
`Reference(s)
`Claims
`Wollesen (Ex. 1006)2
`§ 102(a) and (e)
`18, 19, 30–32, 34–
`36, 47–49, and 51
`18, 19, 30–32, 34–
`36, 47–49, and 51
`
`§ 103(a)
`
`Wollesen and Jeng
`(Ex. 1007)3
`Pet. 20–63.
`
`II. ANALYSIS
`
`A. Claim Construction
`
`Patent Owner filed a Motion for a district court-type claim
`construction, asserting that the ’980 patent will expire on September 8, 2017,
`which is less than eighteen months after entry of the Notice of Filing Date
`Accorded to the Petition. Paper 6; see also 37 C.F.R. § 42.100(b) (“A party
`may request a district court-type claim construction approach to be applied if
`
`
`1 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29,
`which was enacted September 16, 2011, made amendments to 35 U.S.C.
`§§ 102 and 103. AIA § 3(b) and (c). Those amendments became effective
`eighteen months later on March 16, 2013. Id. at § 3(n). Because the
`application from which the ’980 patent issued was filed before March 16,
`2013, our citations to 35 U.S.C. §§ 102 and 103 are to their pre-AIA
`versions.
`2 U.S. Patent No. 5,659,201 to Wollesen was filed June 5, 1995, and issued
`August 19, 1997. The earliest possible effective filing date of the challenged
`claims of the ’980 patent is September 10, 1996. Ex. 1001, [30]. Thus,
`Wollesen is prior art under at least 35 U.S.C. § 102(e).
`3 U.S. Patent No. 5,527,737 to Jeng was filed May 27, 1994, and issued June
`18, 1996. Thus, Jeng is prior art under at least 35 U.S.C. § 102(a).
`6
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`Patent RE41,980 E
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`a party certifies that the involved patent will expire within 18 months from
`the entry of the Notice of Filing Date Accorded to Petition.”); Paper 3
`(Notice of Filing Date Accorded to Petition entered July 12, 2016).
`Petitioner concedes that the ’980 patent will expire on September 8, 2017.
`Pet. 19. We grant Patent Owner’s Motion.
`In district court, claim terms are given their plain and ordinary
`meaning as would be understood by a person of ordinary skill in the art at
`the time of the invention and in the context of the entire patent disclosure.
`Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc).
`“There are only two exceptions to this general rule: 1) when a patentee sets
`out a definition and acts as his own lexicographer, or 2) when the patentee
`disavows the full scope of a claim term either in the specification or during
`prosecution.” Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362,
`1365 (Fed. Cir. 2012).
`Petitioner does not propose an express construction for any limitation.
`Pet. 19. Patent Owner proposes express constructions for several
`limitations, one of which is dispositive and addressed below. Prelim.
`Resp. 9–19.
`
`“an interlayer insulating film”
`
`Independent claims 18 and 35 recite “an interlayer insulating film.”
`Patent Owner argues that this limitation means “an insulating film located
`between but not within layers.” Prelim. Resp. 9. Patent Owner supports its
`construction with intrinsic and extrinsic evidence.
`
`7
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`IPR2016-01367
`Patent RE41,980 E
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`With respect to the intrinsic evidence, Patent Owner points out that
`the figures in the ’980 patent consistently and uniformly depict the interlayer
`insulating film below and not within the metal wire layer, which is above the
`interlayer insulating film. Id. (citing Ex. 1001, Figs. 1–17). Patent Owner,
`citing the same evidence, also points out that the interlayer insulating film is
`consistently and uniformly shown with smooth top and bottom surfaces and
`not extending into any adjacent layers. Id. at 10 (citing Ex. 1001, Figs. 1–
`17). Patent Owner also points out that the specification uses a different
`term, “buried insulating film,” in reference to an insulating film that extends
`into a metal wire layer (i.e., the wires are buried in such an insulating film).
`Id. (quoting Ex. 1001, 8:4–9, 10:44–49, 13:39–47, 15:7–16, 15:52–57,
`Fig. 1).
`With respect to the extrinsic evidence, Patent Owner cites dictionary
`entries to show the contrasting meanings of the prefixes “inter-” and
`“intra-.” Id. at 10–11 (citing Exs. 2001, 2002). Specifically, Patent Owner
`states: “The dictionary provides several definitions for the prefix ‘inter,’ the
`most applicable in context of the ’980 patent being ‘located between’ or
`‘between the limits of.’ The prefix ‘intra’ means within, in, or into
`something.” Id. (citing Exs. 2001, 2002) (footnotes omitted). Patent Owner
`also cites U.S. Patent No. 6,432,811 (“the ’811 patent”). Id. at 11 (citing
`Ex. 2003). The ’811 and ’980 patents are unrelated; neither claims priority
`to or through the other, and they do not share a common inventor or
`assignee. The ’811 patent, however, is from the same general field of
`semiconductors as the ’980 patent. See Ex. 2003, 1:12–20. Patent Owner
`cites the ’811 patent for its following statements: “The term intralayer
`
`8
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`IPR2016-01367
`Patent RE41,980 E
`
`dielectric as used in this field is understood to refer to the dielectric material
`disposed between interconnect lines on a given interconnect level. That is,
`an intralayer dielectric is found between adjacent interconnect lines, rather
`than vertically above or below those interconnect lines.” Prelim. Resp. 11
`(quoting Ex. 2003, 3:48–53 (our emphasis)). The ’811 patent, thus, uses the
`term “intralayer” in the same manner as the ’980 patent uses the term
`“buried.”4
`We are in general agreement with Patent Owner’s proposed
`construction. However, our construction adds the word “other” and is as
`follows: an insulating film located between but not within other layers. Our
`construction is supported sufficiently by the intrinsic evidence alone.
`The ’980 patent uses the terms “interlayer” and “buried” to refer to two
`distinct configurations of insulating films. The term “interlayer insulating
`film” is described with something (namely, a metal wire layer) formed on
`top of it. E.g., Ex. 1001, Abstract (“A plurality of metal wires are formed on
`an underlying interlayer insulating film.”), 13:39–41 (“As is shown in FIG.
`10, on an underlying interlayer insulating film 11 is formed a metal wire
`layer including a plurality of metal wires 12.”); see also id. at Fig. 1
`
`
`4 The ’980 patent identifies several priority applications, having a range of
`filing dates from September 10, 1996 through November 19, 2007.
`Ex. 1001, [22], [64], [60], [30]; see also id. at 1:10–20 (identifying the U.S.
`priority applications). The ’811 patent was filed within this range—on
`December 20, 2000. Ex. 2003, [22]. In its Preliminary Response, Patent
`Owner does not argue for entitlement to any particular priority date. On this
`record, we find the ’811 patent’s disclosure probative of what a person of
`ordinary skill in the art would have understood “intralayer” to mean in the
`context of semiconductors.
`
`9
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`IPR2016-01367
`Patent RE41,980 E
`
`(illustrating the same). In contrast, the term “buried insulating film” is
`described with something (namely, metal wires) buried within it. E.g., id.,
`Abstract (“Areas among the metal wires are filled with a buried insulating
`film.”), 13:39–48 (“The metal wires 12 are buried in the insulating film
`13.”), Fig. 1 (ref. 11, 13); see also id. at Fig. 1 (illustrating the same);
`dependent claims 19 and 36 (reciting “wherein said first dielectric film is
`buried, among said areas among said metal wires, at least in an area having a
`minimum pitch between said metal wires.”). Patent Owner’s extrinsic
`evidence, discussed above, also supports our construction.
`
`B. Anticipation by Wollesen
`1. Disclosure of Wollesen
`Wollesen teaches a semiconductor device comprising a semiconductor
`substrate bearing semiconductor elements (e.g., transistors). Ex. 1006,
`Fig. 1, 1:52–53 (disclosing a “conventional semiconductor device illustrated
`in FIG. 1”). Figure 1 of Wollesen, as annotated and colored by Petitioner, is
`reproduced below.
`
`10
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`IPR2016-01367
`Patent RE41,980 E
`
`Pet. 26. Figure 1, reproduced above as annotated and colored by Petitioner,
`shows a cross-sectional view of a conventional semiconductor device
`comprising a wire bonding layer. Ex. 1006, 3:22–24. Wollesen describes
`the device as follows:
`
`In the conventional semiconductor device illustrated in
`FIG. 1, p-type semiconductor substrate 1 is provided with field
`oxide 2 for isolating an active region comprising N+ source/drain
`regions 3, and a gate electrode 4, typically of polysilicon, above
`the semiconductor substrate with gate oxide 5therebetween.
`Interlayer dielectric layer 6, typically silicon dioxide, is then
`deposited thereover and openings formed by conventional
`photolithographic and etching techniques for establishing
`electrical contact between subsequently deposited conductive
`layer 8, typically of aluminum or an aluminum-base alloy, and
`source/drain regions 3 through vias 7, and to transistor gate 4a.
`Dielectric layer 9, typically silicon dioxide, is deposited on
`conductive layer 8, and another conductive layer 10, typically
`aluminum or an aluminum-base alloy, formed on dielectric layer
`9 and electrically connected to conductive layer 8 through vias
`11.
`
`With continued reference to FIG. 1, conductive layer 10 is
`the uppermost conductive layer and, hence, constitutes the wire
`bonding layer. Dielectric layer 12, also typically silicon dioxide,
`is deposited, and a protective dielectric scratch resistant
`(“topcoat”) layer 13 deposited thereon. . . . After deposition of
`the protective dielectric layer 13, conventional photolithographic
`and etching techniques are employed to form an opening to
`expose wire bonding layer 10 for external connection by means
`of bonding pad 14 and electrically conductive wires 15 or an
`external connection electrode (not shown).
`Ex. 1006, 1:52–2:15.
`
`11
`
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`IPR2016-01367
`Patent RE41,980 E
`
`
`2. Application of Wollesen to the Challenged Claims
`As discussed above, independent claims 18 and 35, recite “an
`interlayer insulating film.” To meet this limitation, Petitioner relies on
`Wollesen’s dielectric layer 9, which is colored light blue in Petitioner’s
`annotated version of Wollesen Figure 1 reproduced above. Pet. 25–26.
`According to Petitioner and its declarant, Sanjay Kumar Banerjee, Ph.D.,
`Wollesen’s dielectric layer 9 is an interlayer insulating film because “it is an
`electrically insulating film positioned between the conducting layers 8 and
`10 in the semiconductor device.” Pet. 26; Ex. 1005 ¶ 65. We are not
`persuaded.
`An “interlayer insulating film” within the meaning of claims 18 and
`35 is an insulating film located between but not within other layers. As
`Patent Owner correctly points out, in Wollesen, dielectric layer 9 is located,
`at least partially, within the same layer as conductive layer 8. See Prelim.
`Resp. 24 (“dielectric layer 9 would be considered an ‘intralayer’ dielectric,
`not an ‘interlayer’ insulating film”). Put another way, conductive layer 8 is
`buried within dielectric layer 9 in a manner similar to that of the ’980
`patent’s metal wires 12 buried within buried insulating film 13. See Ex.
`1001, 13:39–48, Fig. 1. Accordingly, dielectric layer 9 is not an interlayer
`insulating film within the meaning of claims 18 and 35.5
`
`
`5 The Wollesen embodiment that Petitioner asserts as anticipatory also
`includes “[i]nterlayer dielectric layer 6.” Ex. 1006, 1:57. Petitioner does not
`argue, however, that it meets the “interlayer insulating film” limitation of
`claims 18 and 35. Indeed, so arguing would have compromised Petitioner’s
`arguments with respect to other limitations of claims 18 and 35.
`12
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`IPR2016-01367
`Patent RE41,980 E
`
`Petitioner has not shown how any of the challenged claims, all of
`which recite or incorporate “an interlayer insulating film,” is anticipated by
`Wollesen.
`
`C. Obviousness over Wollesen and Jeng
`
`Petitioner’s obviousness challenge relies additionally on Jeng but not
`in a manner that would cure the deficiency of Wollesen identified above.
`More specifically, Petitioner relies additionally on Jeng to meet a different
`limitation of claims 18 and 35, namely “a surface protecting film including a
`first dielectric film with a small dielectric constant for filling at least a part
`of areas among said metal wires in said metal wire layer,” and no other
`limitations. Pet. 52–57. Accordingly, Petitioner has not shown how any of
`the challenged claims would have been obvious over Wollesen and Jeng.
`
`III. CONCLUSION
`
`There is not a reasonable likelihood that Petitioner would prevail with
`respect to any challenged claim. See 35 U.S.C. § 314(a); 37 C.F.R.
`§ 42.108.
`
`IV. ORDER
`
`Accordingly, it is
`ORDERED that the Petition is denied.
`
`13
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`
`
`IPR2016-01367
`Patent RE41,980 E
`
`For Petitioner:
`
`Robert Yoches
`Bob.yoches@finnegan.com
`
`Stephen E. Kabakoff
`Stephen.kabakoff@finnegan.com
`
`Joshua L. Goldberg
`Joshua.goldberg@finnegan.com
`
`
`
`For Patent Owner:
`
`Michael J. Fink
`mfink@gbpatent.com
`
`Neil Greenblum
`ngreenblum@gbpatent.com
`
`Arnold Turk
`aturk@gbpatent.com
`
`
`
`14
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`
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