Inter Partes Review
`United States Patent No. RE41,980
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
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`
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`
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`Taiwan Semiconductor Manufacturing Company Limited
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`Petitioner
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`v.
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`Godo Kaisha IP Bridge 1
`
`Patent Owner
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`
`
`Inter Partes Review No. IPR2016-01367
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`
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`PETITION FOR INTER PARTES REVIEW OF UNITED STATES
`PATENT NO. RE41,980
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`

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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF CONTENTS
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`I.
`
`PRELIMINARY STATEMENT ................................................................... 1
`
`II. TECHNOLOGICAL BACKGROUND....................................................... 3
`
`A.
`
`Integrated Circuits ................................................................................. 3
`
`B. Dielectric Materials ............................................................................... 5
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`C.
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`Bonding Pads ......................................................................................... 8
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`III. THE ’980 PATENT ......................................................................................11
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`A. Overview of the ’980 Patent ................................................................11
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`B.
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`Challenged Claims ..............................................................................16
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`IV. STATEMENT OF PRECISE RELIEF REQUESTED ...........................18
`
`A.
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`B.
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`C.
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`D.
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`Claims for Which Review is Requested ..............................................18
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`Statutory Grounds of Challenge ..........................................................18
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`Level of Ordinary Skill .......................................................................19
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`Claim Construction..............................................................................19
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`V. CLAIMS 18, 19, 30-32, 34-36, 47-49, AND 51 OF THE ’980
`PATENT ARE UNPATENTABLE OVER THE PRIOR ART ..............19
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`A. Disclosures of the Prior Art .................................................................19
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`1. Wollesen ....................................................................................20
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`2.
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`Jeng ...........................................................................................21
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`B. Wollesen anticipates claims 18, 19, 30-32, 34-36, 47-49, and 51 .......23
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`1. Wollesen anticipates claims 18 and 35 .....................................23
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`2. Wollesen anticipates claims 19 and 36 .....................................46
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`3. Wollesen anticipates claims 30 and 47 .....................................47
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`Inter Partes Review
`United States Patent No. RE41,980
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`4. Wollesen anticipates claims 31 and 48 .....................................48
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`5. Wollesen anticipates claims 32 and 49 .....................................50
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`6. Wollesen anticipates claims 34 and 51 .....................................50
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`C.
`
`The Wollesen-Jeng combination renders claims 18, 19, 30-32,
`34-36, 47-49, and 51 obvious ..............................................................51
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`1.
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`2.
`
`3.
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`4.
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`5.
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`Claims 18 and 35 are obvious over the Wollesen-Jeng
`combination ...............................................................................52
`
`Claims 19 and 36 are obvious over the Wollesen-Jeng
`combination ...............................................................................57
`
`Claims 30 and 47 are obvious over the Wollesen-Jeng
`combination ...............................................................................62
`
`Claims 31 and 48 are obvious over the Wollesen-Jeng
`combination ...............................................................................62
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`Claims 32, 34, 49, and 51 are obvious over the Wollesen-
`Jeng combination ......................................................................63
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`VI. MANDATORY NOTICES .........................................................................63
`
`A.
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`B.
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`C.
`
`D.
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`Real Party-in-Interest ..........................................................................63
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`Related Matters ....................................................................................64
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`Lead and Back-Up Counsel .................................................................64
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`Service Information .............................................................................64
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`VII. CERTIFICATION UNDER 37 C.F.R. § 42.24(d) ....................................65
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`VIII. PAYMENT OF FEES .................................................................................65
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`IX. TIME FOR FILING PETITION ...............................................................65
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`X. GROUNDS FOR STANDING ....................................................................65
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`XI. CONCLUSION ............................................................................................66
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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF AUTHORITIES
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` Page(s)
`
`Cases
`American Calcar, Inc. v. American Honda Motor Co.,
`651 F.3d 1318 (Fed. Cir. 2011) .......................................................................... 38
`
`In re Crish,
`393 F.3d 1253 (Fed. Cir. 2004) .................................................................... 36, 48
`
`In re Cronyn,
`890 F.2d 1158 (Fed. Cir. 1989) .......................................................................... 49
`
`Godo Kaisha IP Bridge 1 v. Broadcom Limited et al.,
`Case No. 2-16-cv-00134 (E.D. Tex. February 14, 2016) ................................... 64
`
`In re Hall,
`781 F.2d 897 (Fed. Cir. 1986) ............................................................................ 49
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 51
`
`Ex parte Masham,
`2 U.S.P.Q.2d 1647 (Bd. Pat. App. & Inter. 1987) .............................................. 38
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 19
`
`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1997) .......................................................................... 37
`
`In re Spada,
`911 F.2d 705 (Fed. Cir. 1990) ............................................................................ 38
`
`Verdegaal Bros. v. Union Oil Co. of California,
`814 F.2d 628 (Fed. Cir. 1987) ............................................................................ 49
`
`iii
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`Statutes
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`Inter Partes Review
`United States Patent No. RE41,980
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`35 U.S.C. § 102 ...................................................................................... 18, 20, 21, 35
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`35 U.S.C. § 103 ........................................................................................................ 18
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`35 U.S.C. § 311 .............................................................................................. 2, 18, 65
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`35 U.S.C. §§ 312–319 ................................................................................................ 2
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`Regulations
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`37 C.F.R. § 42.15 ..................................................................................................... 65
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`37 C.F.R. § 42.24 ..................................................................................................... 65
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`37 C.F.R. § 42.100 ............................................................................................... 2, 19
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`37 C.F.R. § 42.101 ................................................................................................... 65
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`37 C.F.R. § 42.102 ................................................................................................... 65
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`37 C.F.R. § 42.103 ................................................................................................... 65
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`Other Authorities
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`M.P.E.P. § 2114(II) .................................................................................................. 38
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`M.P.E.P. § 2143 ....................................................................................................... 52
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`iv
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`LIST OF EXHIBITS
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`Exhibit 1001:
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`Exhibit 1002:
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`Exhibit 1003:
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`Exhibit 1004:
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`Exhibit 1005:
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`Exhibit 1006:
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`Exhibit 1007:
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`Exhibit 1008:
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`Exhibit 1009:
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`Exhibit 1010:
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`Exhibit 1011:
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`Inter Partes Review
`United States Patent No. RE41,980
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`U.S. Patent No. RE41,980 to Yabu et al.
`
`File history of U.S. Patent No. 6,232,656 to Yabu et al.
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`U.S. Patent No. 5,169,680 to Ting
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`U.S. Patent No. 3,617,824 to Shinoda et al.
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`Expert Declaration of Dr. Sanjay Banerjee
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`U.S. Patent No. 5,659,201 to Wollesen
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`U.S. Patent No. 5,527,737 to Jeng
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`U.S. Patent No. 5,300,461 to Ting
`
`Excerpt of El-Kareh, “Fundamentals of Semiconductor
`Processing Technologies,” Kluwer Academic Publishers
`(1995)
`
`U.S. Patent No. 5,394,013 to Oku et al.
`
`Library of Congress Catalog Record of El-Kareh,
`“Fundamentals of Semiconductor Processing
`Technologies,” Kluwer Academic Publishers (1995)
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`Exhibit 1012:
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`Declaration of Dr. Li Jiang
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`I.
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`Inter Partes Review
`United States Patent No. RE41,980
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`PRELIMINARY STATEMENT
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`U.S. Reissue Patent No. 41,980 to Yabu et al. (Ex. 1001) is directed to
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`structures for preventing moisture from being absorbed by insulating films formed
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`in areas between metal wires in a semiconductor device. These structures were not
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`novel or nonobvious; all of the limitations of the challenged claims were known and
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`constitute prior art.
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`When the ’980 patent application was filed, there were certain known
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`properties of insulating materials used in semiconductor devices. In particular, it
`
`was known that:
`
`(1) Depositing an insulating material with a “small dielectric constant” in
`
`areas among metal wires could suppress the parasitic capacitance between
`
`those wires. Ex. 1005, ¶ 45; see also Ex. 1001, 1:50-51, 2:30-36.
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`(2) Covering a device with a moisture-blocking insulating material could
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`improve the device’s moisture-absorption resistance, but those films
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`typically had a “large dielectric constant” that would increase the parasitic
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`capacitance. Ex. 1005, ¶ 45; Ex. 1001, 1:51-52, 2:16-25, 2:30-36.
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`In view of these well-known properties, it is unsurprising that films placing
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`these different insulating materials together were already known in the prior art at
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`the time the ’980 patent was filed. Ex. 1005, ¶ 46; see also Ex. 1001, 1:35-2:29,
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`FIGS. 18-21. In other words, these prior art films included a first insulating material
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`for purposes of controlling parasitic capacitance and placed on it a second
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`insulating material covering the first film to serve as moisture-blocking passivation
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`film. Ex. 1005, ¶ 46; Ex. 1001, 1:35-2:29, FIGS. 18-21.
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`Just like the prior art, the challenged independent claims recite the same
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`surface protecting film including a first dielectric film with a small dielectric
`
`constant (such as silicon oxide) for filling areas among metal wires, and a second
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`dielectric film (such as silicon nitride) with a “higher moisture absorption
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`preventing function” for covering the metal wire layer and first dielectric film. The
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`’980 patent claims only add that the moisture-blocking film and a bonding pad
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`cover the low-dielectric-constant film when the bonding pad is formed in an
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`opening in the moisture-blocking film. But this limitation was well known in the art
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`more than a year before the effective filing date of the ’980 patent.
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`This petition, supported by the expert declaration of Sanjay Banerjee, Ph.D.,
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`(Ex. 1005), establishes that each of the challenged claims 18, 19, 30-32, 34-36,
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`47-49, and 51 is unpatentable over the prior art. Petitioner respectfully requests
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`inter partes review under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.100 et seq. and
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`cancellation of all challenged claims.
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`Inter Partes Review
`United States Patent No. RE41,980
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`II. TECHNOLOGICAL BACKGROUND
`Integrated Circuits
`A.
`An integrated circuit, which is often referred to as an IC, a chip, or a
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`microchip, is an electronic circuit formed on a piece of semiconductor material and
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`includes a plurality of electronic components, such as transistors, usually metal-
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`oxide-semiconductor field-effect transistor (MOSFETs). Ex. 1005, ¶ 31. At the
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`early time of integrated circuit technology, only a few (usually less than about 100)
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`transistors were included in an integrated circuit, and such a level of integration is
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`referred to as small-scale integration (SSI). Ex. 1005, ¶ 32. With the development
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`of improved semiconductor processing technology, more and more transistors were
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`integrated to form a single integrated circuit. Id. Depending on the number of
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`transistors in the integrated circuit, later generations of integration technology are
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`usually referred to as medium-scale integration (MSI, including about 100 to about
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`1000 transistors), large-scale integration (LSI, including about 1000 to about
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`10 thousand transistors), very-large-scale integration (VLSI, including about
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`10 thousand to about 1 million transistors), and ultra-large-scale integration (ULSI,
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`including about 1 million or more transistors)1. Id.
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`1 There is no universal consensus about the number of transistors in each
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`generation. These ranges are only for illustrative purposes. Ex. 1005 at 12, n.2.
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`To form an integrated circuit, transistors need to be electrically coupled to
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`each other by interconnections, which are electrical conductors that provide
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`pathways for electrical signals. Id., ¶ 33. Interconnections can be made from a
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`variety of conducting materials, such as metals, metal alloys, metal compounds,
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`highly doped polycrystalline silicon (polysilicon), or combinations of these (e.g.,
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`metal-silicon compounds, called “silicides”). Id.
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`With increasing integration scales and decreasing sizes of individual
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`transistors, multilevel interconnection structures were increasingly utilized for
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`increasing both the circuit densities and operation speeds of integrated circuits. Id.,
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`¶ 34; see also, e.g., Ex. 1001, 1:28-33; Ex. 1003, 1:21-25; Ex. 1006, 1:42-45; Ex.
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`1007, 1:44-46. Such multilevel interconnection structures have existed for over
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`50 years. Ex. 1005, ¶ 34. For example, U.S. Patent No. 3,617,824 to Shinoda et al.
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`(“Shinoda,” Ex. 1004), which has an earliest priority date of 1965, discloses
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`multilevel interconnections formed between transistors in an integrated circuit,
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`including lower level interconnects (shown in the annotated figures below in blue)
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`and upper level interconnects (in green) separated by insulating material (in red).
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`Ex. 1004, FIGS. 6 and 7 (reproduced below); see also Ex. 1003, FIG. 5; Ex. 1006,
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`FIG. 1; Ex. 1005, ¶ 34.
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`Annotated FIG. 6 of Shinoda (Ex. 1004)
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`Annotated FIG. 7 of Shinoda
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`B. Dielectric Materials
`As mentioned above, the semiconductor industry has steadily moved towards
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`packing more transistors onto one chip, by reducing the size of individual
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`transistors and/or reducing the distance between individual transistors. Ex. 1005,
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`¶¶ 32-34, 36; see also, e.g., Ex. 1001, 1:29-34. As a result, device densities in an
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`integrated circuit increase and interconnects, such as metal wires, within the
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`integrated circuits become packed closer together. Ex. 1005, ¶ 36; see also, e.g.,
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`Ex. 1001, 1:29-34. However, various design restrictions limit further shrinking of
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`the sizes of individual transistors and reducing distances between interconnects. Ex.
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`1005, ¶ 35.
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`One major concern with scaling integrated circuits to smaller sizes and higher
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`densities is the capacitance, also referred to as parasitic capacitance, between the
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`interconnects. Id., ¶ 36. The parasitic capacitance increases with reduced distance
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`(or “pitch”) between two interconnects, which is undesirable because increased
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`parasitic capacitance can increase signal delay times, crosstalk, and power
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`dissipation in the integrated circuit. Id.; see also, e.g., Ex. 1007, 1:50-57 (“As
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`device geometries shrink and functional density increases, it becomes imperative to
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`reduce the capacitance between the lines . . . Reducing the capacitance within these
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`multi-level metallization systems will reduce the RC constant, crosstalk voltage,
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`and power dissipation between the lines.”).
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`The parasitic capacitance between two interconnects is also proportional to
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`the dielectric constant of the material between the interconnects. Ex. 1005, ¶ 37.
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`Therefore, one approach to reduce the parasitic capacitance is to use a dielectric
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`material having a relatively small dielectric constant (also referred to as “low”
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`dielectric constant or low-k) between the interconnects. Id.; see also, e.g., Ex. 1007,
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`1:66-67, 4:30-47, 2:5-6. Dielectric constants of materials, as would have been
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`understood by a POSITA at the time the ’980 patent’s application was filed, are
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`based on a relative scale, where 1.0 represents the dielectric constant of vacuum.
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`Ex. 1005, ¶ 37; Ex. 1007, 1:64-66.
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`Silicon dioxide (often referred to as “silicon oxide”) is a widely used
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`dielectric material for separating different layers of interconnects in a
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`semiconductor device and for isolating interconnects within the same layer. Ex.
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`1005, ¶ 38. The dielectric constant of silicon oxide may depend on how dense it is.
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`Id. For example, dense silicon oxide grown by thermal oxidation or chemical vapor
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`deposition has a dielectric constant on the order of about 3.9. Id.; see also Ex. 1007,
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`1:62-64; Ex. 1009 at 9, Table 2.1.
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`Further decreasing distances between interconnects raises the need for
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`dielectric materials having even smaller dielectric constants. Ex. 1005, ¶ 39. Such
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`dielectric materials can be created by doping silicon oxide with another element,
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`such as fluorine, carbon, or hydrogen, or by making silicon oxide porous. Id.; see
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`also Ex. 1001, 2:32-33 (admitted prior art includes “silicon oxide film doped with
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`fluorine . . . having a small dielectric constant” to suppress parasitic capacitance
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`between metal wires); Ex. 1007, 2:1-4. Some organic materials with small dielectric
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`constants, such as polyimide, polynorbornenes, and organic spin-on glass (SOG)
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`material, can also be used. Ex. 1005, ¶ 39; see also Ex. 1001, 2:33.
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`United States Patent No. RE41,980
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`While low-dielectric-constant materials can reduce parasitic capacitance, they
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`usually absorb moisture more easily than denser materials (which often also have
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`higher dielectric constants), and such moisture absorption can reduce the reliability
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`of the semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1001, 2:30-34. To prevent
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`moisture from entering the semiconductor device through the low-dielectric-
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`constant material, a passivation layer (sometimes also called a “protective”
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`dielectric layer) can be formed over the upper-most layer of low-dielectric-constant
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`material in a semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1006, 2:5-10. The
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`passivation layer usually is formed, for example, using silicon nitride or silicon
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`oxynitride, which have higher moisture-blocking functions and higher dielectric
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`constants than silicon oxide. Ex. 1005, ¶ 40; Ex. 1006, 2:5-7.
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`C. Bonding Pads
`Bonding is often used to electrically couple an integrated circuit with its
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`packaging or other electronic devices, where a conducting bonding material, e.g., a
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`gold or aluminum wire, solder bump, copper pillar, or other external connection, is
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`bonded to a bonding pad of the integrated circuit. Ex. 1005, ¶ 41. A bonding pad
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`usually includes a metal area having an appropriate horizontal size to facilitate
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`bonding to the bonding material, and is electrically coupled to other conducting
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`parts, such as the interconnects, of the integrated circuit. Id. For example, FIG. 11
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`(reproduced and annotated below) of U.S. Patent No. 5,394,013 to Oku et al.
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`(“0ku,” Ex. 1010) schematically illustrates a bonding pad 11 (in pink) connected to
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`a second aluminum film 45 (in red), which in turn is connected to a first aluminum
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`film 43 (in brown). Ex. 1005, 1[ 41.
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`Bonding pad
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`G.
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`PR|0R ART First a1u111111u111 111111
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`Second aluminum film
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`
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`Annotated FIG. 11 of Oku (Ex. 1010)
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`Usually, there are two types of bonding pads. The first type is formed directly
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`using one of the interconnect layers, usually the uppermost interconnect layer, of
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`the integrated circuit, i.e., a portion of the interconnect layer fimctions as the
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`bonding pad- Ex- 1005, 1] 42; Ex. 1006, FIG. 1 (showing an interconnect layer 10
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`with two representative interconnect lines, where one of the interconnect lines has a
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`top surface that also fimctions as a bonding pad 14).
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`United States Patent No. RE41,980
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`Interconnect layer
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`Bonding Pad
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`Interconnect layer
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`FIG, 1
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`PRIORART
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`Annotated FIG. 1 of Wollesen (Ex. 1006)
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`The second type of bonding pad includes conductive pads that are separately
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`formed on one of the interconnect layers, usually the uppermost interconnect layer,
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`of the integrated circuit. Ex. 1005, 1] 43; Ex. 1003, FIG. 5 (showing a bonding pad
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`46 that is formed in an opening on interconnect layer 35 and 36).
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` \
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`'7
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`Jf{)“5
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`Annotated Fig. 5 of Ting (Ex. 1003)
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`10
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`45
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`§
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`:3‘
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`Int
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`t 1
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`For either type of bonding pad, an opening is formed in the uppermost
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`dielectric layers (e.g., shown in FIG. 5 of Ting reproduced above), or merely
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`through a passivation layer if it directly overlies an area of the interconnect layer
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`used for forming the bonding pad (e.g., shown in FIG. 1 of Wollesen reproduced
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`above), to either expose a portion of the interconnect layer that will function as a
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`bonding pad, or to fill the opening with a metal that will function as the bonding
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`pad. Ex. 1005, ¶ 44.
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`III. THE ’980 PATENT
`A. Overview of the ’980 Patent
`The ’980 patent discloses “a semiconductor device which has a small
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`parasitic capacitance in an area with a small pitch between metal wires and is free
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`from a coverage defect as well as the moisture absorption through the opening for
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`the bonding pad.” Ex. 1001, Abstract. While seemingly complicated, the ’980
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`patent simply describes prior art. Ex. 1005, ¶ 47.
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`Specifically, the ’980 patent acknowledges a prior-art technique where an
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`“underlying insulating film 19 of a thin silicon film,” which refers to a silicon-based
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`dielectric film (Ex. 1005, ¶ 47, noting silicon alone is not an insulator) is first
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`deposited between adjacent metal wires 12. Then, a “passivation film 14 of a silicon
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`nitride film” is deposited over the top of the semiconductor device. Ex. 1001, 1:35-
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`2:29, FIGS. 18-21. The passivation film 14 is described as having “a large dielectric
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`11
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`constant” (Id., 2:15-17), implying the underlying insulating film 19 has a lower
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`dielectric constant. Ex. 1005, ¶ 47.
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`In further describing the prior art, the ’980 patent teaches that when the low
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`dielectric film 19 is removed and the silicon-nitride passivation film 14 fills the
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`areas between metal wires with a small pitch (e.g., as shown in FIG. 20(b)), the
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`moisture absorption resistance of the device improves but the parasitic capacitance
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`between the metal wires increases. Id., 2:19-25, FIG. 20(b). In other words, while
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`the low-dielectric-constant film 19 in prior-art devices has the advantage of
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`reducing parasitic capacitance between the metal wires compared to a higher
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`dielectric constant film, such as silicon nitride, the higher-dielectric-constant film
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`14 is a better barrier for moisture absorption. Ex. 1005, ¶ 48.
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`The ’980 patent then purports to solve a problem by using a conventional
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`dual-layered low-dielectric/high-dielectric film. With reference to FIGS. 18 and 21
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`(labeled prior art), the ’980 patent identifies a path through which moisture could
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`enter a conventional semiconductor device having the same passivation film 14 and
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`underlying insulating film 19 discussed above. In this device, a metal wiring layer
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`contains metal wires 12 and “a bonding pad 15 formed out of the same metal film
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`as metal wires 12” for providing external electrical connections. Id., 1:52-57. The
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`’980 patent suggests that when an opening 21a for the bonding pad 15 is created
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`through the films 19 and 14, the low-dielectric-constant insulating film 19 would
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`become exposed along a side wall of the opening 21a, thereby providing a path for
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`moisture absorption. This path is shown in FIG. 21 (copied below). Ex. 1005, ¶ 49.
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`The proposed invention of the ’980 patent, then, is to merely close the
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`opening through which moisture could enter the low-dielectric insulating film 19
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`along the side wall of the opening 21a. The patent discloses various embodiments
`
`where the top-most passivation film 14 and the bonding pad 15 completely cover
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`any potential ingress paths to the insulating layer 19. For example, FIG. 5 shows an
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`embodiment where the passivation film 14 covers the top surface of an underlying
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`insulating film 13 and a bonding pad 15 covers the side walls of opening 20a,
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`thereby preventing the insulating film 13 from being exposed on the side wall of
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`opening 20a. Ex. 1005, ¶ 50.
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`13
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`FIG. 5 of ’980 Patent
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`FIG. 1 shows another embodiment where the bonding pad 15 fills the
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`opening 20a and partially overlaps the top surface of the passivation film 14, again
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`ensuring there is no exposed surface of the underlying insulating layer 13 on the
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`side wall of the opening 20a. Ex. 1005, ¶ 51.
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`FIG. 1 of ’980 Patent
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`14
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`United States Patent No. RE41,980
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`FIGS. 8 and 16 of the ’980 patent show yet other embodiments of the alleged
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`invention where the passivation film 14 partially overlaps the top surface of the
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`bonding pad 15, with the same result of ensuring there is no exposed surface of the
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`underlying insulating layer 13 on the side wall of opening 20a. Ex. 1005, ¶ 52.
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`FIGS. 8 and 16 of ’980 Patent
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`15
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`United States Patent No. RE41,980
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`B. Challenged Claims2
`The two challenged independent claims of the ’980 patent recite:
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`18. A semiconductor device comprising:
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`[18.1] a semiconductor substrate bearing semiconductor elements;
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`[18.2] an interlayer insulating film formed on said semiconductor
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`substrate;
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`[18.3] a metal wire layer including plural metal wires formed on said
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`interlayer insulating film;
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`[18.4a] a surface protecting film including a first dielectric film with a
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`small dielectric constant for filling at least a part of areas among
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`said metal wires in said metal wire layer and
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`[18.4b] a second dielectric film with a higher moisture absorption
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`preventing function than said first dielectric film for covering
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`said metal wire layer and said first dielectric film, said second
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`dielectric film having a function of suppressing moisture
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`absorption of said first dielectric film;
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`[18.5] an opening for a bonding pad formed in said surface protecting
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`film; and
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`2 The challenged claims are claims 18, 19, 30-32, 34-36, 47-49, and 51.
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`16
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`United States Patent No. RE41,980
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`[18.6] a bonding pad formed in said opening for obtaining external
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`electrical connection,
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`[18.7] wherein said bonding pad in said opening and said second
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`dielectric film of said surface protecting film completely cover
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`said first dielectric film so as not to expose said first dielectric
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`film.
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`35. A semiconductor device comprising:
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`[35.1] a semiconductor substrate bearing semiconductor elements;
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`[35.2] an interlayer insulating film formed on said semiconductor
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`substrate;
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`[35.3] a metal wire layer including plural metal wires formed on said
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`interlayer insulating film;
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`[35.4a] a surface protecting film including a first dielectric film with a
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`small dielectric constant for filling at least a part of areas among
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`said metal wires in said metal wire layer and
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`[35.4b] a second dielectric film with a higher moisture absorption
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`preventing function than said first dielectric film for covering
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`said metal wire layer and said first dielectric film, said second
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`dielectric film having a function of suppressing moisture
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`absorption of said first dielectric film;
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`17
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`[35.5] an opening for a bonding pad formed in said surface protecting
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`film; and
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`[35.6] a bonding pad formed in said opening for obtaining external
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`electrical connection,
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`[35.7] wherein said bonding pad covers said opening and said second
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`dielectric film of said surface protecting film completely covers
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`said first dielectric film so as not to expose said first dielectric
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`film.
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`IV.
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`STATEMENT OF PRECISE RELIEF REQUESTED
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`A.
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`Claims for Which Review is Requested
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`Petitioner requests review under 35 U.S.C. § 311 of claims 18, 19, 30-32,
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`34-36, 47-49, and 51, and the cancellation of those claims as unpatentable.
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`B.
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`Statutory Grounds of Challenge
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`Claims 18, 19, 30-32, 34-36, 47-49, and 51 are unpatentable based on 35
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`U.S-C. §§ 102 and 103 as follows:
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`i3f'fi»'s Wollesen in View ofJeng ’ 34-36’
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`103
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`18
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`C. Level of Ordinary Skill
`A person of ordinary skill in the art (“POSITA”) at the time the application
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`leading to the ’980 patent was filed would have an equivalent of a Master of
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`Science degree from an accredited institution in electrical engineering, materials
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`science, or physics, or the equivalent, a working knowledge of semiconductor
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`processing technologies for integrated circuits, and at least two years of experience
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`in semiconductor processing analysis, design, and development. Ex. 1005, ¶ 54.
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`Additional graduate education could substitute for professional experience, and
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`significant work experience could substitute for formal education. Id.
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`D. Claim Construction
`Claim terms are given their ordinary and accustomed meaning as understood
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`by a POSITA. Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en
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`banc). Because the ’980 patent will expire on September 8, 2017, the Phillips
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`standard should be applied to claim terms construed in this proceeding. See, e.g., 37
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`C.F.R. § 42.100(b).
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`V. CLAIMS 18, 19, 30-32, 34-36, 47-49, AND 51 OF THE ’980 PATENT
`ARE UNPATENTABLE OVER THE PRIOR ART
`A. Disclosures of the Prior Art
`The inventors of the ’980 patent were not the first to use bonding pads and/or
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`moisture-blocking passivation layers in a multilayer wiring structure to prevent a
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`low-dielectric-constant insulating layer from becoming exposed to moisture.
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`19
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`1. Wollesen
`U.S. Patent No. 5,659,201 to Wollesen (“Wollesen”) teaches every element of
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`the challenged claims. Wollesen was filed June 5, 1995, and issued on August 19,
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`1997. Wollesen qualifies as prior art to the ’980 patent under pre-AIA 35 U.S.C.
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`§ 102(a) and (e). Wollesen was neither considered nor cited during prosecution of
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`the ’980 patent.
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`Wollesen discloses, “The present invention relates to a semiconductor
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`device.” Ex. 1006, 1:5. Referring to the colored and annotated illustration of the
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`semiconductor device in FIG. 1 of Wollesen below, Wollesen teaches a
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`semiconductor substrate (1) (Ex. 1006, 1:53) including a transistor gate (4) (id.,
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`1:63, 1:55), source/drain regions (3) (id., 1:52-57, 1:62), and a gate oxide (5)
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`therebetween (id., 1:55-58), a dielectric layer (9) (id., 1:63-66), a wire bonding
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`layer (10) (id., 2:1-3, 2:13), a dielectric layer (12) (id., 2:3-4), a protective
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`dielectric layer (13) (id., 2:5-7, 2:10-11), and a bonding pad (14) (id., 2:14). Ex.
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`1005, ¶ 57.
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`Dielectric layer
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`Wire bonding
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`Protective dielectric layer Bonding pad
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`layer
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`Wire bonding
`la er
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`2 ””’
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` [G 17PR'ORAR
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`Transistor‘
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`Dielectric
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`layer
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`Semiconduct