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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and SK HYNIX
`MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B2)
`____________
`
`Record of Oral Hearing
`Held: February 14, 2018
`____________
`
`
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and SHEILA F.
`McSHANE, Administrative Patent Judges.
`
`
`
`

`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH MICALLEF, ESQUIRE
`STEVEN S. BAIK, ESQUIRE
`THEODORE W. CHANDLER, ESQUIRE
`WONJOO SUH, ESQUIRE
`Sidley Austin, LLP
`1501 K Street, N.W.
`Washington, D.C. 20005
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`MEHRAN ARJOMAND, ESQUIRE
`DAVID S. KIM, ESQUIRE
`Morrison & Foerster, LLP
`707 Wilshire Boulevard
`Los Angeles, CA 90017-3543
`
`and
`
`WAYNE BRADLEY, ESQUIRE
`THOMAS J. WIMBISCUS, ESQUIRE
`McAndrews, Held & Malloy, Ltd.
`500 West Madison Street, 34th Floor
`Chicago, Illinois 60661
`
`
`
`The above-entitled matter came on for hearing on Wednesday,
`
`February 14, 2018, commencing at 1:04 p.m., at the U.S. Patent and
`Trademark Office, 600 Dulany Street, Alexandria, Virginia.
`
`
`
`
` 2
`
`

`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`
`P R O C E E D I N G S
`- - - - -
`JUDGE McSHANE: Good afternoon. We are here today. We
`have hearings in case numbers IPR2017-00548, 549, 560, 587. These are
`SK Hynix, a variety of different companies there, America and Memory
`Solutions, Inc., v. Netlist.
`Can we have appearances, please.
`MR. MICALLEF: Good morning, Your Honors. Joe Micallef
`from Sidley Austin for the petitioners. I have a number of lawyers. I don't
`know if you want me to introduce them all now or they can introduce
`themselves when they come up, but at counsel table is Wonjoo Suh, also
`from Sidley.
`JUDGE McSHANE: So you are going to have several people
`speaking today?
`MR. MICALLEF: Yes, Your Honor. I'm going to make the first
`argument and then each proceeding will have a different lawyer making the
`argument.
`JUDGE McSHANE: Okay. We'll introduce them as they come
`through. And for patent owner, please.
`MR. ARJOMAND: Good morning, Mehran Arjomand of
`Morrison & Foerster for patent owner, Netlist. With me today is David
`Kim.
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`
`MR. WIMBISCUS: Good afternoon, Your Honors. Thomas
`Wimbiscus on behalf of Netlist also. With me is Wayne Bradley. Thank
`you.
`
`JUDGE McSHANE: All right. So we sent out a trial order on
`January 25th with a general outline where we'll allow 30 minutes per side
`per case. And that was the general allocation. Any comments on that
`allocation? Is that how you want to proceed?
`MR. MICALLEF: That's fine with us, Your Honor.
`MR. ARJOMAND: Fine with us, Your Honor.
`JUDGE McSHANE: Thank you. So the way that we are going to
`do this is petitioner is going to start. They'll present their case, each specific
`case as we go along. We are doing each case separately as we move
`through. I assume we are going to start with the 548 case?
`MR. MICALLEF: Yes, Your Honor.
`JUDGE McSHANE: And then patent owner is going to present its
`opposition, and petitioner can reserve rebuttal time. Now, I assume you are
`going to use demonstratives here. And if you could, and I know it's
`sometimes tough when you get going, but if you could try to refer to the
`page number for the exhibits, that would be great, the demonstrative sheets.
`It helps for record purposes and it also helps Judge Clements and Judge Siu,
`who I'll introduce here for the record purposes, who are attending here via
`video. So thank you.
`And let's see, try to use the microphone. That helps the record as
`well. And also please don't interrupt the other party if you have objections.
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`Wait until it's your time to speak and then present those objections during
`your argument time, please.
`And petitioner, you can proceed, please.
`MR. MICALLEF: Thank you, Your Honor. Once again, Joe
`Micallef from Sidley for petitioner in the 548 matter. I would like to reserve
`10 minutes of my time for rebuttal.
`Your Honor, this proceeding involves the '837 patent. The Board
`has instituted trial on two grounds, one on the combination of LeClerg and
`Lee and another ground on the combination of LeClerg, Lee and Kim.
`Now, I have a lot of slides here. I don't expect that I'm going to
`use all of them. I may skip over a few. I'm happy to jump back or forward
`and deal with whatever Your Honors would like to deal with in whatever
`order, but I don't actually intend to use all of them. I have put together a
`basic roadmap that I would like to go through. But again, if there's any
`reason to jump around, please let me know.
`I'm going to start with just a very basic overview of the '837 patent.
`It's directed to systems and methods for handshaking with a memory
`module. It describes and claims a memory module that can be put into an
`initialization mode and provide a notification signal back to the memory
`controller providing a status on that initialization. The patent says that the
`module can be in two different modes, an initialization mode and operational
`mode and explicitly says that in either mode a standard memory operation
`such as read and write, recharge and refresh can be used.
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`
`The claim, there's one independent claim at issue here, independent
`claim 1. It includes an output, a controller circuit, a notification circuit and
`this wherein clause at the end. I guess at this point I just want to point out
`that the claim is actually to a memory module. It's not to a memory system
`or a computer. Just a memory module. And that might be useful later.
`So if I can very briefly introduce the prior art, I assume Your
`Honors have looked at that to some extent. The base reference is the
`LeClerg patent application. It describes a system including a processor
`connected to a memory controller and the memory controller coupled to a
`number of memory modules. These memory modules can also -- are
`described as also being capable of going into an initialization mode and
`operating as you might expect in a normal operating mode.
`The patent breaks out in Figure 2 a functional block diagram or a
`block diagram of one memory module and then -- which include this is
`buffer module and a number of memory devices and breaks out the buffer
`module a little bit more in Figure 3 to include a bus interface, an
`initialization test controller, some registers and an interface to the memory
`devices.
`
`LeClerg says that the memory modules can go perform
`initialization functionality on boot-up or can do so when the system is
`brought up from a sleep mode or low power state.
`Now, LeClerg also describes how the memory modules in his
`system can provide a notification signal for the initialization back to the
`process or via the memory controller. He describes two different
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`embodiments. In Figure 5 it's sort of what you might call a non-polling
`embodiment. In this case when the module is done, the initialization
`procedure, it indicates a process completion, sends a message back up to the
`memory controller that it's done. Figure 6 describes a polling embodiment
`where the memory controller or the processor through the memory controller
`actually polls the memory module for a status of the procedure, the
`initialization procedure, and gets a complete or not complete or some other
`message back.
`The Kim patent, one of the secondary references, is directed to a
`memory device having a standard error feedback pin where a number of
`memory devices on a memory module and a number of memory modules are
`connected to this open drain configured line in order to provide some
`feedback across this error pin or number of error pins.
`The Lee patent is probably not going to be talked about much
`today, I don't think, given the issues that have been raised, but it describes a
`memory controller with an interrupt handler and a microprocessor.
`So if I can just move to the single claim construction issue, that is
`the word "mode", the Board has not construed this. I have a slide about that.
`It's not really that interesting. I just have it here to remind myself to say that
`the Board has not addressed this yet in the institution decision. I think there
`may be at least some agreement on this. As we pointed out in our brief, our
`side and at least the other side's expert agrees that the word "mode" in the
`'837 patent is used in its plain and ordinary sense. And indeed, Netlist has
`not attempted to show a disclaimer of any type or kind of special clear
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`definition. So I think that's probably resolved. It's got to be -- it is used in
`its plain and ordinary sense.
`Now, Netlist has proposed an interpretation for this word. Their
`interpretation is -- I'm sorry. I'm not calling out the slides. This is slide 10
`I'm looking at now. This is their interpretation is a distinct behavioral state
`that a system may be switched to.
`As you may recall from the briefing and now I'm just looking at
`slide -- I guess this is 20. I'm sorry, the last one was 19. Slide 20, I asked
`Netlist's expert about this, Mr. Murphy, and what I have on this slide, just so
`Your Honors understand, that chart at the top of this slide comes from
`Mr. Murphy's expert declaration. And this is from the page that he had
`before him when this testimony on this slide was given. And I asked him, Is
`it your view that the interpretation you are proposing here is just the ordinary
`meaning of the word "mode" to a person of ordinary skill in the art reading
`the '837 patent?
`And he says, No. And he explains it more, but he says no. And I
`think the explanation is inarguable that he says no, it's not just the plain and
`ordinary meaning.
`Well, I think that creates something of a dilemma for Netlist
`because it's absolutely agreed, I think, that mode is used in its ordinary sense
`and the interpretation that they are proposing is not the plain and ordinary
`meaning of the word "mode." And I think we talked about that in our reply
`brief, but I want to highlight one reason it is plainly not the plain and
`ordinary meaning. And that is sort of an implicit spin, in my view, an
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`implicit narrowing that they are putting on the words that they have put in
`this interpretation. And we saw it from their own patent owner response.
`This is slide 21, patent owner response at 7. They are arguing that
`LeClerg does not have the two claimed modes because in LeClerg, the
`initialization functionality uses regular memory accesses like read and write
`and refresh, et cetera, and so that therefore, the initialization is not a separate
`or distinct mode from the normal operating mode. And so that in that sense
`I suggest that what they are doing is they are putting a spin on this word or
`these words "distinct behavior" or "distinct behavioral state" to say what that
`really means is you cannot use the same memory commands or the
`commands you use in each mode must be mutually exclusive.
`That is not the plain and ordinary meaning of the word "mode," I
`think. It's not the plain and ordinary meaning of the phrase "distinct
`behavioral state." And it's completely inconsistent with the patent
`specification. This is slide 22. Column 6 of the patent, I think, as we
`pointed out, it plainly says in this passage that the system memory controller
`may cause the memory module to perform standard operation such as
`memory write/read, pre-charge and refresh while in the operational mode.
`And this is the '837 patent now. And then it says, Although it will be
`appreciated that one or more of these operations can also be performed by
`the memory module while in initialization mode.
`So it's clear that in the '837 patent this notion that the modes must
`have mutually exclusive operations or memory operations is just not true.
`That notion is inconsistent with the express teachings of the '837 patent. So
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`that understanding of the word "mode" has to be rejected as a matter of
`claim construction.
`If there are no further questions on mode, I would like to move to
`the arguments that Netlist has advanced for claim 1 or the wording of claim
`1, I should say. The first argument, the main flavor of it here is on slide 26
`that they say that the two modes that LeClerg discloses are not the two
`claimed modes because those modes in LeClerg are a low power sleep mode
`and a normal power mode. Now, this is a complete straw man. This '837
`patent doesn't have anything to do with power modes. That's completely
`irrelevant. And the fact that LeClerg uses the word "mode" in some way
`related to power levels is also irrelevant.
`The question is whether the operations, the LeClerg operations that
`we identified in the petition correspond to the claimed modes as that word
`"mode" is used in the '837 patent. That's the question here. And in the '837
`patent, the initialization mode is simply a mode or state during which
`initialization procedures or functionality occurs. That's exactly what
`LeClerg discloses. During boot-up, for example, it's mode or state during
`which initialization functionality occurs. It is exactly what's disclosed in the
`'837. So LeClerg has that mode. LeClerg also discloses operating these
`memory modules in sort of a normal operating sense, so it has the
`operational mode also. So these power modes is just a straw man and
`irrelevant.
`I think even their expert has agreed with me on that. I asked him
`under cross-examination, this is slide 27, Whether this interpretation on
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`page 17 of mode is correct or not, can we agree that the proper interpretation
`really shouldn't turn on power levels?
`He says, Yeah, I think that would be an accurate assessment.
`So he's completely run away from this notion that power modes or
`power levels have anything to do with the claims of the '837. And he had to.
`He had to because the claims don't say that and the specification of the '837
`patent doesn't say anything about power levels. It's just completely
`irrelevant.
`So let me -- one more point about this. It's also clear not only that
`LeClerg discloses the exact same modes that are in the '837 patent. It's also
`clear that LeClerg discloses that they are distinct behaviors. Now, I have
`slide 28 here, and this is just -- I think I showed this passage before. This is
`just LeClerg saying that this memory initialization is performed upon
`boot-up. Okay. And there's another slide 29 that shows from LeClerg that
`talks about the normal operations, the sort of read and write commands to a
`memory module in the normal sense. And as Netlist's expert agreed, and
`this is slide 30, he would definitely agree, he said, that operational mode
`would not be generally present when you are booting up.
`So these two modes in LeClerg are clearly distinct behavioral
`states into which the system can be switched anyway, right, because you
`have in initialization mode, initialization procedures occurring that are not
`occurring in normal mode. So they are distinct in that sense, but they are
`also distinct in the sense that that operational mode is not going to occur
`during boot-up when initialization occurs.
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`
`So my point is I think their interpretation, how they are spinning it
`is dead wrong. But if that you actually adopted their words and give those
`words their ordinary meaning, LeClerg discloses it based on all of the
`operations that we put in the petition anyway. So there's no question that
`LeClerg discloses these claim modes.
`They have also -- Your Honor, is that my time left?
`JUDGE McSHANE: I put that in as 20 minutes. So if you go
`over, that's fine.
`MR. MICALLEF: I thought that went fast. So I'll be very brief on
`these next three arguments. There's a claimed controller circuit in claim 1.
`They say LeClerg doesn't teach it because the test controller 304, which is
`what we identified in the petition, does not cause the memory controller to
`enter normal power mode from low power mode. And I'm reading from
`slide 32, patent owner response at 13.
`Once again, that's irrelevant. Power mode have nothing to do with
`this patent. And in fact, if I can jump ahead to slide 34, this is paragraph 46
`from LeClerg. It says plainly that the initialization test controller actually is
`the thing that causes the module to begin the process of initializing. It looks
`in some registers for a message, and once it realizes that it has been told to
`do it, the test controller starts the process. There's no question that claim
`element satisfies LeClerg.
`If I can go to slide -- talk about the notification signal, this is slide
`37. This is a little puzzling to me. This is from the patent owner response at
`14. The claims, of course, require the module to send a notification signal
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`up to the memory controller. Patent owner has characterized our argument
`as identifying not a signal but a plurality of wires, which is not an accurate
`characterization of what is in the petition. The petition, as we said, this is
`slide 38, the petition at pages 25, 33, 34, as I said earlier, we pointed to these
`notification signals in Figure 5 and Figure 6 that provide status of the
`initialization procedures. And we also cited -- this is slide 39. We cited the
`paragraph describing those signals. And what's really puzzling about this
`argument from the patent owner is I think we pointed this out in our reply,
`and this is slide 40, they knew what we were accusing. This is their
`preliminary response at 8, and they noted that what we were really accusing
`as the at least one notification signal was LeClerg's initialization complete
`message and/or processor interrupt. I think it wasn't just that, but that was
`one example of it. That's the thing in Figure 5 of LeClerg. So this is an
`entirely mysterious argument of theirs.
`Finally, the last issue I want to talk about as far as claim 1 is this
`notion that they are arguing that LeClerg doesn't disclose sending a
`notification signal to the processor -- I'm sorry, sends it to the processor.
`Not to the memory controller. That is also absolutely incorrect. And once
`again, their expert has simply pulled the rug out from under them on this.
`LeClerg, of course, only discloses one way for the memory module to send
`messages to the processor, and that is through the memory controller. I'm
`looking at slide 43. This is Figure 1 of LeClerg.
`In fact, LeClerg says, this is slide 44, in his paragraph 34 he
`explicitly says that the messages that get sent from the module up to the
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`memory controller can include initialization and/or test status messages. So
`if that's not enough, this is slide 45, I cross-examined their expert on it. I
`asked him, Would you agree that the communications sent from the buffer
`module 202 on the upstream channel to the memory controller could include
`initialization status messages?
`And his answer after I had shown him all this: Based on what I
`have read in LeClerg, yes.
`So they have no leg to stand on there and they are absolutely
`wrong, and their expert agrees with me on that.
`So let me just briefly talk about claim 5. Claim 5 only adds one
`thing to claim 1. This is a dependent claim that depends off of claim 1. I'm
`looking at slide 47 right now. It says where the at least one output, which is
`a structure recited i claim 1, comprises an error output pin. Comprises,
`includes an error-out pin. I think it's clear that that means the at least one
`output can be multiple pins, but one of them has to be an error-out pin.
`They say, Netlist says, well, what that actually means -- and here
`this is slide 48. What that actually means is claim 5 has to have all kinds of
`other functionality, including the error-out pin has to be driven by the
`notification circuit and it has to be essentially the pin over which the
`notification signal to the memory controller goes. That's what I think all
`those words there mean.
`Obviously all those extra words are not in claim 5. As far as I can
`tell, their theory is that because those limitations are recited in claim 1 as
`being limiting the at least one output, in claim 5, if you add an error output
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`pin, they must apply to the error-out pin as well. That is not accurate. There
`is no legal principle that says a patentee cannot claim in this manner so that
`the error-out pin is not the part of the at least one output that does everything
`in claim 1. That is, you can imagine a system with, say, 10 pins, one of
`them an error-out pin, and the notification signal goes out over a different
`pin. It can be claimed that way, right. It's a broader way of claiming.
`They could have claimed it more narrowly like they are now
`suggesting it should be read. Although, I note they have not asked you to
`interpret this claim in that manner. There's no proposed claim interpretation.
`They are just saying that's what it means. But they didn't claim it that way.
`All claim 5 says is you add an error-out pin to that at least one output. And
`this is the conclusion the panel came to in the institution decision. This is
`slide 49. As the panel put it, claim 5 does not recite any specific function of
`the error-out pin at all.
`Now, I recognize that you are not bound, the Board is not bound
`by a claim interpretation decision in the institution decision. But I would
`like to point out that if you simply maintain your position on this issue, the
`position expressed in the institution decision, that all of their arguments on
`claim 5 go away, because they are all based on this implicit interpretation of
`claim 5 that all this information, all these other limitations have to be applied
`to that error-out pin. So if you just stick with what you did in the institution
`decision, those arguments have to be rejected.
`But one more point, I have 14 seconds -- less than that. As we
`pointed out in the reply brief, and this is slide 50, the analysis we put in the
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`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`petition would mean claim 5 is unpatentable even under their interpretation
`because our analysis, the analysis we put in the petition was that the
`combination of LeClerg and Kim would have the notification signal being
`sent to the memory controller over the error-out pin. And we showed how
`that was described -- and this is on claim 50 [sic] I show it again. We
`explain that in detail with respect to claim 3 which was the first time in the
`petition where we described this particular combination in what we were
`proposing as this combination. And then in the analysis of claim 5, we
`noted as demonstrated above, we said, and referred back to it. So I think
`there's no question you were right in the institution decision in your
`interpretation of claim 5. You ought to maintain that. But even if you don't,
`this claim unpatentable.
`So I have nothing further at this point and would like to reserve the
`rest of my time for rebuttal.
`JUDGE McSHANE: Yes, you have nine minutes for rebuttal.
`MR. ARJOMAND: Good afternoon, Your Honors. May it please
`the Board, turning to slide 2, I believe that this case for the purposes of this
`hearing boils down to three issues. One is the construction of the term
`"mode." Two is the deficiencies of LeClerg once you properly construe the
`term "mode." And three is the patentability of claim 5.
`So turning to slide 3, the claim has a base term, "mode," that was
`not construed by the petitioner in the petition. Specifically the claim says
`that the memory module is configured to operate in at least two modes, that's
`the base term "mode," comprising an initialization mode during which the
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`memory module executes at least one initialization sequence and an
`operational mode.
`We believe construing that base term "mode" is critical for the
`purposes of this IPR proceeding. Our construction for the term "mode" is a
`distinct behavioral state that a system may be switched to. And that
`construction is based on the claim language. First of all, the claim
`specifically recites an initialization mode and an operational mode. Those
`are distinct elements. And because they are distinct elements in the claim
`language, they must be given weight.
`Second of all, the claim says controller circuit configured to cause
`the memory module to enter the initialization mode. That provides the
`concept of switching between modes or switching from a mode. So we
`believe that's supported, again, by the claim language.
`So you might ask why did we include the language "behavioral
`state?" What is added by that language "behavioral state?" And the reason
`we added that language is that the patent itself discusses "state" separately
`from the term "mode." So in our view, for example, at column 7, lines 22 to
`26, state didn't quite grasp or reflect the term "mode."
`Furthermore, we also looked to the concept of operations or
`processes or as my colleague here mentioned, functionalities. And that also
`does not quite sort of address the concept here because the patent, for
`example, as my colleague pointed out, does refer to two modes employing
`the same operations and yet it still calls those two modes different names, an
`initialization mode and an operational mode. So it can't just be the fact that
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`

`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`there are overlapping operations between the modes. So what we focused on
`was the term "behavioral state" or "behavior" because that's reflected in the
`specification. The specification at column 7, lines 53 to 58 refers to the
`behavior. It utilizes that language, and we believe that language clarifies the
`concept of mode beyond state or operations. And once you have that, sort of
`see that, I think it's easy to understand why we believe our construction is
`the correct one.
`So let me give you an example from the record of what we are
`trying to get at. So in LeClerg, we saw -- so I'm at slide 8 here. In LeClerg
`there's a discussion of the memory module being revived from a low power
`mode. So the concept there is that it's a low power mode that's being revived
`from, i.e., that's being switched from. And sort of the implied inverse of the
`low power mode would be a normal mode. So there are two modes that the
`memory module in LeClerg is switching from, between a low power mode
`and a normal power mode.
`And then in each state you have very different behavior. So in the
`low power mode you have, for example, as paragraph 18 says, the memory
`module is asleep. And in the normal mode, the memory module is not
`asleep. It's distinct behavior.
`Now, they emphasize in their papers and today you heard at the
`hearing how could that be? Are you trying to say they have to have distinct
`operations? No. You could have the same operations in two different
`modes but yet still when you look at each mode, the behavior is very
`different as a whole. So for example, in the low power mode, you might still
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`

`Case IPR2017-00548 (Patent 8,489,837 B1)
`Case IPR2017-00549 (Patent 8,756,364 B1)
`Case IPR2017-00560 (Patent 8,689,064 B1)
`Case IPR2017-00587 (Patent 8,671,243 B21)
`
`be looking for inputs to wake up the memory module, and in the normal
`mode you might still be looking at inputs in terms of operations. In both
`modes you have the same processes of looking for inputs, but of course
`when you look at the two concepts or the two modes as a whole, they are
`very different behaviors. The low power mode is a very different behavior
`than in normal power mode. And that, we think, is sort of the critical
`concept here.
`And once that concept is reflected or understood, then it's this case,
`with all due respect, is a very simple case because LeClerg is missing
`expressly, blatantly, however you want say, one of the two modes. The
`claim recites in its initialization mode and an operational mode. A

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