U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`Filed on behalf of GlobalFoundries U.S., Inc.
`By: Christopher Carroll, Reg. No. 55,776
`White & Case LLP
`75 State St
`Boston, MA 02109
`Tel: (617) 979-9300
`Email: ccarroll@whitecase.com
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`
`
`
`GlobalFoundries U.S. Inc.
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`Patent Owner
`
`Case No. IPR2017-00903
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. RE41,980
`
`
`
`

`

`
`
`I.
`
`II.
`
`U. S. PATENT NO RE41,980
`Petition for Inter Partes Review
`
`TABLE OF CONTENTS
`
`PRELIMINARY STATEMENT ................................................................. 1
`
`The ’980 Patent ............................................................................................ 2
`
`A.
`
` Overview of the ’980 Patent .............................................................. 2
`
`B.
`
`
`
`Challenged Claims ............................................................................ 9
`
`III. Technological Background ........................................................................ 11
`
`A.
`
`
`
`Integrated Circuits ........................................................................... 12
`
`B.
`
` Dielectric Insulating Films .............................................................. 17
`
`C.
`
`
`
`Bonding Pads ................................................................................... 20
`
`IV. STATEMENT OF PRECISE RELIEF REQUESTED ............................. 21
`
`A.
`
`
`
`B.
`
`
`
`C.
`
`
`
`D.
`
`
`
`Claims for Which Review is Requested .......................................... 21
`
`Statutory Grounds of Challenge ...................................................... 22
`
`Level of Ordinary Skill ................................................................... 23
`
`Claim Construction ......................................................................... 23
`
`V.
`
`CLAIMS 18, 19, 30-36, AND 47-51 OF THE ’980 PATENT ARE
`UNPATENTABLE OVER THE PRIOR ART ......................................... 24
`
`A.
`
` Overview of Prior Art ..................................................................... 24
`
`1.
`
`2.
`
`3.
`
`4.
`
`Cheung ................................................................................. 24
`
`Chiang .................................................................................. 25
`
`Shinoda ................................................................................. 27
`
`El-Kareh ............................................................................... 27
`
`ii
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
` Motivation to Combine Prior Art References ................................. 28
`
`B.
`
`C.
`
`
`
`The Challenged Claims are obvious in view of Cheung alone or
`in combination with Chiang, Shinoda and/or El Kareh .................. 31
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`[18.1] and [35.1] Cheung discloses “semiconductor
`device comprising: a semiconductor substrate bearing
`semiconductor elements ...................................................... 31
`
`[18.2] and [35.2] Cheung discloses “an interlayer
`insulating film formed on said semiconductor
`substrate” ............................................................................. 33
`
`[18.3] and [35.3] Cheung discloses “a metal wire layer
`including plural metal wires formed on said interlayer
`insulating film” .................................................................... 40
`
`[18.4a] and [35.4a] Cheung discloses “a surface
`protecting film including a first dielectric film with a
`small dielectric constant for filling at least a part of
`areas among said metal wires in said metal wire layer” . 41
`
`[18.4b] and [35.4b] Cheung discloses “a second
`dielectric film with a higher moisture absorption
`preventing function than said first dielectric film for
`covering said metal wire layer and said first dielectric
`film, said second dielectric film having a function of
`suppressing moisture absorption of said first dielectric
`film” ...................................................................................... 44
`
`[18.5] and [35.5] Cheung discloses “an opening for a
`bonding pad formed in said surface protecting film” ..... 47
`
`[18.6] and [35.6] Cheung discloses “a bonding pad
`formed in said opening for obtaining external electrical
`connection” .......................................................................... 49
`
`[18.7] Cheung discloses “wherein said bonding pad in
`said opening and said second dielectric film of said
`surface protecting film completely cover said first
`
`iii
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`dielectric film so as not to expose said first dielectric
`film” of claim 18 .................................................................. 49
`
`9.
`
`[35.7] Cheung discloses “wherein said bonding pad
`covers said opening and said second dielectric film of
`said surface protecting film completely covers said first
`dielectric film so as not to expose said first dielectric
`film” of claim 35 .................................................................. 51
`
`10. Cheung discloses Patent Owner’s proposed
`construction of [18.7] and [35.7] ........................................ 52
`
`11.
`
`12.
`
`13.
`
`14.
`
`15.
`
`16.
`
`[19] and [36] Cheung discloses “wherein said first
`dielectric film is buried, among said areas among said
`metal wires, at least in an area having a minimum
`pitch between said metal wires” ........................................ 53
`
`[30] and [47] Cheung discloses “wherein said first
`dielectric film is made from at least one oxide film
`selected from the group consisting of a silicon oxide
`film, a silicon oxide film doped with fluorine and a
`porous silicon oxide film, or a composite film including
`an organic insulating film and at least one oxide film
`selected from the group consisting of a silicon oxide
`film, a silicon oxide film doped with fluorine and a
`porous silicon oxide film” ................................................... 54
`
`[31] and [48] Cheung discloses “wherein said first
`dielectric film has a dielectric constant of 3.9 or less” ..... 54
`
`[32] and [49] Cheung discloses “wherein said second
`dielectric film is made from a silicon nitride film” .......... 56
`
`[33] and [50] Cheung discloses “wherein said bonding
`pad directly contacts one of said plural metal wires
`formed on said interlayer insulating film” ....................... 57
`
`[34] and [51] Cheung discloses “wherein said bonding
`pad directly contacts said surface protecting film” ......... 58
`
`
`
`iv
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`The Challenged Claims are obvious in view of Chiang alone or
`in combination with Cheung and/or El-Kareh ................................ 59
`
`D.
`
`
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`[18.1] and [35.1] Chiang discloses “semiconductor
`device comprising: a semiconductor substrate bearing
`semiconductor elements ...................................................... 59
`
`[18.2] and [35.2] Chiang discloses “an interlayer
`insulating film formed on said semiconductor
`substrate” ............................................................................. 60
`
`[18.3] and [35.3] Chiang discloses “a metal wire layer
`including plural metal wires formed on said interlayer
`insulating film” .................................................................... 65
`
`[18.4a] and [35.4a] Chiang discloses “a surface
`protecting film including a first dielectric film with a
`small dielectric constant for filling at least a part of
`areas among said metal wires in said metal wire layer” . 67
`
`[18.4b] and [35.4b] Chiang discloses “a second
`dielectric film with a higher moisture absorption
`preventing function than said first dielectric film for
`covering said metal wire layer and said first dielectric
`film, said second dielectric film having a function of
`suppressing moisture absorption of said first dielectric
`film” ...................................................................................... 71
`
`[18.5] and [35.5] Chiang discloses “an opening for a
`bonding pad formed in said surface protecting film” ..... 74
`
`[18.6] and [35.6] Chiang discloses “a bonding pad
`formed in said opening for obtaining external electrical
`connection” .......................................................................... 76
`
`[18.7] Chiang discloses “wherein said bonding pad in
`said opening and said second dielectric film of said
`surface protecting film completely cover said first
`dielectric film so as not to expose said first dielectric
`film” of claim 18 .................................................................. 78
`v
`
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`

`

`9.
`
`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`[35.7] Chiang discloses “wherein said bonding pad
`covers said opening and said second dielectric film of
`said surface protecting film completely covers said first
`dielectric film so as not to expose said first dielectric
`film” of claim 35 .................................................................. 78
`
`10. Chiang discloses Patent Owner’s proposed
`construction of [18.7] and [35.7] ........................................ 78
`
`11.
`
`12.
`
`13.
`
`14.
`
`15.
`
`16.
`
`[19] and [36] Chiang discloses “wherein said first
`dielectric film is buried, among said areas among said
`metal wires, at least in an area having a minimum
`pitch between said metal wires” ........................................ 79
`
`[30] and [47] Chiang discloses “wherein said first
`dielectric film is made from at least one oxide film
`selected from the group consisting of a silicon oxide
`film, a silicon oxide film doped with fluorine and a
`porous silicon oxide film, or a composite film including
`an organic insulating film and at least one oxide film
`selected from the group consisting of a silicon oxide
`film, a silicon oxide film doped with fluorine and a
`porous silicon oxide film” ................................................... 81
`
`[31] and [48] Chiang discloses “wherein said first
`dielectric film has a dielectric constant of 3.9 or less” ..... 82
`
`[32] and [49] Chiang discloses “wherein said second
`dielectric film is made from a silicon nitride film” .......... 83
`
`[33] and [50] Chiang discloses “wherein said bonding
`pad directly contacts one of said plural metal wires
`formed on said interlayer insulating film” ....................... 85
`
`[34] and [51] Chiang discloses “wherein said bonding
`pad directly contacts said surface protecting film” ......... 85
`
`VI. MANDATORY NOTICES ....................................................................... 86
`
`A.
`
`
`
`Real Party-in-Interest ...................................................................... 86
`
`
`
`vi
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`Related Matters ................................................................................ 86
`
`Lead and Back-Up Counsel ............................................................. 86
`
`Service Information ......................................................................... 87
`
`B.
`
`
`
`C.
`
`
`
`D.
`
`
`
`VII. PAYMENT OF FEES ............................................................................... 87
`
`VIII. TIME FOR FILING PETITION................................................................ 87
`
`IX. GROUNDS FOR STANDING .................................................................. 88
`
`X.
`
`CONCLUSION .......................................................................................... 88
`
`
`
`vii
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`Cases
`
`Cisco Systems Inc. v. Crossroads Systems Inc., IPR2014-01544, Paper 9 (April 3,
`
`2015) .................................................................................................................... 22
`
`In re Crish, 393 F.3d 1253 (Fed. Cir. 2004) ............................................................ 46
`
`Microsoft Corp. v. Parallel Networks Licensing LLC, IPR2015-00486, Paper 10
`
`(July 15, 2015) ..................................................................................................... 22
`
`Motorola Mobility LLC v. Patent of Michael Arnouse, IPR2013-0010, Paper 20
`
`(Jan. 30, 2013) ...................................................................................................... 88
`
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) .................................. 23, 39
`
`Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576 (Fed. Cir. 1996) .................... 39
`
`Statutes
`
`35 U.S.C. § 103 ........................................................................................................ 22
`
`35 U.S.C. §§ 311–319 ......................................................................................... 2, 21
`
`Regulations
`
`37 C.F.R. § 42.100 et seq. ................................................................................... 2, 88
`
`37 C.F.R. § 42.15(a). ................................................................................................ 87
`
`37 CFR § 42.24 ........................................................................................................ 89
`
`37 CFR § 42.8 .......................................................................................................... 89
`viii
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`
`
`LIST OF EXHIBITS
`
`Exhibit 1001:
`
`U.S. Patent No. RE41,980 to Yabu et al.
`
`Exhibit 1002:
`
`File history of U.S. Patent No. 6,232,656 to Yabu et al.
`
`Exhibit 1003:
`
`Expert Declaration of Dr. Sanjay Banerjee.
`
`Exhibit 1004:
`
`U.S. Patent No. 5, 785,236 (“Cheung”)
`
`Exhibit 1005:
`
`U.S. Patent No. 5,739,579 (“Chiang”)
`
`Exhibit 1006:
`
`U.S. Patent No. 3,617,824 (“Shinoda”)
`
`Exhibit 1007:
`
`
`Exhibit 1008:
`
`Exhibit 1009:
`
`
`Exhibit 1010:
`
`Exhibit 1011:
`
`Exhibit 1012:
`
`
`Exhibit 1013:
`
`Exhibit 1014:
`
`
`
`Excerpt of El-Kareh, “Fundamentals of Semiconductor
`Processing Technologies,” Kluwer Academic Publishers (1995)
`(“El-Kareh”).
`
`
`IPR2016-01331, Paper 2 (Petition)
`
`IPR2016-01331, Paper 7 (Patent Owner’s Preliminary
`Response)
`
`IPR2016-01331, Paper 9 (Board Institution Decision)
`
`IPR2016-01367, Paper 2 (Petition)
`
`IPR2016-01367, Paper 7 (Patent Owner’s Preliminary
`Response)
`
`IPR2016-01367, Paper 8 (Board Institution Decision)
`
`Godo Kaisha IP Bridge 1 v. Broadcom Limited et al, 2:16-cv-
`00134, D.I. 105 (E.D. Tex. Nov. 9, 2016) (Claim Construction
`Order)
`
`ix
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`
`Exhibit 1015:
`
`
`Exhibit 1016:
`
`Summary of District Court Claim Construction Ruling
`Related to the RE41,980 Patent
`
`Excerpt of Stanley Wolf, Ph.D., “Silicon Processing for the
`VLSI Era,” Lattice Press (Vol. 2 1990) (“Wolf”).
`
`
`
`x
`
`

`

`
`
`I.
`
`PRELIMINARY STATEMENT
`
`U. S. PATENT NO RE41,980
`Petition for Inter Partes Review
`
`U.S. Reissue Patent No. 41,980 to Yabu et al. (Ex. 1001) is owned by Godo
`
`Kaisha IP Bridge 1 (“Patent Owner) and is directed to preventing moisture from
`
`being absorbed by insulating films formed in areas between metal wires in a
`
`semiconductor device. All of the limitations of the challenged claims were known
`
`and constitute prior art.
`
`Before the ’980 patent application was filed, the following was well-known:
`
`(1) Depositing an insulating material with a “small dielectric constant”
`
`(e.g., silicon dioxide) in areas among metal wires could suppress the
`
`parasitic capacitance between those wires. Ex. 1001, 1:50-51, 2:30-
`
`36.
`
`(2) Covering a device with a moisture-blocking insulating material (e.g.,
`
`silicon nitride) would improve the device’s resistance to moisture-
`
`absorption. Ex. 1001, 1:51-52, 2:16-25, 2:30-36; El-Kareh, pp. 68-70.
`
`(3) Using a metal film to fill a bonding pad opening in the moisture-
`
`blocking layer could further improve resistance to moisture-
`
`absorption. Cheung, Fig. 2D.
`
`
`
`1
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`Accordingly, it is unsurprising that prior art semiconductor devices made use
`
`of such insulating materials and bonding pads to manufacture semiconductor
`
`devices.
`
`Just like the prior art, the challenged independent claims recite the same
`
`surface protecting film including a first dielectric film with a small dielectric
`
`constant (e.g., silicon oxide) for filling areas among metal wires, and a second
`
`dielectric film (e.g., silicon nitride) with a “higher moisture absorption preventing
`
`function” for covering the metal wire layer and first dielectric film. The ’980
`
`patent claims also recite the obvious use of a moisture-blocking film and a bonding
`
`pad to cover the low-dielectric constant film.
`
`This petition, supported by the expert declaration of Sanjay Banerjee, Ph.D.,
`
`(Ex. 1003), establishes that each of the challenged claims 18, 19, 30-36, and 47-51
`
`is unpatentable over the prior art. Petitioner respectfully requests inter partes
`
`review under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.100 et seq. and
`
`cancellation of all challenged claims.
`
`II.
`
`The ’980 Patent
`
`A.
`
` Overview of the ’980 Patent
`
`The ’980 patent discloses that it relates to the manufacturing of
`
`semiconductor devices (Ex. 1001, 1:23-26) and confirms in the BACKGROUND
`
`
`
`2
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`OF THE INVENTION that semiconductor devices were well-known in the prior
`
`art. Ex. 1001, 1:32-34 (discussing “a conventional semiconductor device”); 1:35-
`
`37 (“FIG. 18 is a … conventional semiconductor device”). Figure 18 of the ’980
`
`patent illustrates various known layers of a conventional semiconductor device.
`
`Ex. 1001, 1:35-36 (Figure 18 illustrates “the structure in the vicinity of the
`
`uppermost wires of the conventional semiconductor device.”); Fig. 18 (labeled
`
`“PRIOR ART”).
`
`Ex. 1001, Figure 18 (annotated)
`
`
`
`The ’980 patent discloses that Figure 18 omits numerous lower layers that
`
`comprise prior art semiconductor devices, including “a semiconductor substrate
`
`and elements such as a transistor … interlayer insulating films and metal wires in
`
`several layers.” Ex. 1001, 1:37-41. A person of ordinary skill in the art
`3
`
`
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`(“POSITA”) would understand that interlayer insulating film 11 is formed between
`
`the transistor components and wires 12 to prevent wires 12 from shorting with the
`
`transistor components, which would otherwise render the semiconductor device
`
`non-functional. Ex. 1001, 1:40-43; Ex. 1003, ¶ 35. Wires 12 could be formed by
`
`stacking layers of metal, including titanium-based films. Ex. 1001, 1:45-47; 7:67-
`
`8:3 (“stacking and then patterning a Ti type barrier metal … an Al type alloy film
`
`… and a Ti type anti-reflective film.”).
`
`The ’980 patent discloses that a conventional semiconductor included a
`
`multilayer surface protecting film 21 comprised of “an underlaying insulating film
`
`19 of a thin silicon film and a passivation film 14 of a silicon nitride film.” Ex.
`
`1001, 1:49-52. Silicon nitride was known to have “a large dielectric constant” (Ex.
`
`1001, 2:16-17), whereas silicon oxide was known to have a low dielectric constant
`
`(Ex. 1001, 2:32-33). A POSITA would have understood that the term “passivation
`
`layer” describes a moisture-blocking insulating material such as silicon nitride.
`
`Ex. 1001, Abstract (“passivation film of a silicon nitride film with high moisture
`
`absorption resistance”); 1:51-52 (“passivation film 14 of a silicon nitride film”);
`
`2:4-5 (“silicon nitride film for forming the passivation film 14”); Ex. 1003, ¶ 39.
`
`Conventional prior art semiconductor devices also included an opening 21a in the
`
`
`
`4
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`surface protecting film 21 to expose a bonding pad (Ex. 1001, 1:54-57; Fig. 18)
`
`formed of the same metal film as the metal wires 12 (Ex. 1001, 1:52-53).
`
`The ’980 patent confirms that certain material properties were also well-
`
`known in the prior art:
`
`• depositing an insulator material with a “small dielectric constant”
`
`(e.g., silicon oxide) in areas among metal wires would reduce the
`
`parasitic capacitance between the wires (Ex. 1001, 1:50-51, 2:30-36);
`
`• covering a device with an insulator material having a densely packed
`
`molecular structure (e.g., silicon nitride) would improve the device’s
`
`resistance to moisture absorption (Ex. 1001, 1:51-52, 2:16-25, 2:30-
`
`36);
`
`• using silicon nitride between wires 12 would increase parasitic
`
`capacitance (Ex. 1001, 2:19-25); and
`
`• using silicon oxide alone would not provide resistance to moisture
`
`absorption (Ex. 1001, 2:26-27).
`
`Indeed, prior art surface protecting film 21 illustrated in Fig. 18 was comprised of
`
`silicon oxide between wires 12 and silicon nitride above the wire layer, resulting in
`
`reduced parasitic capacitance between the wires, and increased moisture blocking.
`
`Ex. 1001, 1:49-52.
`
`
`
`5
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`Figure 21 of the ’980 patent illustrates a problem with prior art
`
`semiconductor devices. Figure 21 shows that the low-dielectric silicon oxide film
`
`used for underlayer insulating film 19 is exposed within the bonding pad opening
`
`21a, which allows a path for moisture absorption. Ex. 1001, Fig. 21 (arrows
`
`identifying path for moisture through exposed portion of underlaying insulating
`
`film 19).
`
`Ex. 1001, Figure 21 (annotated)
`
`
`
`The only limitation in independent claims 18 and 35 that purports to solve
`
`this problem recites “completely cover[ing]” the dielectric film that has a small
`
`
`
`6
`
`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`dielectric constant (i.e., the underlaying insulating film 11) with a bonding pad
`
`“formed in/cover[ing]” the bonding pad opening. The claimed solution is
`
`identified in Figures 1, 5, and 16, which show different ways of closing the small
`
`exposed area of underlying insulating film in the bonding pad opening.
`
`Figure 1 illustrates a bonding pad 15 filling the opening 20a and partially
`
`overlapping the top surface of passivation film 14.
`
`Ex. 1001, Figure 1
`
`
`
`Figure 5 illustrates a passivation film 14 covering the top surface of
`
`underlying insulating film 13 and a bonding pad 15 covering the side walls of
`
`opening 20a.
`
`
`
`7
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`Ex. 1001 (’980 Patent), Figure 5
`
`
`
`Figure 16 illustrates a passivation film 14 completely covering the
`
`underlying insulating layer by partially overlapping the top surface of bonding pad
`
`15.
`
`Ex. 1001, Figure 16
`
`
`
`As discussed in the Technological Background (Section III., infra), Cheung
`
`discloses the purported bonding pad and passivation layer solutions identified in
`
`Figures 1, 5 and 16.
`
`
`
`8
`
`

`

`B.
`
` Challenged Claims1
`
`The two challenged independent claims of the ’980 patent recite:
`
`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`18. A semiconductor device comprising:
`
`
`
`[18.1] a semiconductor substrate bearing semiconductor elements;
`
`[18.2] an interlayer insulating film formed on said semiconductor
`
`substrate;
`
`[18.3] a metal wire layer including plural metal wires formed on said
`
`interlayer insulating film;
`
`[18.4a] a surface protecting film including a first dielectric film with a
`
`small dielectric constant for filling at least a part of areas among
`
`said metal wires in said metal wire layer and
`
`[18.4b] a second dielectric film with a higher moisture absorption
`
`preventing function than said first dielectric film for covering
`
`said metal wire layer and said first dielectric film, said second
`
`dielectric film having a function of suppressing moisture
`
`absorption of said first dielectric film;
`
`
`
`
`
`1
`
` The challenged claims are claims 18, 19, 30-36, and 47-51 (“Challenged
`Claims”).
`
`9
`
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`

`

`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`[18.5] an opening for a bonding pad formed in said surface protecting
`
`film; and
`
`[18.6] a bonding pad formed in said opening for obtaining external
`
`electrical connection,
`
`[18.7] wherein said bonding pad in said opening and said second
`
`dielectric film of said surface protecting film completely cover
`
`said first dielectric film so as not to expose said first dielectric
`
`film.
`
`35. A semiconductor device comprising:
`
`[35.1] a semiconductor substrate bearing semiconductor elements;
`
`[35.2] an interlayer insulating film formed on said semiconductor
`
`substrate;
`
`[35.3] a metal wire layer including plural metal wires formed on said
`
`interlayer insulating film;
`
`[35.4a] a surface protecting film including a first dielectric film with a
`
`small dielectric constant for filling at least a part of areas among
`
`said metal wires in said metal wire layer and
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`[35.4b] a second dielectric film with a higher moisture absorption
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`preventing function than said first dielectric film for covering
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`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`said metal wire layer and said first dielectric film, said second
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`dielectric film having a function of suppressing moisture
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`absorption of said first dielectric film;
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`[35.5] an opening for a bonding pad formed in said surface protecting
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`film; and
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`[35.6] a bonding pad formed in said opening for obtaining external
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`electrical connection,
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`[35.7] wherein said bonding pad covers said opening and said second
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`dielectric film of said surface protecting film completely covers
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`said first dielectric film so as not to expose said first dielectric
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`film.
`
`III. Technological Background
`
`U.S. Patent No. 5,785,236 to Cheung et al. (“Cheung”) 2, U.S. Patent No.
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`5,739,579 to Chiang et al. (“Chiang”)3, U.S. Patent No. 3,617,284 to Shinoda et al.
`
`
`
`2 Cheung qualifies as prior art under 35 U.S.C. § 102(e). Cheung was filed on
`November 29, 1995, which predates the September 10, 1996 earliest possible
`priority date of the ’980 patent. Ex. 1004.
`3 Chiang qualifies as prior art under 35 U.S.C. § 102(e). Chiang was filed on Sep.
`10, 1996, and is a continuation of Application No. 430,759 (abandoned), filed
`Apr. 27, 1995, which is a division of Application No. 314,248 (abandoned),
`filed Sep. 28, 1994. Ex. 1005. Chiang constitutes prior art as of Sept. 24, 1994,
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`U. S. PATENT NO. RE41,980
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`(“Shinoda”)4 and El-Kareh, “Fundamentals of Semiconductor Processing
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`Technologies,” Kluwer Academic Publishers (1995) (“El-Kareh”) 5 confirm that
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`integrated circuits, dielectric insulating films and bonding pads were known and
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`implemented in prior art semiconductor devices before the earliest possible priority
`
`date of the ’980 patent.6
`
`A.
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`
`
`Integrated Circuits
`
`Cheung discloses an integrated circuit structure 10 comprised of “a
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`semiconductor substrate having integrated circuit devices” such as transistors
`
`formed by “doped regions in the semiconductor substrate separated by field
`
`oxide.” Cheung, 3:5-8; Fig. 2D. “[I]ntegrated circuit structure 10 may
`
`additionally include a multilayer interconnect structure … connecting the
`
`
`
`which predates the September 10, 1996 earliest possible priority date of the
`’980 patent.
`4 Shinoda qualifies as prior art under 35 U.S.C. § 102(b). Shinoda was issued on
`November 2, 1971, which predates the September 10, 1996 earliest possible
`priority date of the ’980 patent by more than one year. Ex. 1006.
`5 El-Kareh qualifies as prior art under 35 U.S.C. § 102(b). El-Kareh has a
`copyright date of 1995, and bears a Library of Congress stamp of December 21,
`1994. Ex. 1007. El-Kareh was publicly available at least as of December 21,
`1994, which predates the September 10, 1996 earliest possible priority date of
`the ’980 patent by more than one year.
`6 The earliest possible priority date attributable to the Challenged Claims is the
`September 10, 1996 foreign priority date of Japanese Patent Application No.
`08-239403, only to the extent that such foreign patent application discloses
`every element of the Challenged Claims
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`U. S. PATENT NO. RE41,980
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`integrated circuit devices.” Cheung, 3:8-13. Figure 2D of Cheung illustrates metal
`
`interconnects 12 above the integrated circuit structure 10.
`
`Cheung, Fig. 2D (annotated)
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`
`
`A POSITA would understand from the disclosure of a “multilayer
`
`interconnect structure” (Cheung, 3:9-11) that each layer of interconnects must be
`
`separated by an insulating film to ensure interconnects do not short with other
`
`layers or transistor components. Ex. 1003, ¶ 48. If metal interconnects 12 make
`
`direct contact with transistor components and/or other interconnects in such areas,
`
`the semiconductor device would be rendered non-functional. Id.
`
`Cheung discloses that although Figure 2D illustrates only two interconnects
`
`12, “it will be readily apparent to those skilled in the art that in fact any number of
`
`such copper interconnects [can be] formed.” Cheung, 3:18-21; 4:32-35.
`
`Shinoda discloses an integrated circuit device comprised of a silicon
`
`substrate 11, transistors, diodes and resistors, a layer of silicon dioxide 12 and
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`metal interconnects formed of three layers of metal 71, 72 and 73. Shinoda, 4:63-
`
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`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`70; Fig. 7. An insulating film 74 fills the areas between the metal interconnects.
`
`Shinoda, 4:69-70. A POSITA would understand that silicon dioxide layer 12 is an
`
`interlayer insulating film that ensures interconnects formed of layers 71, 72 and 73
`
`do not short with the underlying silicon substrate, transistors and/or diodes in
`
`regions where such contact would render the integrated circuit 70 non-functional.
`
`Ex. 1003, ¶ 50. Figure 7 illustrates silicon dioxide 12 (i.e, interlayer insulating
`
`film, red) located between but not within other layers.
`
`Shinoda, Fig. 7 (annotated)
`
`
`
`Chiang discloses a “semiconductor device” with multiple layers formed on a
`
`semiconductor substrate. Chiang, 3:52-4:2. Chiang discloses transistor
`
`components formed on the semiconductor substrate, including, for example, an N+
`
`region 21 within monocrystalline silicon layer 20. Chiang, 7: 64-64; 7:31-36
`
`(“present invention can be used with any semiconductor technology including
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`U. S. PATENT NO. RE41,980
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`NMOS, FMOS, CMOS, BiCMOS, bipolar, multi-chip modules (MCM) and II-VI
`
`semiconductors”). Dielectric layers 22 and 23 are formed over the transistor
`
`components (e.g., N+ region 21) and the silicon substrate 21. Chiang, 5:42-44.
`
`Metal wire interconnects 60 and 61 are formed over dielectric layers 22 and 23.
`
`Chiang, 10:39-41. Chiang, 5:51-57. Similar to the ’980 patent, Chiang discloses
`
`“more than one level of interconnects” separated by dielectric insulating film (e.g.,
`
`“a second silicon nitride layer 90, a second silicon dioxide layer 91, and a third
`
`silicon nitride layer 92”). Chiang, 10:50-54. Additional metal wire interconnects
`
`96 and 97 are formed over dielectric layers 90, 91 and 92. Chiang, 10:67-11:3.
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`Via plugs 40-41 and 93-94 are formed between metal wire interconnect layers to
`
`allow for electrical connection between layers and with transistor components in
`
`substrate 20. Chiang, 5:40-47; Fig. 9. A POSITA would understand that via plugs
`
`93 and 94 are not metal wire interconnects and that the metal wire layer of Chiang
`
`is comprised of metal wire interconnects 96 and 97. Ex. 1003, ¶ 51.
`
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`15
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`U. S. PATENT NO. RE41,980
`Petition for Inter Partes Review
`
`Chiang, Fig. 9 (annotated)
`
`
`
`A POSITA would understand that the dielectric layers 22 and 23 between
`
`the silicon substrate and first-level interconnects 60 and 61 prevent the
`
`interconnects from shorting with the substrate and/or transistor components. Ex.
`
`1003, ¶ 52. Similarly, a POSITA would understand that dielectric layers 90, 91
`
`and 92 function as an insulator that prevents interconnects from shorting with
`
`interconnects on other layers. Id. Figure 9 illustrates that each interlayer
`
`insulating film is formed between