Inter Partes Review
`United States Patent No. RE41,980
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`Taiwan Semiconductor Manufacturing Company Limited
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`Patent Owner
`
`
`
`Inter Partes Review No. IPR2017-00931
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES
`PATENT NO. RE41,980
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`
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`
`
`

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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF CONTENTS
`
`I.
`
`PRELIMINARY STATEMENT ................................................................... 1
`
`A.
`
`Related IPR2016-01331 ........................................................................ 1
`
`B. Overview of the ’980 Patent .................................................................. 3
`
`II. TECHNOLOGICAL BACKGROUND....................................................... 4
`
`A.
`
`Integrated Circuits ................................................................................. 4
`
`B. Dielectric Materials ............................................................................... 7
`
`C.
`
`Bonding Pads .......................................................................................10
`
`III. THE ’980 PATENT ......................................................................................13
`
`A. Overview of the ’980 Patent ................................................................13
`
`B.
`
`Challenged Claims ..............................................................................17
`
`IV. STATEMENT OF PRECISE RELIEF REQUESTED ...........................19
`
`A.
`
`Claims for Which Review is Requested ..............................................19
`
`B.
`
`C.
`
`Statutory Grounds of Challenge ..........................................................20
`
`Level of Ordinary Skill .......................................................................20
`
`D.
`
`Claim Construction..............................................................................20
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`“interlayer insulating film” .......................................................21
`
`“a metal wire layer including plural metal wires” ....................22
`
`“at least a part of areas among said metal wires in said
`metal wire layer” .......................................................................22
`
`“wherein said bonding pad covers said opening” .....................22
`
`“said bonding pad” in/covers “said opening and said
`second dielectric film of said surface protecting film
`completely cover[s] said first dielectric film so as not to
`expose said first dielectric film” ...............................................23
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`Inter Partes Review
`United States Patent No. RE41,980
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`V. CLAIMS 18, 19, 30-36, AND 47-51 OF THE ’980 PATENT ARE
`UNPATENTABLE OVER THE PRIOR ART .........................................23
`
`A. Disclosures of the Prior Art .................................................................23
`
`1.
`
`2.
`
`Ting ...........................................................................................23
`
`Jeng ...........................................................................................25
`
`B.
`
`Ting anticipates claims 18, 19, 30-36, and 47-51 ...............................27
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`Ting anticipates claims 18 and 35 .............................................27
`
`Ting anticipates claims 19 and 36 .............................................48
`
`Ting anticipates claims 30 and 47 .............................................49
`
`Ting anticipates claims 31 and 48 .............................................50
`
`Ting anticipates claims 32 and 49 .............................................51
`
`Ting anticipates claims 33 and 50 .............................................51
`
`Ting anticipates claims 34 and 51 .............................................53
`
`C.
`
`The combined teachings of Ting and Jeng render claims 18, 19,
`30-36, and 47-51 obvious ....................................................................54
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Claims 18 and 35 are obvious over the Ting-Jeng
`combination ...............................................................................55
`
`Claims 19 and 36 are obvious over the Ting-Jeng
`combination ...............................................................................62
`
`Claims 30 and 47 are obvious over the Ting-Jeng
`combination ...............................................................................66
`
`Claims 31 and 48 are obvious over the Ting-Jeng
`combination ...............................................................................66
`
`Claims 32-34 and 49-51 are obvious over the Ting-Jeng
`combination ...............................................................................67
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`Inter Partes Review
`United States Patent No. RE41,980
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`VI. THIS PETITION RAISES SUBSTANTIAL NEW ARGUMENTS
`THAT COULD NOT HAVE BEEN RAISED IN THE IPR2016-
`01331 PETITION .........................................................................................67
`
`VII. MANDATORY NOTICES .........................................................................71
`
`A.
`
`Real Party-in-Interest ..........................................................................71
`
`B.
`
`C.
`
`Related Matters ....................................................................................72
`
`Lead and Back-Up Counsel .................................................................72
`
`D.
`
`Service Information .............................................................................73
`
`VIII. CERTIFICATION UNDER 37 C.F.R. § 42.24(d) ....................................73
`
`IX. PAYMENT OF FEES .................................................................................73
`
`X.
`
`TIME FOR FILING PETITION ...............................................................73
`
`XI. GROUNDS FOR STANDING ....................................................................74
`
`XII. CONCLUSION ............................................................................................74
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`Inter Partes Review
`United States Patent No. RE41,980
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`
`
`Cases
`
`American Calcar, Inc. v. American Honda Motor Co.,
`651 F.3d 1318 (Fed. Cir. 2011) .......................................................................... 42
`
`In re Crish,
`393 F.3d 1253 (Fed. Cir. 2004) .................................................................... 40, 50
`
`In re Cronyn,
`890 F.2d 1158 (Fed. Cir. 1989) ............................................................................ 9
`
`Godo Kaisha IP Bridge 1 v. Broadcom Limited et al.,
`Case No. 2-16-cv-00134 (E.D. Tex. February 14, 2016) ............................. 67, 72
`
`Great West Casualty Co. v. Intellectual Ventures II LLC,
`IPR2016-00453, Paper No. 12 ............................................................................ 70
`
`In re Hall,
`781 F.2d 897 (Fed. Cir. 1986) .............................................................................. 9
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 54
`
`LG Electronics v. Core Wireless Licensing S.A.R.L.,
`IPR2016-00986, Paper No. 12 ...................................................................... 69, 70
`
`Ex parte Masham,
`2 U.S.P.Q.2d 1647 (Bd. Pat. App. & Inter. 1987) .............................................. 42
`
`Microsoft Corp. v. Bradium Technologies LLC,
`IPR2016-00449, Paper No. 9 .............................................................................. 70
`
`NRT Technology Corp. v. Everi Payments Inc.,
`CBM2016-00080, Paper No. 12 ................................................................... 69, 70
`
`Omega Eng’g, Inc. v. Raytek Corp.,
`334 F.3d 1314 (Fed. Cir. 2003) .......................................................................... 69
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 20
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`Inter Partes Review
`United States Patent No. RE41,980
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`In re Schreiber,
`128 F.3d 1473 (Fed. Cir. 1997) .......................................................................... 41
`
`In re Spada,
`911 F.2d 705 (Fed. Cir. 1990) ...................................................................... 42, 50
`
`Upsher-Smith Labs., Inc. v. PamLab L.L.C.,
`412 F.3d 1319 (Fed. Cir. 2005) .......................................................................... 52
`
`Verdegaal Bros. v. Union Oil Co. of California,
`814 F.2d 628 (Fed. Cir. 1987) ............................................................................ 50
`
`ZTE Corp. v. Contentguard Holdings Inc.,
`IPR2013-00454, Paper No. 12 ............................................................................ 71
`
`Statutes
`
`35 U.S.C. § 102 ...................................................................................... 20, 25, 39, 42
`
`35 U.S.C. § 103 ........................................................................................................ 20
`
`35 U.S.C. § 311 .................................................................................................. 19, 73
`
`35 U.S.C. §§ 311–319 ................................................................................................ 4
`
`35 U.S.C. § 314 ........................................................................................................ 69
`
`35 U.S.C. § 315 ........................................................................................................ 71
`
`35 U.S.C. § 325 .................................................................................................. 69, 70
`
`Regulations
`
`37 C.F.R. § 42.15 ..................................................................................................... 73
`
`37 C.F.R. § 42.24 ..................................................................................................... 73
`
`37 C.F.R. § 42.100 ............................................................................................... 4, 21
`
`37 C.F.R. § 42.101 ................................................................................................... 74
`
`37 C.F.R. § 42.102 ................................................................................................... 73
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`37 C.F.R. § 42.103 ................................................................................................... 73
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`Inter Partes Review
`United States Patent No. RE41,980
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`Other Authorities
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`M.P.E.P. § 2114(II) .................................................................................................. 42
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`M.P.E.P. § 2143 ....................................................................................................... 54
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`Inter Partes Review
`United States Patent No. RE41,980
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`LIST OF EXHIBITS
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`Exhibit 1001:
`
`U.S. Patent No. RE41,980 to Yabu et al.
`
`Exhibit 1002
`
`File history of U.S. Patent No. 6,232,656 to Yabu et al.
`
`Exhibit 1003:
`
`U.S. Patent No. 5,659,201 to Wollesen.
`
`Exhibit 1004:
`
`U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Exhibit 1005:
`
`Expert Declaration of Dr. Sanjay Banerjee.
`
`Exhibit 1006:
`
`U.S. Patent No. 5,169,680 to Ting.
`
`Exhibit 1007:
`
`U.S. Patent No. 5,527,737 to Jeng.
`
`Exhibit 1008:
`
`U.S. Patent No. 5,300,461 to Ting.
`
`Exhibit 1009:
`
`Excerpt of El-Kareh, “Fundamentals of Semiconductor
`Processing Technologies,” Kluwer Academic Publishers
`(1995).
`
`Exhibit 1010:
`
`U.S. Patent No. 5,394,013 to Oku et al.
`
`Exhibit 1011:
`
`Library of Congress Catalog Record of El-Kareh,
`“Fundamentals of Semiconductor Processing
`Technologies,” Kluwer Academic Publishers (1995).
`
`Exhibit 1012:
`
`Declaration of Stephen E. Kabakoff.
`
`Exhibit 1013:
`
`
`
`Godo Kaisha IP Bridge 1 v. Broadcom Ltd., Case No.
`2:16-cv-00134-JRG-RSP, Claim Construction
`Memorandum and Order, Dkt. No. 105 (E.D. Tex. Feb.
`14, 2016).
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`Inter Partes Review
`United States Patent No. RE41,980
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`PRELIMINARY STATEMENT
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`A. Related IPR2016-01331
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`
`
`I.
`
`This petition is related to Petitioner’s request for inter partes review in
`
`IPR2016-01331 involving U.S. Reissue Patent No. 41,980 to Yabu et al. (Ex. 1001,
`
`“the ’980 patent”). In its previous petition, Petitioner urged the Board to adopt the
`
`plain meaning of the claim terms as they would have been understood by a person
`
`of ordinary skill in the art at the time of the ’980 patent. IPR2016-01331, Paper No.
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`2, at 19-20. The Board denied the previous petition because it concluded the
`
`insulating layer identified by Petitioner was not the claimed “interlayer insulating
`
`film” as defined by the Board. IPR2016-01331, Paper No. 9 at 8.
`
`The Board rejected Petitioner’s assertion that the claimed “interlayer
`
`insulating film” corresponds to a dielectric layer 25, with upper and lower films 26
`
`and 27, in Figure 5 of U.S. Patent 5,169,680 (“Ting”) (Ex. 1006, FIG. 5, 7:6-14),
`
`because Ting’s layer 25 is located, at least partially, within a conducting layer 21.
`
`IPR2016-01331, Paper No. 9 at 11. Ting’s upper dielectric film 26, however, is an
`
`insulating film that does not extend in any part into any other layers and satisfies
`
`the Board’s construction. The Board appeared to recognize this when it stated,
`
`“Petitioner does not assert that upper region 26 alone constitutes an ‘interlayer
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`insulating film’ within the meaning of claims 18 and 35.” Id. at 11, n. 5. This
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`petition modifies the mapping of the “interlayer insulating film” to correspond to
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`Inter Partes Review
`United States Patent No. RE41,980
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`the upper dielectric film 26 in Ting’s Figure 5 to satisfy the Board’s claim
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`construction, which was unexpected.
`
`In IPR2016-01331, Petitioner filed a Request for Rehearing to explain why
`
`the negative limitation in the Board’s construction (“but not within other layers”)
`
`was inconsistent with both the intrinsic and extrinsic evidence, and Petitioner stands
`
`by the position set forth in its request. IPR2016-01331, Paper No. 10. In this
`
`petition, however, to the extent that the Board does not accept the arguments in its
`
`Request for Rehearing, Petitioner has applied the Board’s construction of
`
`“interlayer insulating film” to demonstrate that the challenged claims are invalid in
`
`view of Ting’s Figure 5 with or without the Board’s negative limitation.
`
`This petition raises arguments that are not substantially the same as the
`
`arguments raised in the previous petition because it relies on Ting’s film 26 instead
`
`of dielectric layer 25 for the claimed “interlayer insulating film.” This change is
`
`substantial because although the Board found the dual-layer dielectric layer 25 is
`
`not an “interlayer insulating film” under its construction, the Board suggested but
`
`did not consider whether Ting’s upper film 26 alone would satisfy the construction,
`
`which was the only stated basis for denying the petition in IPR2016-01331.
`
`Petitioner submits the Board should grant this petition so Patent Owner
`
`cannot continue asserting invalid claims against Petitioner’s products and those of
`
`other operating companies in the industry.
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`Inter Partes Review
`United States Patent No. RE41,980
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`B. Overview of the ’980 Patent
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`
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`The ’980 patent is directed to structures for preventing moisture from being
`
`absorbed by insulating films in areas between metal wires in a semiconductor
`
`device. These structures were not novel or nonobvious: All of the limitations of the
`
`challenged claims were known and constitute prior art.
`
`A person of ordinary skill in the art (“POSITA”) as of the effective filing date
`
`of the ’980 patent knew the following properties of insulating materials used in
`
`semiconductor devices:
`
`(1) Depositing an insulating material with a “small dielectric constant” in
`
`areas among metal wires could suppress the parasitic capacitance between
`
`those wires. Ex. 1005, ¶ 45; see also Ex. 1001, 1:50-51, 2:30-36.
`
`(2) Covering a device with a moisture-blocking insulating material could
`
`improve the device’s moisture-absorption resistance, but those films
`
`typically had a “large dielectric constant” that would increase the parasitic
`
`capacitance between wires. Ex. 1005, ¶ 45; Ex. 1001, 1:51-52, 2:16-25,
`
`2:30-36.
`
`In view of these well-known properties, a POSITA as of the effective date of
`
`the ’980 patent already knew to place these different insulating materials together.
`
`Ex. 1005, ¶ 46; see also Ex. 1001, 1:35-2:29, FIGS. 18-21. Prior art films included
`
`a first insulating material to control parasitic capacitance covered by a different
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`Inter Partes Review
`United States Patent No. RE41,980
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`insulating material to serve as a moisture-blocking passivation film. Ex. 1005, ¶ 46;
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`Ex. 1001, 1:35-2:29, FIGS. 18-21.
`
`The challenged claims recite the same surface-protecting film including a
`
`first dielectric film with a small dielectric constant (such as silicon oxide) for filling
`
`areas among metal wires, and a second dielectric film (such as silicon nitride) with
`
`a “higher moisture absorption preventing function” for covering the metal wire
`
`layer and first dielectric film. The ’980 patent claims only add that the moisture-
`
`blocking film and a bonding pad cover the low-dielectric-constant film when the
`
`bonding pad is formed in an opening in the moisture-blocking film. This was also
`
`well known in the art before the effective filing date of the ’980 patent.
`
`This petition, supported by the expert declaration of Sanjay Banerjee, Ph.D.,
`
`(Ex. 1005), establishes that each of the challenged claims 18, 19, 30-36, and 47-51
`
`is unpatentable over the prior art. Petitioner respectfully requests inter partes
`
`review under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.100 et seq. and cancellation
`
`of all challenged claims.
`
`II. TECHNOLOGICAL BACKGROUND
`
`A.
`
`Integrated Circuits
`
`An integrated circuit (“IC,” “chip,” or “microchip”) is an electronic circuit
`
`formed on a piece of semiconductor material and includes electronic components,
`
`such as transistors, usually metal-oxide-semiconductor field-effect transistor
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`Inter Partes Review
`United States Patent No. RE41,980
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`(MOSFETs). Ex. 1005, ¶ 31. At the early time of integrated circuit technology, only
`
`a few (usually less than about 100) transistors were included in an integrated circuit,
`
`and such a level of integration is referred to as small-scale integration (SSI). Ex.
`
`1005, ¶ 32. With the development of improved semiconductor processing
`
`technology, more and more transistors were integrated to form a single integrated
`
`circuit. Id. Depending on the number of transistors in the integrated circuit, later
`
`generations of integration technology are usually referred to as medium-scale
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`integration (MSI, including about 100 to about 1000 transistors), large-scale
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`integration (LSI, including about 1000 to about 10 thousand transistors), very-large-
`
`scale integration (VLSI, including about 10 thousand to about 1 million transistors),
`
`and ultra-large-scale integration (ULSI, including about 1 million or more
`
`transistors).1 Id.
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`To form an integrated circuit, transistors need to be electrically coupled to
`
`each other by interconnections, which are electrical conductors that provide
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`pathways for electrical signals. Id., ¶ 33. Interconnections can be made from a
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`variety of conducting materials, such as metals, metal alloys, metal compounds,
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`highly doped polycrystalline silicon (polysilicon), or combinations of these (e.g.,
`
`metal-silicon compounds, called “silicides”). Id.
`
`
`1 There is no universal consensus about the number of transistors in each
`
`generation. These ranges are only for illustrative purposes. Ex. 1005 at 12, n. 2.
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`Inter Partes Review
`United States Patent No. RE41,980
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`As integration scales increased and transistor sizes decreased, integrated
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`circuit designers used multilevel interconnection structures for increasing the circuit
`
`densities and operation speeds of the integrated circuits. Id., ¶ 34; see also, e.g., Ex.
`
`1001, 1:28-33; Ex. 1003, 1:42-45; Ex. 1006, 1:21-25; Ex. 1007, 1:44-46. Such
`
`multilevel interconnection structures have existed for over 50 years. Ex. 1005, ¶ 34.
`
`For example, U.S. Patent No. 3,617,824 to Shinoda et al. (“Shinoda,” Ex. 1004),
`
`which has a priority date of 1965, discloses multilevel interconnections formed
`
`between transistors in an integrated circuit, including lower level interconnects
`
`(shown in blue in the annotated figures below) and upper level interconnects
`
`(shown in green below) separated by insulating material (shown in red below).
`
`Ex. 1004, FIGS. 6 and 7 (reproduced below); see also Ex. 1003, FIG. 1; Ex. 1006,
`
`FIG. 5; Ex. 1005, ¶ 34.
`
`Annotated FIG. 6 of Shinoda (Ex. 1004)
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`Inter Partes Review
`United States Patent No. RE41,980
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`Annotated FIG. 7 of Shinoda
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`B. Dielectric Materials
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`As mentioned above, the semiconductor industry has steadily moved towards
`
`packing more transistors onto one chip, by reducing the size of individual
`
`transistors and/or reducing the distance between transistors. Ex. 1005, ¶¶ 32-34, 36;
`
`see also, e.g., Ex. 1001, 1:29-34. As a result, device densities have increased and
`
`interconnects, such as metal wires, within the integrated circuits have become
`
`packed closer together. Ex. 1005, ¶ 32-34, 36; see also, e.g., Ex. 1001, 1:29-34.
`
`Various design restrictions limit reducing distances between interconnects and
`
`shrinking individual transistor sizes. Ex. 1005, ¶ 35. One restriction is the parasitic
`
`capacitance between the interconnects. Id., ¶ 36. Parasitic capacitance, which can
`
`increase electrical interference, increases with reduced distance (or “pitch”)
`
`between interconnects, and is undesirable because it increases signal delay,
`
`crosstalk, and power dissipation. Id., ¶ 36; see also, e.g., Ex. 1007, 1:50-57 (“As
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`Inter Partes Review
`United States Patent No. RE41,980
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`device geometries shrink and functional density increases, it becomes imperative to
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`reduce the capacitance between the lines . . . Reducing the capacitance within these
`
`multi-level metallization systems will reduce the RC constant, crosstalk voltage,
`
`and power dissipation between the lines.”).
`
`Parasitic capacitance between two interconnects is proportional to the
`
`dielectric constant of the material between the interconnects. Ex. 1005, ¶ 37. One
`
`way to reduce parasitic capacitance is to use a dielectric material with a small
`
`dielectric constant (also referred to as “low” dielectric constant or low-k) between
`
`the interconnects. Id.; see also, e.g., Ex. 1007, 1:66-67, 4:30-47, 2:5-6. Dielectric
`
`constants of materials, as would have been understood by a POSITA at the time the
`
`’980 patent’s application was filed, are based on a relative scale, where 1.0
`
`represents the dielectric constant of vacuum. Ex. 1005, ¶ 37; Ex. 1007, 1:64-66.
`
`Silicon dioxide (often referred to as “silicon oxide”) is a widely used
`
`dielectric material for separating different interconnect layers in a semiconductor
`
`device and for isolating interconnects within the same layer. Ex. 1005, ¶ 38. The
`
`dielectric constant of silicon oxide may depend on its density. Id. Dense silicon
`
`oxide grown by thermal oxidation or chemical vapor deposition has a dielectric
`
`constant of about 3.9. Id.; see also Ex. 1007, 1:62-64; Badih El-Kareh,
`
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`Inter Partes Review
`United States Patent No. RE41,980
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`“Fundamentals of Semiconductor Processing Technology,” at 9, Table 2.1, Kluwer
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`Academic Publishers (1995) (“El-Kareh,” Ex. 1009).2
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`The decreasing distances between interconnects raises the need for dielectric
`
`materials with even smaller dielectric constants (Ex. 1005, ¶ 39), which can be
`
`created by doping silicon oxide with, for example, fluorine, carbon, or hydrogen, or
`
`by making silicon oxide porous. Id.; see also Ex. 1001, 2:32-33 (admitted prior art
`
`includes “silicon oxide film doped with fluorine . . . having a small dielectric
`
`constant” to suppress parasitic capacitance between metal wires); Ex. 1007, 2:1-4.
`
`Some organic materials with small dielectric constants, such as polyimide,
`
`polynorbornenes, and organic spin-on glass (SOG) material, can also be used. Ex.
`
`1005, ¶ 39; see also Ex. 1001, 2:33.
`
`
`2 Exhibit 1009 was catalogued and available to the public in the Library of
`
`Congress in 1994. Ex. 1009 at 2 (showing Library of Congress stamp dated
`
`December 21, 1994); Ex. 1011 (catalogue entry); Ex. 1012 at ¶ 3 (linking Ex. 1009
`
`to Ex. 1011). Papers catalogued and available to the public in libraries, including
`
`the Library of Congress, are sufficiently “publicly accessible” to serve as prior art.
`
`See, e.g., In re Hall, 781 F.2d 897 (Fed. Cir. 1986); In re Cronyn, 890 F.2d 1158,
`
`1161 (Fed. Cir. 1989). Accordingly, Exhibit 1009 qualified as prior art at least one
`
`year before the earliest priority date of the ’980 patent.
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`Inter Partes Review
`United States Patent No. RE41,980
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`While low-dielectric-constant materials can reduce parasitic capacitance, they
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`usually absorb moisture more easily than denser materials (which often also have
`
`higher dielectric constants), and such moisture absorption can reduce the reliability
`
`of the semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1001, 2:30-34. To prevent
`
`moisture from entering the semiconductor device through the low-dielectric-
`
`constant material, circuit designers form a passivation layer (sometimes also called
`
`a “protective” dielectric layer) over the uppermost layer of low-dielectric-constant
`
`material in a semiconductor device. Ex. 1005, ¶ 40; see also Ex. 1003, 2:5-10.
`
`Common materials for a passivation layer are silicon nitride or silicon oxynitride,
`
`which have higher moisture-blocking functions and higher dielectric constants than
`
`silicon oxide. Ex. 1005, ¶ 40; Ex. 1003, 2:5-7.
`
`C. Bonding Pads
`
`Bonding is often used to electrically couple an integrated circuit with its
`
`packaging or other electronic devices, where a conducting bonding material, e.g., a
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`gold or aluminum wire, solder bump, copper pillar, or other external connection, is
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`bonded to a bonding pad of the integrated circuit. Ex. 1005, ¶ 41. A bonding pad
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`usually includes a metal area having an appropriate size to facilitate bonding, and
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`the pad is electrically coupled to other conducting parts, such as the interconnects,
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`of the integrated circuit. Id. For example, FIG. 11 (reproduced and annotated
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`below) of U.S. Patent No. 5,394,013 to Oku et al. (Ex. 1010) illustrates a bonding
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`United States Patent No. RE41,980
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`pad 11 (in pink) connected to a second aluminum film 45 (in red), which in turn
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`connects to a first aluminum film 43 (in brown). Ex. 1005, ¶ 41.
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`Annotated FIG. 11 of Oku (Ex. 1010)
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`Usually, there are two types of bonding pads. The first type is formed directly
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`using one of the interconnect layers, usually the uppermost interconnect layer, of
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`the integrated circuit, i.e., a portion of the interconnect layer functions as the
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`bonding pad. Ex. 1005, ¶ 42; Ex. 1003, FIG. 1 (showing an interconnect layer 10
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`with two representative interconnect lines, where one of the interconnect lines has a
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`top surface that also functions as a bonding pad 14).
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`11
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`Bonding pad
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`First aluminum film
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`Second aluminum film
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`United States Patent No. RE41,980
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`Annotated FIG. 1 of Wollesen (Ex. 1003)
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`Another type of bonding pad includes conductive pads that are separately
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`formed on one of the interconnect layers, usually the uppermost interconnect layer,
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`of the integrated circuit. Ex. 1005, ¶ 43; Ex. 1006, FIG. 5 (showing a bonding pad
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`46 that is formed in an opening on interconnect layer 35 and 36).
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`Annotated Fig. 5 of Ting (Ex. 1006)
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`12
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`Interconnect layer
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`Bonding pad
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`Interconnect layer
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`Bonding pad
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`Interconnect layer
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`United States Patent No. RE41,980
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`Both types of bonding pads need an opening in the uppermost dielectric
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`layers (e.g., opening 45 in FIG. 5 of Ting above), or through the passivation layer if
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`it directly overlies an area of the interconnect layer used for forming the bonding
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`pad (e.g., opening in passivation film 13 in FIG. 1 of Wollesen above), to either
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`expose a portion of the interconnect layer that will function as a bonding pad, or to
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`fill the opening with a metal that will function as the bonding pad. Ex. 1005, ¶ 44.
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`III. THE ’980 PATENT
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`A. Overview of the ’980 Patent
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`The ’980 patent discloses “a semiconductor device which has a small
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`parasitic capacitance in an area with a small pitch between metal wires and is free
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`from a coverage defect as well as the moisture absorption through the opening for
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`the bonding pad.” Ex. 1001, Abstract. The patent, though, acknowledges a prior-art
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`technique where an “underlying insulating film 19 of a thin silicon film,” which
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`refers to a silicon-based dielectric film (Ex. 1005, ¶ 47) is deposited between
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`adjacent metal wires 12, and then covered by a “passivation film 14 of a silicon
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`nitride film.” Id., 1:35-2:29, FIGS. 18-21. The passivation film 14 has “a large
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`dielectric constant” (Ex. 1001, 2:15-17), implying the underlying insulating film 19
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`has a lower dielectric constant. Ex. 1005, ¶ 47.
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`The ’980 patent teaches that if the silicon-nitride passivation film 14 fills the
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`areas between metal wires with a small pitch (e.g., as shown in FIG. 20(b)), the
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`13
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`United States Patent No. RE41,980
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`moisture absorption resistance of the device improves, but at the cost of an
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`increased parasitic capacitance between the metal wires. Id., 2:19-25, FIG. 20(b);
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`Ex. 1005 ¶ 48.
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`The ’980 patent purports to solve this problem by using a conventional dual-
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`layered low-dielectric/high-dielectric film. With reference to FIGS. 18 and 21 (both
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`labeled “Prior Art”), the ’980 patent identifies a path through which moisture could
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`enter a conventional semiconductor device having the same passivation film 14 and
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`underlying insulating film 19 discussed above. In this device, a metal wiring layer
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`contains metal wires 12 and “a bonding pad 15 formed out of the same metal film
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`as metal wires 12” for providing external electrical connections. Id., 1:52-57. The
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`’980 patent suggests that an opening 21a for the bonding pad 15 through the films
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`19 and 14 exposes a path for moisture absorption through the low-dielectric-
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`constant insulating film 19 along a side wall of the opening 21a. FIG. 21 (below)
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`shows this path. Ex. 1005, ¶ 49.
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`United States Patent No. RE41,980
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`The ’980 patent simply seeks to close the opening through which moisture
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`could enter the low-dielectric insulating film 19 along the side wall of the opening
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`21a. The patent discloses various embodiments where the top-most passivation film
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`14 and the bonding pad 15 cover any potential ingress paths that could allow
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`moisture to enter the insulating layer 19. Ex. 1005, ¶ 50. For example, FIG. 1
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`(below) shows an embodiment where the bonding pad 15 fills the opening 20a and
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`partially overlaps the top surface of the passivation film 14 to ensure there is no
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`exposed surface of the underlying insulating layer 13 on the side wall of the
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`opening 20a. Ex. 1005, ¶ 51.
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`FIG. 1 of ’980 Patent
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`FIG. 5 shows another embodiment where the passivation film 14 covers the
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`top surface of the underlying insulating film 13 and the bonding pad 15 covers the
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`15
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`side walls of opening 20a, preventing the insulating film 13 from being exposed on
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`the side wall of opening 20a. Ex. 1005, ¶ 52.
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`FIG. 5 of ’980 Patent
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`FIGS. 8 and 16 of the ’980 patent show other embodiments where the
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`passivation film 14 partially overlaps the top surface of the bonding pad 15, with
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`the same result of ensuring there is no exposed surface of the underlying insulating
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`layer 13 on the side wall of opening 20a. Ex. 1005, ¶ 53.
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`FIG. 8 of ’980 Patent
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`16
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`FIG. 16 of ’980 Patent
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`B. Challenged Claims3
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`The two challenged independent claims of the ’980 patent recite:
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`18. A semiconductor device comprising:
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`[18.1] a semiconductor substrate bearing semiconductor elemen