Trials@uspto.gov
`571-272-7822
`
`
`
`Paper 22
`Entered: April 12, 2019
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`SAINT REGIS MOHAWK TRIBE,
`Patent Owner.
`____________
`
`Cases IPR2018-01605, IPR2018-01606, and IPR2018-01607
`Patent 7,620,800 B2
`____________
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`571-272-7822
`
`
`
`Paper 22
`Entered: April 12, 2019
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`SAINT REGIS MOHAWK TRIBE,
`Patent Owner.
`____________
`
`Cases IPR2018-01605, IPR2018-01606, and IPR2018-01607
`Patent 7,620,800 B2
`____________
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`
`ARBES, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`
`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`
`Paper 1
`(“Pet.”)
`
`I. INTRODUCTION
`Petitioner Microsoft Corporation filed three Petitions requesting inter
`partes review of claims 1–5, 7–9, 15, 17, 18, and 20–24 of U.S. Patent
`No. 7,620,800 B2 (Ex. 1005, “the ’800 patent”) pursuant to 35 U.S.C.
`§ 311(a). Patent Owner Saint Regis Mohawk Tribe filed a Preliminary
`Response pursuant to 35 U.S.C. § 313 in each proceeding. Pursuant to our
`authorization, Petitioner also filed a Reply and Patent Owner filed a
`Sur-Reply in each proceeding, as listed in the following chart.1
`Case Number
`Challenged
`Petition Preliminary
`Reply
`Claims
`Response
`IPR2018-01605 1, 8, 9, and
`Paper 15
`20
`(“Prelim.
`Resp.”)
`
`Paper 1 Paper 16
`(“-1606
`(“-1606
`Pet.”)
`Prelim.
`Resp.”)
`Paper 15
`(“-1607
`Prelim.
`Resp.”)
`
`Paper 19
`(“Reply”)
`
`Sur-
`Reply
`Paper 20
`(“Sur-
`Reply”)
`Paper 20 Paper 21
`
`Paper 19 Paper 20
`
`IPR2018-01606 1, 7, 15,
`17, and 24
`
`IPR2018-01607 1–5, 18,
`and 21–23
`
`Paper 1
`(“-1607
`Pet.”)
`
`Pursuant to 35 U.S.C. § 314(a), the Director may not authorize an
`inter partes review unless the information in the petition and preliminary
`response “shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” For the reasons that follow, we institute an inter partes review as
`to claims 1–5, 7–9, 15, 17, 18, and 20–24 of the ’800 patent on all grounds
`
`
`1 Unless otherwise noted with the prefix “-1606” or “-1607,” references
`herein are to the exhibits filed in Case IPR2018-01605.
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`
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`2
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`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
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`of unpatentability asserted in the Petitions. Claims 2–5, 7–9, 15, 17, 18, and
`20–24 depend from claim 1, and, therefore, analysis of each dependent claim
`requires the same analysis of independent claim 1. To administer the
`proceedings more efficiently, we also exercise our authority under 35 U.S.C.
`§ 315(d) to consolidate the three proceedings and conduct the proceedings as
`one trial. See also 37 C.F.R. § 42.122(a) (“Where another matter involving
`the patent is before the Office, the Board may during the pendency of the
`inter partes review enter any appropriate order regarding the additional
`matter including providing for the stay, transfer, consolidation, or
`termination of any such matter.”).
`
`
`II. BACKGROUND
`A. The ’800 Patent
`The ’800 patent2 discloses “multi-adaptive processing systems and
`techniques for enhancing parallelism and performance of computational
`functions.” Ex. 1005, col. 1, ll. 40–43. Parallel processing “allows multiple
`processors to work simultaneously on the same problem to achieve a
`solution” in less time than it would take a single processor. Id. at col. 1,
`ll. 44–49. “[A]s more and more performance is required, so is more
`parallelism, resulting in ever larger systems” and associated difficulties,
`including “facility requirements, power, heat generation and reliability.”
`Id. at col. 1, ll. 53–61. The ’800 patent discloses that
`if a processor technology could be employed that offers orders
`of magnitude more parallelism per processor, these systems
`
`2 The ’800 patent is a continuation of U.S. Patent No. 7,225,324 B2
`(Ex. 1001, “the ’324 patent”), challenged by Petitioner in Cases
`IPR2018-01601, IPR2018-01602, and IPR2018-01603.
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`3
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`could be reduced in size by a comparable factor. Such a
`processor or processing element is possible through the use of a
`reconfigurable processor. Reconfigurable processors instantiate
`only the functional units needed to solve a particular application,
`and as a result, have available space to instantiate as many
`functional units as may be required to solve the problem up to
`the total capacity of the integrated circuit chips they employ.
`Id. at col. 1, l. 65–col. 2, l. 7. The ’800 patent describes a known issue
`where each processor in a multi-processor system is allocated a portion of a
`problem called a “cell” and “to solve the total problem, results of one
`processor are often required by many adjacent cells because their cells
`interact at the boundary.” Id. at col. 2, ll. 26–32. Passing intermediate
`results around the system to complete the problem requires using “numerous
`other chips and busses that run at much slower speeds than the
`microprocessor,” diminishing performance. Id. at col. 2, ll. 32–38, col. 5,
`ll. 16–28, Fig. 1 (depicting a conventional multi-processor arrangement).
`In an adaptive processor-based system, however, “any boundary data that is
`shared between . . . functional units need never leave a single integrated
`circuit chip,” reducing “data moving around the system” and improving
`performance. Id. at col. 2, ll. 39–49.
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`Figure 2 of the ’800 patent is reproduced below.
`
`
`Figure 2 is “a functional block diagram of an adaptive processor 200
`communications path for implementing the technique of the present
`invention.” Id. at col. 5, ll. 29–32. Adaptive processor 200 includes
`adaptive processor chip 202, which is coupled to memory element 206,
`interconnect 208, and additional adaptive processor chips 210. Id. at col. 5,
`ll. 32–37. Adaptive processor chip 202 includes thousands of functional
`units (“FU”) 204 interconnected by “reconfigurable routing resources”
`inside adaptive processor chip 202, allowing functional units 204 to
`“exchange data at much higher data rates and lower latencies than a standard
`microprocessor.” Id. at col. 5, ll. 39–45.
`
`
`
`
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`5
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`Figures 4A and 4B of the ’800 patent are reproduced below.
`
`
`
`Figure 4A depicts conventional sequential processing operation 400 where
`“nested Loops A (first loop 402) and B (second loop 404) are alternately
`active on different phases of the process.” Id. at col. 5, l. 65–col. 6, l. 2.
`Because first loop 402 must be completed before beginning second loop
`404, “all of the logic that has been instantiated is not being completely
`utilized.” Id. at col. 6, ll. 3–9. Figure 4B depicts “multi-dimensional
`process 410 in accordance with the technique of the present invention.” Id.
`at col. 6, ll. 11–14. “[M]ulti-dimensional process 410 is effectuated such
`that multiple dimensions of data are processed by both Loops A (first loop
`412) and B (second loop 414) such that the computing system logic is
`operative on every clock cycle.” Id. at col. 6, ll. 14–18. A “dimension” of
`data can be “multiple vectors of a problem, multiple plans of a problem,
`multiple time steps in a problem and so forth.” Id. at col. 6, ll. 25–28. The
`’800 patent discloses that available resources are utilized more effectively
`in the multi-dimensional process by “hav[ing] an application evaluate a
`
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`6
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`problem in a data flow sense. That is, it will ‘pass’ a subsequent dimension
`of a given problem through the first loop 412 of logic concurrently with the
`previous dimension of data being processed through the second loop.” Id. at
`col. 6, ll. 19–25.
`The ’800 patent states that the disclosed process can be utilized for a
`variety of applications. Id. at col. 9, ll. 10–20. For example, seismic
`imaging applications, which “process echo data to produce detailed analysis
`of subsurface features” for oil and gas exploration, would “particularly
`benefit from the tight parallelism that can be found in the use of adaptive or
`reconfigurable processors” because they “use data collected at numerous
`points and consisting of many repeated parameters” and “the results of the
`computation on one data point are used in the computation of the next.” Id.
`at col. 9, ll. 25–34; see id. at col. 6, l. 30–col. 7, l. 37, Figs. 5A–B, 6A–6B
`(describing a seismic imaging function that can be adapted to utilize the
`disclosed parallelism, where computational process 610 “loops over the
`depth slices as indicated by reference number 622 and loops over the shots
`as indicated by reference number 624”). Also, reservoir simulation
`applications, which “process fluid flow data in . . . oil and gas subsurface
`reservoirs to produce extraction models,” would benefit from the disclosed
`process because they define a three dimensional set of cells for the reservoir,
`utilize repeated operations on each cell, and “information computed for each
`cell is then passed to neighboring cells.” Id. at col. 9, l. 59–col. 10, l. 2; see
`id. at col. 7, l. 38–col. 8, l. 20, Figs. 7A–7D (describing “process 700 for
`performing a representative systolic wavefront operation in the form of a
`reservoir simulation function” in which “the computation of fluid flow
`properties are communicated to neighboring cells 710” without storing data
`
`
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`7
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`in memory, “a set of cells can reside in an adaptive processor,” and “the
`pipeline of computation can extend across multiple adaptive processors,”
`where the process involves nested loops and systolic walls 712 and 714 of
`computation at different time sets), col. 8, l. 21–col. 9, l. 9, Figs. 8A–8C,
`9A–9C (describing two other processes for performing “a representative
`systolic wavefront operation”). Finally, the disclosed process may be used
`for genetic pattern matching applications, which “look[] for matches of a
`particular genetic sequence (or model) to a database of genetic records,”
`performing repeated operations to “compare[] each character in the model to
`the characters in [a particular] genetic record.” Id. at col. 11, ll. 42–52.
`
`
`B. Illustrative Claim
`Claim 1 of the ’800 patent is independent. Claims 2–5, 7–9, 15, 17,
`18, and 20–24 each depend from claim 1. Claim 1 recites:
`1. A method for data processing in a reconfigurable
`computing system,
`the reconfigurable computing system
`comprising at
`least one
`reconfigurable processor,
`the
`reconfigurable processor comprising a plurality of functional
`units, said method comprising:
`transforming an algorithm into a data driven calculation
`that is implemented by said reconfigurable computing system at
`the at least one reconfigurable processor;
`forming at least two of said functional units at the at least
`one reconfigurable processor to perform said calculation wherein
`only functional units needed to solve the calculation are formed
`and wherein each formed functional unit at the at least one
`reconfigurable processor interconnects with each other formed
`functional unit at the at least one reconfigurable processor based
`on reconfigurable routing resources within the at least one
`reconfigurable processor as established at formation, and
`wherein lines of code of said calculation are formed as clusters
`
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`8
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`of functional units within the at least one reconfigurable
`processor;
`utilizing a first of said formed functional units to operate
`upon a subsequent data dimension of said calculation forming a
`first computational loop; and
`substantially concurrently utilizing a second of said
`formed functional units to operate upon a previous data
`dimension of said calculation generating a second computational
`loop wherein said implementation of said calculation enables
`said first computational loop and said second computational loop
`execute concurrently and pass computed data seamlessly
`between said computational loops.
`
`C. The Prior Art
`Petitioner relies on the following prior art:
`in
`Jean-Luc Gaudiot, “Data-Driven Multicomputers
`Digital Signal Processing,” Proceedings of the IEEE, Special
`Issue on Hardware and Software for Digital Signal Processing,
`vol. 75, no. 9, Sept. 1987, pp. 1220–1234 (Ex. 1010, “Gaudiot”);
`Duncan A. Buell, Jeffrey M. Arnold, & Walter J.
`Kleinfelder, SPLASH2: FPGAS
`IN A CUSTOM COMPUTING
`MACHINE (1996) (Ex. 1007, “Splash2”);
`Carl Ebeling et al., “Mapping Applications to the RaPiD
`Configurable Architecture,” Proceedings of
`the
`IEEE
`Symposium on FPGAs for Custom Computing Machines,
`Apr. 16–18, 1997, pp. 106–115 (Ex. 1009, “RaPiD”);
`Michael Rencher & Brad L. Hutchings, “Automated
`Target Recognition on SPLASH 2,” Proceedings of the IEEE
`Symposium on FPGAs for Custom Computing Machines,
`Apr. 16–18, 1997, pp. 192–200 (Ex. 1011, “Chunky SLD”);
`Yong-Jin Jeong & Wayne P. Burleson, “VLSI Array
`Algorithms and Architectures for RSA Modular Multiplication,”
`IEEE Transactions on Very Large Scale Integration (VLSI)
`Systems, vol. 5, no. 2, June 1997, pp. 211–217 (Ex. 1061,
`“Jeong”); and
`
`
`
`9
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`D. Roccatano et al., “Development of a Parallel Molecular
`Dynamics Code on SIMD Computers: Algorithm for Use of Pair
`List Criterion,” Journal of Computational Chemistry, vol. 19,
`no. 7, May 1998, pp. 685–694 (Ex. 1012, “Roccatano”).3
`
`D. The Asserted Grounds
`Petitioner challenges claims 1–5, 7–9, 15, 17, 18, and 20–24 of the
`’800 patent as unpatentable on the following grounds:
`Case Number(s) Reference(s)
`Basis
`
`Splash2
`
`Splash2
`
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`IPR2018-01605 Splash2 and
`RaPiD
`
`Splash2 and
`Gaudiot
`
`Claim(s)
`Challenged
`1, 15, 18, 21,
`and 22
`
`35 U.S.C.
`§§ 102(a) and
`102(b)4
`35 U.S.C. § 103(a) 1, 15, 18, 21,
`and 22
`
`35 U.S.C. § 103(a) 1, 15, 18, 21,
`and 22
`
`35 U.S.C. § 103(a) 8 and 9
`
`
`3 When citing each of the references, we refer to the page numbers in the
`bottom-right corner added by Petitioner. See 37 C.F.R. § 42.63(d)(2).
`4 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
`challenged claims of the ’800 patent have an effective filing date before the
`effective date of the applicable AIA amendments, we refer to the pre-AIA
`versions of 35 U.S.C. §§ 102 and 103.
`
`
`
`10
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`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
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`
`Case Number(s) Reference(s)
`
`IPR2018-01605 Splash2,
`RaPiD, and
`Gaudiot5
`IPR2018-01605 Splash2 and
`Jeong
`IPR2018-01605 Splash2,
`Jeong, and
`Gaudiot
`IPR2018-01606 Splash2 and
`Chunky SLD
`IPR2018-01606 Splash2,
`Chunky SLD,
`and Gaudiot
`IPR2018-01607 Splash2 and
`Roccatano
`IPR2018-01607 Splash2,
`Roccatano,
`and Gaudiot
`
`
`
`Basis
`
`Claim(s)
`Challenged
`35 U.S.C. § 103(a) 8 and 9
`
`35 U.S.C. § 103(a) 20
`
`35 U.S.C. § 103(a) 20
`
`35 U.S.C. § 103(a) 7, 17, and 24
`
`35 U.S.C. § 103(a) 7, 17, and 24
`
`35 U.S.C. § 103(a) 2–5, 22, and
`23
`35 U.S.C. § 103(a) 2–5, 22, and
`23
`
`III. ANALYSIS
`A. Discretionary Denial Under 35 U.S.C. § 314(a)
`As an initial matter, Patent Owner argues that we should exercise
`discretion to deny the Petitions under § 314(a). Prelim. Resp. 5–13;
`Sur-Reply 1–5. Petitioner argues that we should not. Reply 1–5.6 General
`
`
`5 For many of Petitioner’s asserted grounds, Petitioner relies on certain
`references “with or without” Gaudiot. See Pet. 5; -1606 Pet. 5; -1607 Pet. 5.
`6 The parties assert substantially the same arguments in all three
`proceedings. Where applicable, we cite the papers in Case IPR2018-01605
`for convenience.
`
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`11
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`3.
`
`4.
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`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
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`Plastic Indus. Co., Ltd. v. Canon Kabushiki Kaisha, Case IPR2016-01357
`(PTAB Sept. 6, 2017) (Paper 19) (precedential) (“General Plastic”), set
`forth a list of seven non-exclusive factors that the Board considers in
`determining whether to exercise discretion under § 314(a):
`1. whether the same petitioner previously filed a petition
`directed to the same claims of the same patent;
`2. whether at the time of filing of the first petition the
`petitioner knew of the prior art asserted in the second
`petition or should have known of it;
`whether at the time of filing of the second petition the
`petitioner already received the patent owner’s preliminary
`response to the first petition or received the Board’s
`decision on whether to institute review in the first petition;
`the length of time that elapsed between the time the
`petitioner learned of the prior art asserted in the second
`petition and the filing of the second petition;
`5. whether the petitioner provides adequate explanation for
`the time elapsed between the filings of multiple petitions
`directed to the same claims of the same patent;
`the finite resources of the Board; and
`the requirement under 35 U.S.C. § 316(a)(11) to issue a
`final determination not later than 1 year after the date on
`which the Director notices institution of review.
`General Plastic at 9–10. Petitioner filed its three Petitions in the instant
`proceedings on September 6, 2018, and Patent Owner has not identified any
`previously filed petition seeking review of the ’800 patent. Thus, the
`concerns outlined in General Plastic regarding the filing of serial petitions
`over time do not apply. Patent Owner does not argue that the General
`Plastic factors above weigh in favor of exercising discretion to deny
`institution of inter partes review under § 314(a). Accordingly, we conclude
`
`6.
`7.
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`that none of the factors above weigh in favor of exercising discretion to deny
`the Petitions under § 314(a).
`The General Plastic factors are non-exclusive, however, and Patent
`Owner argues that three other considerations support denial. Prelim. Resp.
`6–7. First, Patent Owner argues that SRC Labs, LLC (“SRC”)7 is the “sole
`source provider to Lockheed Martin” for the U.S. Army’s Tactical
`Reconnaissance and Counter-Concealment Radar (“TRACER”) program,
`which “requires extremely high-performance signal processing in a very
`limited size, weight, and power (‘SWAP’) environment.” Id. at 2, 8. Patent
`Owner argues that “SRC/DirectStream’s processors have allowed [the
`TRACER program’s] surveillance operations to produce images of targets
`on the ground in real-time, providing immediately actionable information.”
`Id. at 8. In support of its arguments, Patent Owner cites a declaration from
`Lockheed Martin’s Engineering Program Manager in charge of the
`TRACER program, who testifies that “Lockheed Martin’s own procurement
`process showed no other vendor could match” the capabilities of
`SRC/DirectStream’s processors and, in his opinion, “it is in the best security
`interests of the United States as a whole, and Lockheed Martin in particular,
`to keep companies like SRC/DirectStream healthy and unencumbered so
`they can stay focused on technology development that they have proven they
`can do best” and “our national security interests are not served by requiring
`
`
`7 Patent Owner contends that the ’800 patent resulted from work done by
`SRC Computers, which has since “restructured into three entities:
`a corporate parent FG-SRC, LLC, an operating company DirectStream,
`LLC, and a licensing entity called SRC Labs, LLC,” where DirectStream,
`LLC (“DirectStream”) and SRC “operate in tandem.” Prelim. Resp. 3
`(citing Ex. 2036 ¶ 1).
`
`
`
`13
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`SRC/DirectStream to spend time or money defending against inter partes
`review proceedings.” Ex. 2033 ¶¶ 21–23; see Prelim. Resp. 2, 9; Sur-Reply
`3–5. Patent Owner contends that “[t]he cost of defending [ten petitions filed
`by Petitioner seeking inter partes review of six patents owned by Patent
`Owner] may put SRC out of business.” Prelim. Resp. 2 (citing Ex. 2036
`¶¶ 9–10). Patent Owner owns the ’800 patent, SRC is an exclusive licensee
`of the patent with a right to sublicense it, and DirectStream is an operating
`company. See id. at 4; Ex. 2036 ¶¶ 1–3.
`We are not persuaded, on the record presented, that institution should
`be denied under § 314(a) based on the commercial activities of SRC and
`DirectStream, which do not own the subject patent and are not parties to
`these proceedings. Further, as Petitioner points out, Patent Owner does not
`provide any information showing that SRC/DirectStream “actually sells a
`product practicing any of the challenged claims [of the ’800 patent]” or
`demonstrating “why a finding of unpatentability might interfere with
`[SRC/DirectStream’s] ability to make or sell such products.” Reply 4. In
`addition, the time and costs associated with a party defending an inter partes
`review, should a trial be instituted, exist in every such proceeding, as
`Petitioner also points out. Id.
`Second, Patent Owner argues that we should deny institution because
`Petitioner is “relying on the same prior art . . . and arguments in its district
`court invalidity contentions,” but waited ten months from the filing of the
`complaint in the related district court case to file its Petitions. Prelim. Resp.
`10–12 (citing Exs. 2052, 2055); see -1606 Ex. 2059; -1607 Ex. 2060. Patent
`Owner also contends that it sued Amazon (Amazon Web Services, Inc.,
`Amazon.com, Inc., and VADATA, Inc.) for infringement of the ’800 patent
`
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`in another district court case, and Amazon, in its invalidity contentions,
`relies on the same primary reference as Petitioner (Splash2). Id. at 11–12
`(citing Exs. 2050, 2051). Finally, Patent Owner argues that Petitioner filed
`three Petitions challenging claim 1 as unpatentable based on Splash2, and
`Petitioner’s “duplicative challenges . . . [are] both inefficient and impact[]
`Patent Owner’s ability to defend its patent.” Id. at 12.
`We are not persuaded by Patent Owner’s arguments. The related
`district court cases are not at an advanced stage where a trial (that would
`result in a decision on Petitioner’s invalidity arguments) is scheduled to take
`place soon. Indeed, the district court, in November 2018, stayed both cases
`pending our decisions on these Petitions and related petitions seeking inter
`partes review. See Ex. 2020. Accordingly, there are no inefficiencies
`associated with the instant proceedings because the parallel proceedings are
`stayed pending these proceedings. Nor are the Petitions here serial
`challenges to the same patent, as they were all filed on the same day by the
`same petitioner. Although there is overlap between them, such overlap
`appears to be the result of claim 1 being the sole challenged independent
`claim and Petitioner challenging different dependent claims in each Petition.
`We also consolidate the proceedings to maximize efficiency going forward.
`Third, Patent Owner argues that we should deny institution because
`Patent Owner is “a federally recognized, American Indian Tribe” and, “as a
`sovereign government, is not amenable to suit unless it expressly consents or
`Congress abrogates its immunity.” Prelim. Resp. 12–13. Patent Owner
`argues that it filed a petition for a writ of certiorari appealing the U.S. Court
`of Appeals for the Federal Circuit’s decision in Saint Regis Mohawk Tribe v.
`Mylan Pharmaceuticals Inc., 896 F.3d 1322, 1327 (Fed. Cir. 2018), and
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`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`notes the Federal Circuit’s statement that the “Director bears the political
`responsibility of determining which cases should proceed” and may deny
`institution “based on a party’s status as a sovereign.” Id. at 13 (emphasis
`omitted).
`We are not persuaded by Patent Owner’s argument. The Federal
`Circuit held in Mylan that “tribal sovereign immunity cannot be asserted in
`[inter partes reviews],” 896 F.3d at 1326, and the Supreme Court of the
`United States has not yet decided Patent Owner’s petition for a writ of
`certiorari with respect to that decision. We also found no good cause to
`extend the time for Patent Owner to file its Preliminary Responses given the
`pending petition for a writ of certiorari. Paper 14. Based on the particular
`facts of these proceedings, including the points addressed above and that the
`General Plastic factors do not weigh in favor of exercising discretion to
`deny institution under § 314(a), we decline to exercise such discretion.
`
`B. Claim Interpretation
`We interpret claims in an unexpired patent using the “broadest
`reasonable construction in light of the specification of the patent in which
`[they] appear[].” 37 C.F.R. § 42.100(b) (2017).8 Under this standard, we
`interpret claim terms using “the broadest reasonable meaning of the words in
`
`
`8 Patent Owner argues that we should apply the federal court claim
`interpretation standard. Prelim. Resp. 18–19. The Petitions in these
`proceedings, however, were filed on September 6, 2018, prior to the
`effective date of the rule change that replaces the broadest reasonable
`interpretation standard with the federal court claim interpretation standard.
`See Changes to the Claim Construction Standard for Interpreting Claims in
`Trial Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg.
`51,340, 51,340 (Oct. 11, 2018).
`
`
`
`16
`
`
`
`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`their ordinary usage as they would be understood by one of ordinary skill in
`the art, taking into account whatever enlightenment by way of definitions or
`otherwise that may be afforded by the written description contained in the
`applicant’s specification.” In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
`1997). “Under a broadest reasonable interpretation, words of the claim must
`be given their plain meaning, unless such meaning is inconsistent with the
`specification and prosecution history.” TriVascular, Inc. v. Samuels, 812
`F.3d 1056, 1062 (Fed. Cir. 2016).
`The parties propose interpretations for numerous terms in the
`challenged claims. See Pet. 10–19; Prelim. Resp. 19–30; -1606 Pet. 10–17;
`-1606 Prelim. Resp. 19–31; -1607 Pet. 10–19; -1607 Prelim. Resp. 20–31.
`We have reviewed all of the proposed interpretations and conclude that, for
`purposes of this Decision, only three terms require express interpretation.
`
`
`1. “Data Driven”
`Claim 1 recites “transforming an algorithm into a data driven
`calculation that is implemented by said reconfigurable computing system at
`the at least one reconfigurable processor” (emphases added). Petitioner
`argues that “data driven” should be given its plain and ordinary meaning of
`“the scheduling of operations upon the availability of their operands,” citing
`the use of the term in Gaudiot and one other reference. Pet. 11 (citing
`Ex. 1010, 1220; Ex. 1034, 141). Patent Owner argues that the plain and
`ordinary meaning of the term is “[c]omputation triggered by the availability
`of input data,” citing two other references. Prelim. Resp. 25 (citing
`Ex. 2047, 1; Ex. 2048, 2).
`
`
`
`17
`
`
`
`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`
`We see little difference between the parties’ proposed interpretations,
`and Patent Owner’s cited sources are consistent with Petitioner’s proposed
`interpretation. See Ex. 2047, 1 (“the availability of operands triggers the
`execution of [an] operation”); Ex. 2048, 2 (“an instruction is ready for
`execution when its operands have arrived”). On this record, applying the
`broadest reasonable interpretation of the claims in light of the Specification,
`we interpret “data driven” to mean the scheduling of operations upon the
`availability of their operands.
`
`
`2. “Computational Loop”
`Claim 1 recites “utilizing a first of said formed functional units to
`operate upon a subsequent data dimension of said calculation forming a first
`computational loop” and “substantially concurrently utilizing a second of
`said formed functional units to operate upon a previous data dimension of
`said calculation generating a second computational loop” (emphases added).
`Petitioner does not propose an interpretation for “computational loop” in its
`Petitions. Patent Owner argues that “computational loop” should be given
`its plain and ordinary meaning and interpreted to mean “a sequence of
`computations that is repeated until a prescribed condition is satisfied.”
`Prelim. Resp. 21. Patent Owner submits a dictionary definition for
`“computation” and three dictionary definitions for “loop,” relying in
`particular on the following definition: “a sequence of instructions that is
`repeated until a prescribed condition, such as agreement with a data element
`or completion of a count, is satisfied.” Id. at 21–22 (citing Exs. 2024–2026,
`2038). Patent Owner also argues that its interpretation is consistent with
`both the Specification of the ’800 patent, which “depicts numerous ‘loops’
`
`
`
`18
`
`
`
`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`that are repeated until some condition is met,” and an article that the
`’800 patent purportedly incorporates by reference. Id. at 22 (citing
`Ex. 1005, col. 4, ll. 58–62, col. 5, l. 65–col. 6, l. 28, col. 6, l. 46–col. 7, l. 43,
`col. 8, ll. 22–39, Figs. 4A–4B, 6B–6G, 7A, 8A–8B; Ex. 2037).
`The three dictionary definitions of “loop” submitted by Patent Owner
`are similar in that they all describe a set of instructions executed repeatedly
`until a particular condition exists—until “a prescribed condition, such as
`agreement with a data element or completion of a count” (Ex. 2024),
`“a terminal condition” (Ex. 2025), or “a fixed number of times or until some
`condition is true or false” (Ex. 2026). We conclude, based on the current
`record, that the third definition reflects the broadest reasonable interpretation
`of “loop” and most closely mirrors how the term is used in the Specification.
`See, e.g., Ex. 1005, col. 6, l. 67–col. 7, l. 3 (explaining that computational
`process 610 “loops over the depth slices” and “loops over the shots” of a
`seismic imaging application), Figs. 7A (depicting three loops each
`performing computations a particular number of times as “k = 1, nz”; “j = 1,
`ny”; and “i = 1, nx”), 8B (depicting two loops as “i = 1, l” and “k = 1, m”);
`see also Ex. 2037, 7 (depicting an algorithm programming flow with a loop
`incrementing J by one each iteration until J = N, and an associated
`“algorithm data flow that will be put into hardware logic for the
`[field-programmable gate arrays (FPGAs)]”). On this record, applying the
`broadest reasonable interpretation of the claims in light of the Specification,
`we interpret “computational loop” to mean a set of computations that is
`executed repeatedly, either a fixed number of times or until some condition
`is true or false.
`
`
`
`
`19
`
`
`
`IPR2018-01605, IPR2018-01606, IPR2018-01607
`Patent 7,620,800 B2
`
`
`3. “Pass Computed Data Seamlessly Between Said Computational Loops”
`Claim 1 recites that “said implementation of said calculation enables
`said first computational loop and said second computational loop execute
`concurrently and pass computed data seamlessly between said computational
`loops.” Petitioner argues that “pass computed data seamlessly between said
`computational loops” should be interpreted to mean “communicate
`computed data directly between functional units that are calculating
`computational loops.” Pet. 15. Patent Owner argues that Petitioner’s
`proposed interpretation is “overly broad” and the phrase instead should be
`interpreted to mean “communicating the computed data over the
`reconfigurable routing resources between said computational loops.”
`Prelim. Resp. 27–29.
`We are not persuaded, based on the current record, that Petitioner’s
`proposed interpretation is unreasonably broad. Both parties point to an
`Offic
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