throbber
Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 1 of 18 PageID #: 86
`
`Exhibit 4
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 2 of 18 PageID #: 87
`
`USOO6972790B2
`
`(12) United States Patent
`Suska
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,972,790 B2
`Dec. 6, 2005
`
`(54) HOST INTERFACE FOR IMAGING ARRAYS
`
`(75) Inventor: Mark Suska, Ottawa (CA)
`
`(*) Notice:
`
`(73) Assignee: Psion Teklogix Systems Inc.,
`Mississauga (CA)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 953 days.
`(21) Appl. No.: 09/742,723
`
`(22) Filed:
`(65)
`
`Dec. 21, 2000
`Prior Publication Data
`US 2002/0080244 A1
`Jun. 27, 2002
`Related U.S. Application Data
`(60) Provisional application No. 60/177,496, filed on Jan.
`21, 2000.
`
`(51) Int. Cl." .............................................. H04N 5/228
`(52) U.S. Cl. ............................... 348/222.1; 348/230.1;
`348/312; 348/231.6; 348/231.3
`(58) Field of Search .......................... 348/231.6, 231.1,
`348/231.9, 231.99, 222.1, 211.14, 207.2,
`348/207.1,230.1, 312,231.3,317
`
`(56)
`
`4/2004 Lee et al. ................... 348/302
`6,721,008 B2
`6,833,862 B1* 12/2004 Li .............
`... 348/207.99
`2002/0101528 A1
`8/2002 Lee et al. ................... 348/304
`2002/0191090 A1 12/2002 Safai .......................... 348/239
`2004/0004664 A1
`1/2004 Safai ..................... 348/231.99
`FOREIGN PATENT DOCUMENTS
`O 932 302 A2
`7/1999
`OTHER PUBLICATIONS
`OmniVision: “OV511 Advanced Camera to USB Bridge,
`Data Sheet Rev. 1.0', Jul. 17, 1998, OmniVision Technolo
`gies, XP002293773, * p. 6-p. 14 *, * tables 9-11 *, * figures
`1-4, 6,10,12 *.
`
`EP
`
`(Continued)
`Primary Examiner Thai Tran
`ASSistant Examiner-Nelson D. Hernandez
`(74) Attorney, Agent, or Firm-Pearne & Gordon LLP
`(57)
`ABSTRACT
`
`21 Claims, 8 Drawing Sheets
`
`An interface for receiving data from an image Sensor having
`an imaging array and a clock generator and for transferring
`the data to a processor System is described. The interface
`comprises a memory for Storing the imaging array data and
`the clocking Signals at a rate determined by the clocking
`Signals. In response to the quantity of data in the memory, a
`Signal generator generates a signal for transmission to the
`processor System and a circuit controls the transfer of the
`data from the memory at a rate determined by the processor
`References Cited
`system. The memory may be a first-in first-out (FIFO) buffer
`or an addressable memory. The interface is preferably inte
`U.S. PATENT DOCUMENTS
`grated on the same die as the image sensor. The Signal
`4,837.628 A * 6/1989 Sasaki ..................... 348/220.1
`generator may generate either an interrupt Signal for trans
`5,786.851 A * 7/1998 Kondo et al. ............ 348/222.1
`mission to the processor System or a bus request Signal for
`5,801,773 A : 9/1998 Ikeda ...................... 348/229.1
`E. A : S. yearst als sil transmission to a bus arbitration unit for the processor
`6,064,355. A
`5/2000 Donahue et al. ............... 345/8
`System.
`6,493.025 B1* 12/2002 Kiriyama et al. ........ 348/207.1
`6,704,310 B1* 3/2004 Zimmermann et al. ..... 370/389
`
`?terface ;
`
`Y-13
`
`: OTHER
`Ecry
`costs
`------
`i
`
`&
`--
`
`|
`
`|
`
`wiDEO
`St.
`
`MAGIMS
`are
`^-12
`-
`1
`--
`
`&
`
`44
`| -
`0
`21-
`FFC BUFER
`MAGNG
`ri
`array 38.
`3.
`.
`47-s:
`as
`s
`INTERRUPT "r,
`B: ADERESS
`RSA
`:
`e
`GENERATER
`iso,
`---
`
`it.
`
`Y-15
`W
`
`1
`
`&
`
`essRator
`
`
`
`I
`
`56-
`S
`
`4ss
`
`COMMAND !
`DECODE:
`
`Y,
`-
`
`Comistration
`REGISTERs
`Y-4s
`
`Y-1s
`
`8,
`a.
`
`array
`REGISTERs
`Y
`
`& 15
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 3 of 18 PageID #: 88
`
`US 6,972,790 B2
`Page 2
`
`OTHER PUBLICATIONS
`Omnivision: "OV7610 Single-Chip CMOS VGA Color
`Digital Camera, Datasheet V1.3", May 15, 1999, OmniVi-
`sion, XP002293774, * p. 3-p. 11 *, * figure 1 *.
`Texas Instruments: “TMS320C54X DSP Reference Set; vol.
`1: CPU and Peripherals”, Apr. 1999, Texas Instruments,
`
`c: :
`
`c:
`
`XP002293775, * pp. 2-12 *, * pp. 2-14-pp. 2-15 *, * pp.
`IEEE. E.E...
`Fossum E. R. : “Digital Camera System on a Chip", IEEE
`Mi
`IEEE Inc. New York, US 1. 18. No. 3. Mav 1.
`1CrO,
`nc. New York, US, Vol. 18, No. 3, May 1,
`1998, pp. 8-15, XP000755752 ISSN: 0272-1732, * p. 12 * .
`* cited by examiner
`
`c:
`
`c:
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 4 of 18 PageID #: 89
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 1 of 8
`
`US 6,972,790 B2
`
`1O
`
`
`
`
`
`
`
`WDEO
`CLOCK
`GENERATOR
`
`
`
`
`
`
`
`14
`
`FIGURE 1
`
`
`
`MEMORY
`COMPONENTS
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 5 of 18 PageID #: 90
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 2 of 8
`
`US 6,972,790 B2
`
`12 N.
`Y.
`
`
`
`13
`
`N
`
`
`
`21 N.
`- -
`IMAGING
`|ARRAY
`a
`e - array
`ADDRESS
`B
`B.
`GENERATOR
`Y-22
`
`
`
`
`
`is
`
`C.
`
`READ
`control.
`Saw
`
`NTERRUPT
`GENERATOR
`St
`S.
`-
`CONFIGURAON
`REGISTERS
`N
`45 -
`- Leslie
`15
`46
`
`
`
`
`
`16 YJ COMMAND
`
`DECODER
`
`
`
`
`
`ARRAY
`REGISTERS
`
`FIGURE 2
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 6 of 18 PageID #: 91
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 3 of 8
`
`US 6,972,790 B2
`
`COLUMN AMPLIFERS,
`--- GAIN AMPLIFIERS,
`COLUMN SELECTORS
`
`
`
`
`
`
`
`
`
`LINE
`DRIVERS
`35
`
`3 -
`32
`
`ARRAY OF PXELS
`
`FIGURE 3
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 7 of 18 PageID #: 92
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 4 of 8
`
`US 6,972,790 B2
`
`B.
`
`i
`
`C
`
`22 N
`
`42 N
`
`ROW
`COUNTER
`
`41
`
`C
`
`COLUMN
`COUNTER
`
`A. th
`
`FIGURE 4
`
`As
`
`C.
`
`C
`
`A.
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 8 of 18 PageID #: 93
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 5 of 8
`
`US 6,972,790 B2
`
`
`
`
`
`
`
`
`
`INCREMENT/DECREMENT
`COUNTER
`
`SHIFT REGISTER
`
`FIGURE 5
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 9 of 18 PageID #: 94
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 6 of 8
`
`US 6,972,790 B2
`
`BUS
`ARBTRATION
`
`
`
`1 O
`
`C
`
`MAGNG
`ARRAY
`
`INTERFACE
`
`MEMORY
`COMPONENTS
`
`15
`
`11
`
`
`
`
`
`14
`
`VIDEO
`CLOCK
`GENERATOR
`
`
`
`FIGURE 6
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 10 of 18 PageID #: 95
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 7 of 8
`
`US 6,972,790 B2
`
`73
`44 N
`c. -
`FIFO BUFFER
`
`Y-15
`
`D
`
`64 sy
`N 55
`
`17
`BUS REO UEST NS
`GENERATOR -----
`
`D,
`
`C
`C.
`
`12-N
`
`21
`- Y -
`MAGING
`| ARRAY
`
`
`
`
`
`C.
`
`
`
`ARRAY
`ADDRESS
`B
`B. GENERATOR
`N2
`
`/
`
`-Hi-e
`
`Saa
`
`
`
`
`
`
`
`Saa
`
`Ses
`
`s
`
`CONFIGURATION
`REGISTERS
`
`46
`
`49
`
`N Y-87
`
`COMMAND
`UNIT
`
`OUTPUT
`S. ADDRESS
`UNIT
`
`COMMAND
`
`ARRAY
`
`58
`N
`-
`
`
`
`FIGURE 7
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 11 of 18 PageID #: 96
`
`U.S. Patent
`
`Dec. 6, 2005
`
`Sheet 8 of 8
`
`US 6,972,790 B2
`
`12
`N
`
`83
`Y
`
`C.
`
`\
`
`MEMORY
`
`81 N
`21 N
`AppRESSABLE
`Imaging is
`ARRAY
`N38 ---
`N15 - - N
`
`D
`
`er
`
`S,
`
`17
`
`82
`
`SR
`Y
`
`48 N s: 55
`-
`
`ADDRESS
`B
`R-
`: B.E GENERATOR
`N 22
`
`| C-
`s
`
`-
`
`Er NTERRUPT
`GENERATOR
`CONTROL
`A
`
`
`
`MEMORY
`CONFIGURATION
`REGISTERS
`
`45 -
`
`16 N
`
`COMMAND
`DECODER
`
`85
`Y
`Y-57
`
`B
`
`-
`
`FIGURE 8
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 12 of 18 PageID #: 97
`
`1
`HOST INTERFACE FOR IMAGING ARRAYS
`
`US 6,972,790 B2
`
`2
`SUMMARY OF THE INVENTION
`
`This application claims the benefit of U.S. Provisional
`Patent Application Ser. No. 60/177,496 filed on Jan. 21,
`2OOO.
`
`FIELD OF THE INVENTION
`
`The invention relates generally to integrated electronic
`image Sensing circuitry and more particularly to CMOS
`imaging circuitry.
`
`BACKGROUND OF THE INVENTION
`
`15
`
`25
`
`Integrated circuit (IC) technology, applied to imaging, is
`revolutionizing that field. Semiconductors can be used to
`represent an image as an electrical Signal. Charge coupled
`devices (CCDs) are the most significant commercial IC
`technology to date. However, when compared with CMOS
`technology, there are many advantages to producing CMOS
`image devices.
`CMOS is a less expensive technology; CMOS employs
`fewer mask layerS and is a more mature fabrication tech
`nology with greater commercial Volume. CCD technology
`complexity causes lower fabrication yield. One of the main
`benefits of employing CMOS technology, compared to
`CCD, is the ability to include image-processing elements on
`the same Substrate as the imaging circuitry.
`On a monolithic Semiconductor IC, with a Surface coin
`cident to an optical focal plane, photosensitive elements are
`employed in pixels that are arranged in an array of rows and
`columns. The basis for the pixels of CMOS technology is a
`photoSensitive diode. In an active pixel arrangement each
`35
`pixel photodiode is buffered from the shared readout com
`ponents by an amplification Stage.
`IC image Sensors of existing technologies provide Video
`Style output. In one example, Such a Sensor receives master
`clock input. The Sensor derives data Sample, line, and clockS
`from this master clock. These clocks, which correspond to
`pixel, row, and column, control the Sampling rate of the
`imaging array. The pixel data of Such a Sensor is output at the
`Same rate as it is Sampled. The derived clocks are output as
`well to Synchronize the data output. The result is a stream of
`Synchronized pixel intensities comprising a Video frame.
`This output is incompatible with the data interface of
`commercial microprocessors, without the use of additional
`glue logic. A commercial microprocessor data interface
`consists of address and control output Signals and data
`input/output signals. This configuration allows the processor
`to randomly acceSS any word of data in memory by asserting
`various addresses.
`In an image acquiring computer System based on Such a
`Sensor and Such a processor, additional interface circuitry to
`respond to the Sensor clock outputs to Sample the Video
`information, and to make this video data available in the
`memory Space of the processor. Optionally, this interface
`circuit may include interrupt signals to the processor, and
`enough memory Space for a number of pixels.
`Such additional circuitry diminishes the benefit of a single
`Substrate that integrates Sensor and processing elements. The
`CMOS technology optimum cost benefit is not reached.
`Therefore, there is a need for an interface which may be
`integrated with the imaging array which a System processor
`can access to directly receive imaging data.
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`This invention is directed to an interface for receiving
`data from an image Sensor having an imaging array and a
`clock generator, and for transferring the data to a processor
`System. The interface comprises a memory for Storing the
`imaging array data and the clocking Signals at a rate deter
`mined by the clocking Signals. In response to the quantity of
`data in the memory, a Signal generator generates a signal for
`transmission to the processor System and a circuit controls
`the transfer of the data from the memory at a rate determined
`by the processor System. The memory may be a first-in
`first-out (FIFO) buffer or an addressable memory.
`The Signal generator may generate an interrupt signal for
`transmission to the processor System or a bus request Signal
`for transmission to a bus arbitration unit for the processor
`System. The circuit for controlling the transfer of the data
`may include a command decoder for receiving address and
`command Signals from the processor System, a configuration
`register for storing configuration data for the FIFO buffer
`and a read control for controlling the read-out of the FIFO
`buffer, and may further include a bus command unit for
`receiving control of the System bus and providing an address
`for the data read-out from the memory.
`In accordance with another aspect of this invention, an
`integrated Semiconductor imaging circuit for use with an
`electronic processing System having a data bus comprises an
`imaging array Sensor having an array of Sensing pixels and
`an array address generator integrated on a die and an
`interface integrated on the same die. The interface is adapted
`to receive data from the imaging array Sensor as determined
`by the imaging array and to transfer the data to the electronic
`processing System as determined by the electronic process
`ing System. The interface may include a memory Such as a
`FIFO buffer or an addressable memory for storing imaging
`array data and address Signals at a rate determined by the
`imaging array Sensor, and a circuit for controlling the
`transfer of the data from the memory means to the data bus
`at a rate determined by the electronic processing System. The
`imaging circuit may further include a bus arbitration circuit
`integrated on the same die and coupled to the circuit for
`controlling the transfer of the data.
`In accordance with a further aspect of this invention, an
`integrated Semiconductor imaging circuit for use with an
`electronic processing System having a data bus may com
`prise an imaging array of Sensing pixels, a buffer for Storing
`data received at an input port and for Outputting data through
`an output port to the data bus, a circuit for transferring data
`from a Selected pixel to the buffer input port, a circuit for
`determining the quantity of data in the buffer, a circuit for
`alerting the electronic processing System when the quantity
`of data in the buffer attains a predetermined level and a
`controller adapted to respond to the electronic processing
`System for controlling the transfer of the Stored data through
`the buffer output port.
`In accordance with another aspect of this invention, an
`integrated Semiconductor imaging circuit for use with an
`electronic processing System having a data bus and a System
`address/control bus, may comprise an imaging array of
`Sensing pixels, a buffer for Storing data received at an input
`port and for outputting data through an output port to the
`data bus, a circuit for transferring data from a Selected pixel
`to the buffer input port, a circuit for determining the quantity
`of data in the buffer, a controller for seeking control of the
`data bus when the quantity of data in the buffer attains a
`predetermined level and adapted to respond to the availabil
`ity of the data bus for controlling the transfer of the stored
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 13 of 18 PageID #: 98
`
`US 6,972,790 B2
`
`4
`FIG. 7 is a block diagram of an imaging array Sensor that
`includes an interface having bus arbitration circuitry; and
`FIG. 8 is a block diagram of an imaging array Sensor that
`includes an interface having an addressable memory.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The imaging computer System illustrated in FIG. 1
`includes a central processing unit (CPU) 10, other memory
`and System components 11, an imaging array Sensor 12, an
`interface 13 in accordance with the present invention and a
`video clock generator 14. The CPU 10, components 11 and
`interface 13 all have access to a system data bus 15 and are
`controlled by the CPU 11 via the system control and address
`buS 16. The clock generator 14 provides pixel clock signals
`C to the imaging array Sensor 12. The interface 13 is further
`connected to the CPU 10 through an interrupt bus 17 by
`which the CPU 10 is signalled that data is available for it to
`upload.
`In accordance with the present invention, the interface 13
`Stores data and clocking Signals from the imaging array
`sensor 12 in order to free up the CPU 10 for other process
`ing. In addition, the full economic and commercial advan
`tage of CMOS technology may be gained by integrating the
`interface 13 on the Same die as the imaging array Sensor 12.
`An embodiment of the interface 13 is illustrated as a block
`diagram in FIG. 2. The imaging array Sensor 12 includes an
`imaging array 21 which is an array of active photosensitive
`pixels with access control as will be described further with
`reference to FIG. 3. The imaging array 21 further includes
`an array address generator 22 which generates the column
`addresses A, the row addresses A, the row clock C and
`the frame clock C as will be described further with refer
`ence to FIG. 4.
`Referring to FIG. 3, the array 30 of pixels 33 is organized
`in rows 31 and columns 32. Each pixel 33 is located at the
`intersection of a row 31 and a column 32. The row control
`lines 34 provide access to a row 31 of pixels 33. The row line
`34 is driven by the row drivers 35 in response to the row
`address Signal A. Each Selected pixel 33 asserts data onto
`its own column data line 36 when accessed. The data on
`lines 36 is amplified by column amplifiers and Second Stage
`amplification in unit 37. Unit 37 further selects the column
`32 as determined by column address A, from which array
`data DA is placed on the array output 38.
`Referring to FIG. 4, the array address generator 22 is
`shown in greater detail. The column address A is generated
`by a column counter 41 which is incremented by the video
`System clock C. The maximum number of Sequential
`addresses generated by the column counter 41 will depend
`on the number of columns in the imaging array 21, however
`the actual number of Sequential addresses generated by the
`column counter 41 will be determined by the column
`boundary signal B, which is controlled by the CPU 10 as
`will be described later. The row clock C is generated by the
`overflow of the column counter 41. The row counter 42
`generates the row address Signal A based on the row clock
`Signal C and the row boundary signal B. The maximum
`number of Sequential addresses generated by the row
`counter 42 will depend on the number of rows in the imaging
`array 21, however the actual number of Sequential addresses
`generated by the row counter 42 will be determined by the
`row boundary signal B which is controlled by the CPU 10
`as will be described later. The row clock C is also applied
`
`3
`data through the buffer output port. The integrated Semicon
`ductor imaging circuit may further include a bus arbitration
`unit for receiving data bus control requests and for providing
`data bus control in response to a request, and the controller
`for receiving bus control comprising a register for Storing
`and incrementing destination addresses, and a circuit for
`asserting the destination address and write controls on the
`System address/control bus.
`In accordance with a further aspect of this invention, an
`integrated Semiconductor imaging circuit for use with an
`electronic processing System having a data bus, may com
`prise an imaging array of Sensing pixels, an addressable
`memory having a plurality of memory cells arranged in rows
`and columns for Storing data received at an input port and for
`outputting data through an output port to the data bus, a
`circuit for transferring data from a Selected pixel to a
`Selected memory cell through the memory input port, a
`circuit for determining the quantity of data in the memory,
`a circuit for alerting the electronic processing System when
`the quantity of data in the memory attains a predetermined
`level, and a controller adapted to respond to the electronic
`processing System for controlling the transfer of the Stored
`data through the memory output port.
`In accordance with another aspect of this invention, an
`integrated Semiconductor imaging circuit for use with an
`electronic processing System having a data bus and a System
`address/control bus, may comprise an imaging array of
`Sensing pixels, an addressable memory having a plurality of
`memory cells arranged in rows and columns for Storing data
`received at an input port and for outputting data through an
`output port to the data bus, a circuit for transferring data
`from a selected pixel to a selected memory cell through the
`memory input port, a circuit for determining the quantity of
`data in the memory, and a controller for Seeking control of
`the data bus when the quantity of data in the memory attains
`a predetermined level and adapted to respond to the avail
`ability of the data bus for controlling the transfer of the
`Stored data through the memory output port. The integrated
`Semiconductor imaging circuit may further include a bus
`arbitration unit for receiving data bus control requests and
`for providing data bus control in response to a request, and
`the controller for receiving bus control comprising a register
`for Storing and incrementing destination addresses, and a
`circuit for asserting the destination address and write con
`trols on the System address/control bus.
`Other aspects and advantages of the invention, as well as
`the Structure and operation of various embodiments of the
`invention, will become apparent to those ordinarily skilled
`in the art upon review of the following description of the
`invention in conjunction with the accompanying drawings.
`
`1O
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The invention will be described with reference to the
`accompanying drawings, wherein:
`FIG. 1 is a block diagram of a computer System utilizing
`the imaging array Sensor,
`FIG. 2 is a block diagram of an imaging array Sensor
`including the interface of the present invention;
`FIG. 3 is a block diagram of the pixel imaging array and
`acceSS,
`FIG. 4 is a block diagram of the video clock and array
`address generator;
`FIG. 5 is a block diagram of a FIFO buffer;
`FIG. 6 is a block diagram of a computer system with bus
`arbitration utilizing the imaging array Sensor;
`
`55
`
`60
`
`65
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 14 of 18 PageID #: 99
`
`US 6,972,790 B2
`
`6
`mask, and the FIFO interrupt register. All of these registers
`are connected to the System data buS 15 and are read/write
`capable, except the FIFO interrupt register, which is read
`only and determines its value from the interrupt generator as
`Signal S. The reading and writing of these registers is
`controlled by the FIFO register command bus 57. The output
`of the FIFO configuration registers include FIFO limit signal
`S, from the FIFO limit register, the interrupt enable signal
`S from the FIFO interrupt mask, and the output bus width
`Signal S from the FIFO output bus width register.
`The interrupt generator 48 compares the FIFO counter
`output S, and the FIFO limit S. If SeS, and if the
`interrupt enable Signal S is valid, the generator 48 asserts
`the interrupt signal S, to the CPU 10 via the interrupt bus 17.
`The use of an interrupt signal S as an interrupt to the CPU
`10 allows the processor to multi-task. It performs a buffer 44
`unload operation when the interrupt is asserted, and carries
`out other programmed tasks at all other times.
`Access to the array registers 49 is controlled by the array
`register command bus, 58. Data is exchanged with the
`system data bus 15. The content of the registers 49 defines
`the number of rows and columns to be employed in the
`imaging array 21. This information is communicated to the
`array address generator 22 by the row and column boundary
`Signals B and B.
`The above interface 13 signals the CPU 10 through the
`interrupt Signal S when it has an amount of data approach
`ing the limits of its Storage capacity. The CPU then responds
`by having the data downloaded onto the system bus 15. It is
`important for the CPU to respond to the interface faster then
`the imaging array 21 can generate data. In addition, the size
`of the FIFO buffer 44 will also depend on the latency of the
`CPU 10, since during the period of time required by the CPU
`10 to respond to the interrupt Signal S, data is being Stored
`in the buffer 44. The faster that the CPU 10 is able to respond
`to the interrupt and accept the downloaded data, the Smaller
`the buffer 44 can be and the less space that it will require if
`integrated on the die with the imaging array 21. However, in
`real time control applications, it is important that the inter
`face 13 and the CPU 10 be matched so that the data from all
`frames Scanned by the imaging array 21 is properly and
`completely transferred to the CPU 10. This requirement may
`be relaxed Somewhat for camera type applications where the
`necessity of capturing all frames is not required.
`In a further embodiment of the present invention as
`illustrated in FIG. 6, the interface 73 would interact with the
`CPU 10 and other system components through a bus arbi
`tration unit 61. Rather then Send an interrupt signal S to the
`CPU 10, the interface 73 sends a bus request signal S to
`the bus arbitration unit 61 and receives an arbitration
`acknowledgement Signal SAA when the buS 15 is available to
`it for downloading data. As illustrated in FIG. 6, the other
`units, CPU 10 and components 11 in the system have their
`own arbitration request lines 62 and arbitration acknowl
`edgement lines 63. The Bus Arbitration Unit 61 receives all
`the requests for the bus 15 and selects one unit that is
`acknowledged as the current bus master.
`The required components in the interface 73 that are
`required in order for it to be compatible with a bus arbitra
`tion system are shown in FIG. 7. A Bus Request Generator
`64 functions in the same manner as the Interrupt Generator
`48 shown in FIG. 2. AbuS request Signal S is generated in
`the same manner as the interrupt S. If S-2S, and the bus
`request enable Signal S is valid, the generator 64 asserts
`the bus request Signal S to the bus arbitration unit 61.
`An arbitration acknowledge Signal SAA notifies the inter
`face 73 that the interface 73 may assert command of the bus
`
`S
`to an output 43 from the array address generator 22. The row
`counter 42 also generates a frame signal C based on count
`overflow.
`Referring again to FIG. 2, the interface 13 includes a
`memory 44 as well as devices 45 to 49 required to support
`the memory 44. In this particular embodiment, memory 44
`is a first-in first-out (FIFO) buffer memory. FIFO buffer 44
`receives array data DA from the imaging array, clocking
`signals C. from the video clock generator 14 and clocking
`Signals C and C from the array address generator 22. FIFO
`buffer 44 is shown in greater detail in FIG. 5. The imaging
`array 21 output DA, row clock C and frame clock C. are
`bundled onto a single bus 51 for storage in the buffer 44. The
`storage components of the FIFO buffer 44 are registers 52
`arranged as a shift register Series 53. Since the total number
`of valid outputs may vary due to the differing rates of Storage
`and access, the buS 51 is connected to each register 52. An
`increment/decrement counter 54 is used to count the occur
`rences of FIFO buffer 44 writes and FIFO buffer 44 reads.
`Counter 54 has access to the pixel clock C and a FIFO read
`signal S. The FIFO counter 54 outputS is applied to buffer
`output 55 and to the Register address decoder 56. The
`decoder uses the counter output S, and pixel clock C in
`determining when to assert the appropriate register write
`Signal on lines 57. The read signal S is connected to the
`shift registers 52 to shift the registers by a number of
`registers depending on the read Signal S value. The same
`number of registers, from the end of the buffer, asserts data
`D, on the System data buS 15 during this operation.
`There are basically three types of FIFO buffers, each of
`which may be used with the present invention. The first type
`of buffer 44 is the one shown in FIG. 5 where stored data is
`removed from buffer register series 53 from the first register
`53 on the right hand end and data from the bus 51 is written
`into the last available shift register 52 from the left end of the
`buffer register series 53. A second type of buffer is one where
`the data is written into the first register on the left hand end
`of the buffer register series and data is taken out of the buffer
`register Series from the first register with data in the Series
`looking at it from the right end of the register Series. The
`third type of buffer is one in which data from the data bus
`is written into the last available shift register looking from
`the left end of the buffer register Series and data is taken out
`of the buffer register series from the first register with data
`in the Series looking at it from the right end of the register
`Series. In all three cases, data is removed from the buffer in
`the same Sequence that it is entered into the buffer.
`Referring again to FIG. 2, the interface 13 includes
`devices 45 to 49 to support the FIFO buffer 44. The devices
`include a Chip Command Decoder 45, FIFO Configuration
`Registers 46, FIFO Read Control, an Interrupt Generator 48
`and Array Registers 49.
`The CPU 10 accesses the registers 46 and 49 and FIFO
`buffer 44 through the Chip Command Decoder 45 by assert
`ing the necessary read or write commands, along with the
`address on the system address and command bus 16. The
`command decoder 45 identifies any buffer or register being
`addressed and asserts the necessary read or write Signal on
`the FIFO read control 47 line 56, the FIFO configuration
`register 46 command bus 57, or the array register 49
`command bus 58. The signal on line 56 permits the FIFO
`read control 47 to generate a FIFO read Signal S in response
`the output bus width signal S. Variation of the FIFO 44
`output bus width register provides compatibility with a
`variety of system bus configurations such as 8-bit or 32-bit.
`The FIFO configuration registers 46 include the FIFO
`output bus width, the FIFO limit value, the FIFO interrupt
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`

`

`Case 2:20-cv-00234-JRG Document 1-4 Filed 07/13/20 Page 15 of 18 PageID #: 100
`
`US 6,972,790 B2
`
`7
`15. The arbitration acknowledge Signal SAA is applied to the
`chip command decoder 45 and a bus command unit 65. The
`arbitration acknowledge Signal SAA deactivates the com
`mand decoder 45 for the duration that the interface controls
`the buS 15. On receiving the arbitration acknowledge Signal
`SAA, the bus command unit 65 will activate an output
`address unit 66 via the request output address signal SA and
`receive from it the next address on the output address Signal
`SA. This address is sent out onto the System address and
`control line 16. At the same time the bus command unit 65
`asserts the necessary read or write Signal on the FIFO read
`control 47 line 67.
`The address may represent a location in the CPU 10,
`however, one advantage of this arrangement is that the
`address may be to a location in one of the System compo
`nents 11 Such as a memory So that the data may be Stored in
`the system for processing by the CPU 10 without the CPU
`10 being disturbed to make the transfer. The output address
`unit 66 contains a register and increment circuit for the
`purpose of recording and updating this address. The
`addresses in the output address unit 66 are transferred to the
`address registers through buS 15 under the control of a signal
`from CPU 10 on the system control and address bus 16
`through command decoder 45.
`AS Stated previously, the imaging array Sensor 12 and the
`interface may be integrated onto one die. However, in
`addition, the Bus Arbitration Unit 61 may also be integrated
`onto the same die, and thus the bus arbitration request and
`acknowledge Signals on lines 62 and 63 become external
`Signals of the integrated unit.
`In a further embodiment of the present invention, the
`memory in the interface 83 may be an addressable memory
`81 as shown on FIG.8. For purposes of writing to memory
`81 from the imaging array 21 the row and frame clockSC
`and C serve as row and column addresses. The video
`System clock C. Serves as a write clock. Thus the memory
`81 records the imaging array output DA at the Same rate as
`the imaging array 21, and in the same array order as the
`imaging array 21.
`For reading purposes, the read control signal S. provides
`the necessary address information, bus width information
`and read control timing. The memory read control 82 derives
`this information from the memory configuration registerS 84
`via the output bus width signal S and from the command
`decoder 45 via the read enable and read address bus 16 and
`through line 85. The memory configuration registers 84 are
`identical to the FIFO configuration registers 46. The
`memory 81 also includes an increment/decrement counter
`Similar to counter 54 to interface with the interrupt generator
`48. In addition, the interface 83 may be adapted for use with
`a bus arbitration unit 61 in the same manner that the
`interface 73 has been adapted as described in conjunction
`with FIG. 7.
`Though the use of an addressable memory 81 in interface
`83 does not provide the size, simplicity and lower cost of a
`FIFO memory, the fact that

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket