Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 1 of 19 PageID #: 104
`
`Exhibit 5
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 2 of 19 PageID #: 105
`
`US008537242B2
`
`(12) United States Patent
`Suska
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,537,242 B2
`*Sep. 17, 2013
`
`HOST INTERFACE FOR MAGING ARRAYS
`
`(56)
`
`References Cited
`
`(54)
`(75)
`(73)
`
`Inventor: Mark Suska, Ottawa (CA)
`Assignee: Harusaki Technologies, LLC,
`Wilmington, DE (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 1584 days.
`This patent is Subject to a terminal dis
`claimer.
`
`(21)
`(22)
`(65)
`
`(62)
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Appl. No.: 11/259,791
`
`Filed:
`
`Oct. 27, 2005
`
`Prior Publication Data
`US 2006/0044435 A1
`Mar. 2, 2006
`
`Related U.S. Application Data
`Division of application No. 09/742,723, filed on Dec.
`21, 2000, now Pat. No. 6,972,790.
`Provisional application No. 60/177,496, filed on Jan.
`21, 2000.
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`Int. C.
`H04N 5/76
`H04N 5/228
`H04N 5/235
`U.S. C.
`USPC ................... 348/231.1; 348/222.1; 348/230.1
`Field of Classification Search
`USPC ................. 348/241, 294,302,307, 308, 311,
`348/207.1, 333.05, 222.1, 231.3, 231.99,
`348/312,317, 203, 246
`See application file for complete search history.
`
`EP
`JP
`
`U.S. PATENT DOCUMENTS
`4,837,628 A
`6, 1989 Sasaki
`5,581,280 A * 12/1996 Reinert et al. ................ 345/558
`(Continued)
`FOREIGN PATENT DOCUMENTS
`O932. 302 A2
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`11, 1988
`(Continued)
`OTHER PUBLICATIONS
`Omnivision: “OV511 Advanced Camera to USB Bridge, Data Sheet
`Rev. 1.0”, Jul. 17, 1998, Omnivision Technologies, XP002293773,
`p. 6-14, tables 9-11, figures 1-4, 6,10,12.
`(Continued)
`Primary Examiner — Trung Diep
`(74) Attorney, Agent, or Firm — McAndrews, Held &
`Malloy, Ltd.
`
`ABSTRACT
`(57)
`An interface for receiving data from an image sensor having
`an imaging array and a clock generator and for transferring
`the data to a processor system is described. The interface
`comprises a memory for storing the imaging array data and
`the clocking signals at a rate determined by the clocking
`signals. In response to the quantity of data in the memory, a
`signal generator generates a signal for transmission to the
`processor System and a circuit controls the transfer of the data
`from the memory at a rate determined by the processor sys
`tem. The memory may be a first-in first-out (FIFO) buffer or
`an addressable memory. The interface is preferably integrated
`on the same die as the image sensor. The signal generator may
`generate either an interrupt signal for transmission to the
`processor system or a bus request signal for transmission to a
`bus arbitration unit for the processor System.
`23 Claims, 8 Drawing Sheets
`
`12-
`
`21
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`ARRAY
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`47
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`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 3 of 19 PageID #: 106
`
`US 8,537,242 B2
`Page 2
`
`(56)
`
`References Cited
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`OTHER PUBLICATIONS
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`Omnivision: “OV7610 Single-Chip CMOSVGA Color Digital Cam
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`2-12, pp. 2-14-2-15, pp. 8-37-8-54, pp. 9-33-9-55.
`IEEE Inc. New York, US, vol.18, No. 3, May 1, 1998, pp. 8-15,
`XP000755752 ISSN: 0272-1732, p. 12.
`Japanese Office Action dated Jun. 25, 2010 (translation provided).
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`6.298,370 B1 * 10/2001 Tang et al. .................... T18, 102
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`36 R ck $398 Shy
`OOll, JT. . . . . . . . . . . . . . . . . . . . . . .
`I
`-
`6,972,790 B2 * 12/2005 Suska ........................ 348.222.1
`2002/0101528 A1
`8, 2002 Lee et al.
`2002/019 1090 A1 12, 2002 Safai
`2004/OOO4664 A1
`1/2004 Safai
`
`6,833,862 B1* 12/2004 Li .
`
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`
`. 348.20799
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 4 of 19 PageID #: 107
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`U.S. Patent
`
`Sep. 17, 2013
`
`Sheet 1 of 8
`
`US 8,537,242 B2
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`1 O
`
`CPU
`
`16
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`17
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`
`FIGURE 1
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 5 of 19 PageID #: 108
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 2 of 8
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`US 8,537,242 B2
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`
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`13
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`FIGURE 2
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 6 of 19 PageID #: 109
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 3 of 8
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`US 8,537,242 B2
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`D.
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`
`ARRAY OF PXELS
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 7 of 19 PageID #: 110
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 4 of 8
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`US 8,537,242 B2
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`22 N
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`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 8 of 19 PageID #: 111
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 5 of 8
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`US 8,537,242 B2
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`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 9 of 19 PageID #: 112
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 6 of 8
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`US 8,537,242 B2
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`
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`ARBITRATION
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`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 10 of 19 PageID #: 113
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`U.S. Patent
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`Sep. 17, 2013
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`Sheet 7 of 8
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`US 8,537,242 B2
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`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 11 of 19 PageID #: 114
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`Sheet 8 of 8
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`US 8,537,242 B2
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`12
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`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 12 of 19 PageID #: 115
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`US 8,537,242 B2
`
`1.
`HOST INTERFACE FOR MAGING ARRAYS
`
`This application is a divisional of U.S. application Ser. No.
`09/742,723, filed Dec. 21, 2000, now U.S. Pat. No. 6,972,790,
`which claims the benefit of U.S. Provisional Application No.
`60/177,496, filed Jan. 21, 2000.
`
`FIELD OF THE INVENTION
`
`The invention relates generally to integrated electronic
`10
`image sensing circuitry and more particularly to CMOS
`imaging circuitry.
`
`BACKGROUND OF THE INVENTION
`
`2
`generator, and for transferring the data to a processor System.
`The interface comprises a memory for storing the imaging
`array data and the clocking signals at a rate determined by the
`clocking signals. In response to the quantity of data in the
`memory, a signal generator generates a signal for transmis
`sion to the processor System and a circuit controls the transfer
`of the data from the memory at a rate determined by the
`processor System. The memory may be a first-in first-out
`(FIFO) buffer or an addressable memory.
`The signal generator may generate an interrupt signal for
`transmission to the processor system or a bus request signal
`for transmission to a bus arbitration unit for the processor
`system. The circuit for controlling the transfer of the data may
`include a command decoder for receiving address and com
`mand signals from the processor system, a configuration reg
`ister for storing configuration data for the FIFO buffer and a
`read control for controlling the read-out of the FIFO buffer,
`and may further include a bus command unit for receiving
`control of the system bus and providing an address for the data
`read-out from the memory.
`In accordance with another aspect of this invention, an
`integrated semiconductor imaging circuit for use with an
`electronic processing system having a data bus comprises an
`imaging array sensor having an array of sensing pixels and an
`array address generator integrated on a die and an interface
`integrated on the same die. The interface is adapted to receive
`data from the imaging array sensor as determined by the
`imaging array and to transfer the data to the electronic pro
`cessing system as determined by the electronic processing
`system. The interface may include a memory such as a FIFO
`buffer or an addressable memory for storing imaging array
`data and address signals at a rate determined by the imaging
`array sensor, and a circuit for controlling the transfer of the
`data from the memory means to the data bus at a rate deter
`mined by the electronic processing system. The imaging cir
`cuit may further include a bus arbitration circuit integrated on
`the same die and coupled to the circuit for controlling the
`transfer of the data.
`In accordance with a further aspect of this invention, an
`integrated semiconductor imaging circuit for use with an
`electronic processing system having a data bus may comprise
`an imaging array of sensing pixels, a buffer for storing data
`received at an input port and for outputting data through an
`output port to the data bus, a circuit for transferring data from
`a selected pixel to the buffer input port, a circuit for determin
`ing the quantity of data in the buffer, a circuit for alerting the
`electronic processing system when the quantity of data in the
`buffer attains a predetermined level and a controller adapted
`to respond to the electronic processing system for controlling
`the transfer of the stored data through the buffer output port.
`In accordance with another aspect of this invention, an
`integrated semiconductor imaging circuit for use with an
`electronic processing system having a data bus and a system
`address/control bus, may comprise an imaging array of sens
`ing pixels, a buffer for storing data received at an input port
`and for outputting data through an output port to the data bus,
`a circuit for transferring data from a selected pixel to the
`buffer input port, a circuit for determining the quantity of data
`in the buffer, a controller for seeking control of the data bus
`when the quantity of data in the buffer attains a predetermined
`leveland adapted to respond to the availability of the data bus
`for controlling the transfer of the stored data through the
`buffer output port. The integrated semiconductor imaging
`circuit may further include a bus arbitration unit for receiving
`data bus control requests and for providing data bus control in
`response to a request, and the controller for receiving bus
`control comprising a register for storing and incrementing
`
`15
`
`Integrated circuit (IC) technology, applied to imaging, is
`revolutionizing that field. Semiconductors can be used to
`represent an image as an electrical signal. Charge coupled
`devices (CCDs) are the most significant commercial IC tech
`nology to date. However, when compared with CMOS tech
`nology, there are many advantages to producing CMOS
`image devices.
`CMOS is a less expensive technology; CMOS employs
`fewer mask layers and is a more mature fabrication technol
`ogy with greater commercial Volume. CCD technology com
`plexity causes lower fabrication yield. One of the main ben
`25
`efits of employing CMOS technology, compared to CCD, is
`the ability to include image-processing elements on the same
`Substrate as the imaging circuitry.
`On a monolithic semiconductor IC, with a surface coinci
`dent to an optical focal plane, photosensitive elements are
`employed in pixels that are arranged in an array of rows and
`columns. The basis for the pixels of CMOS technology is a
`photosensitive diode. In an active pixel arrangement each
`pixel photodiode is buffered from the shared readout compo
`nents by an amplification stage.
`IC image sensors of existing technologies provide video
`style output. In one example, such a sensor receives master
`clock input. The sensor derives data sample, line, and clocks
`from this master clock. These clocks, which correspond to
`pixel, row, and column, control the sampling rate of the imag
`ing array. The pixel data of Such a sensor is output at the same
`rate as it is sampled. The derived clocks are output as well to
`synchronize the data output. The result is a stream of synchro
`nized pixel intensities comprising a video frame.
`This output is incompatible with the data interface of com
`mercial microprocessors, without the use of additional glue
`45
`logic. A commercial microprocessor data interface consists of
`address and control output signals and data input/output sig
`nals. This configuration allows the processor to randomly
`access any word of data in memory by asserting various
`addresses.
`In an image acquiring computer system based on Such a
`sensor and Such a processor, additional interface circuitry to
`respond to the sensor clock outputs to sample the video infor
`mation, and to make this video data available in the memory
`space of the processor. Optionally, this interface circuit may
`include interrupt signals to the processor, and enough
`memory space for a number of pixels.
`Such additional circuitry diminishes the benefit of a single
`Substrate that integrates sensor and processing elements. The
`CMOS technology optimum cost benefit is not reached.
`Therefore, there is a need for an interface which may be
`integrated with the imaging array which a system processor
`can access to directly receive imaging data.
`
`30
`
`35
`
`40
`
`50
`
`55
`
`60
`
`SUMMARY OF THE INVENTION
`
`This invention is directed to an interface for receiving data
`from an image sensor having an imaging array and a clock
`
`65
`
`

`

`Case 2:20-cv-00234-JRG Document 1-5 Filed 07/13/20 Page 13 of 19 PageID #: 116
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`US 8,537,242 B2
`
`4
`and system components 11, an imaging array sensor 12, an
`interface 13 in accordance with the present invention and a
`video clock generator 14. The CPU 10, components 11 and
`interface 13 all have access to a system data bus 15 and are
`controlled by the CPU 11 via the system control and address
`bus 16. The clock generator 14 provides pixel clock signals
`C. to the imaging array sensor 12. The interface 13 is further
`connected to the CPU 10 through an interrupt bus 17 by which
`the CPU 10 is signalled that data is available for it to upload.
`In accordance with the present invention, the interface 13
`stores data and clocking signals from the imaging array sen
`sor 12 in order to free up the CPU 10 for other processing. In
`addition, the full economic and commercial advantage of
`CMOS technology may begained by integrating the interface
`13 on the same die as the imaging array sensor 12.
`An embodiment of the interface 13 is illustrated as a block
`diagram in FIG. 2. The imaging array sensor 12 includes an
`imaging array 21 which is an array of active photosensitive
`pixels with access control as will be described further with
`reference to FIG. 3. The imaging array 21 further includes an
`array address generator 22 which generates the column
`addresses A, the row addresses A, the row clock C and the
`frame clock C as will be described further with reference to
`FIG. 4.
`Referring to FIG. 3, the array 30 of pixels 33 is organized
`in rows 31 and columns 32. Each pixel 33 is located at the
`intersection of a row 31 and a column 32. The row control
`lines 34 provide access to a row 31 of pixels 33. The row line
`34 is driven by the row drivers 35 in response to the row
`address signal A. Each selected pixel 33 asserts data onto its
`own column data line 36 when accessed. The data onlines 36
`is amplified by column amplifiers and second stage amplifi
`cation in unit 37. Unit 37 further selects the column 32 as
`determined by column address A, from which array data D,
`is placed on the array output 38.
`Referring to FIG. 4, the array address generator 22 is
`shown in greater detail. The column address A is generated
`by a column counter 41 which is incremented by the video
`system clock C. The maximum number of sequential
`addresses generated by the column counter 41 will depend on
`the number of columns in the imaging array 21, however the
`actual number of sequential addresses generated by the col
`umn counter 41 will be determined by the column boundary
`signal B, which is controlled by the CPU 10 as will be
`described later. The row clock C is generated by the overflow
`of the column counter 41. The row counter 42 generates the
`row address signal A based on the row clock signal C and
`the row boundary signal B. The maximum number of
`sequential addresses generated by the row counter 42 will
`depend on the number of rows in the imaging array 21, how
`ever the actual number of sequential addresses generated by
`the row counter 42 will be determined by the row boundary
`signal B which is controlled by the CPU 10 as will be
`described later. The row clock C is also applied to an output
`43 from the array address generator 22. The row counter 42
`also generates a frame signal C based on count overflow.
`Referring again to FIG. 2, the interface 13 includes a
`memory 44 as well as devices 45 to 49 required to support the
`memory 44. In this particular embodiment, memory 44 is a
`first-in first-out (FIFO) buffer memory. FIFO buffer 44
`receives array data D. from the imaging array, clocking sig
`nals C. from the video clock generator 14 and clocking sig
`nals C and C from the array address generator 22. FIFO
`buffer 44 is shown in greater detail in FIG. 5. The imaging
`array 21 output D, row clock C and frame clock C. are
`bundled onto a single bus 51 for storage in the buffer 44. The
`storage components of the FIFO buffer 44 are registers 52
`
`3
`destination addresses, and a circuit for asserting the destina
`tion address and write controls on the system address/control
`bus.
`In accordance with a further aspect of this invention, an
`integrated semiconductor imaging circuit for use with an
`electronic processing system having a data bus, may com
`prise an imaging array of sensing pixels, an addressable
`memory having a plurality of memory cells arranged in rows
`and columns for storing data received at an input port and for
`outputting data throughan output port to the data bus, a circuit
`for transferring data from a selected pixel to a selected
`memory cell through the memory input port, a circuit for
`determining the quantity of data in the memory, a circuit for
`alerting the electronic processing system when the quantity of
`data in the memory attains a predetermined level, and a con
`troller adapted to respond to the electronic processing system
`for controlling the transfer of the stored data through the
`memory output port.
`In accordance with another aspect of this invention, an
`integrated semiconductor imaging circuit for use with an
`electronic processing system having a data bus and a system
`address/control bus, may comprise an imaging array of sens
`ing pixels, an addressable memory having a plurality of
`memory cells arranged in rows and columns for storing data
`received at an input port and for outputting data through an
`output port to the data bus, a circuit for transferring data from
`a selected pixel to a selected memory cell through the
`memory input port, a circuit for determining the quantity of
`data in the memory, and a controller for seeking control of the
`data bus when the quantity of data in the memory attains a
`predetermined level and adapted to respond to the availability
`of the data bus for controlling the transfer of the stored data
`through the memory output port. The integrated semiconduc
`tor imaging circuit may further include a bus arbitration unit
`for receiving data bus control requests and for providing data
`bus control in response to a request, and the controller for
`receiving bus control comprising a register for storing and
`incrementing destination addresses, and a circuit for asserting
`the destination address and write controls on the system
`address/control bus.
`Other aspects and advantages of the invention, as well as
`the structure and operation of various embodiments of the
`invention, will become apparent to those ordinarily skilled in
`the art upon review of the following description of the inven
`tion in conjunction with the accompanying drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The invention will be described with reference to the
`accompanying drawings, wherein:
`FIG. 1 is a block diagram of a computer system utilizing
`the imaging array sensor,
`FIG. 2 is a block diagram of an imaging array sensor
`including the interface of the present invention;
`FIG. 3 is a block diagram of the pixel imaging array and
`acceSS,
`FIG. 4 is a block diagram of the video clock and array
`address generator;
`FIG. 5 is a block diagram of a FIFO buffer;
`FIG. 6 is a block diagram of a computer system with bus
`arbitration utilizing the imaging array sensor,
`FIG. 7 is a block diagram of an imaging array sensor that
`includes an interface having bus arbitration circuitry; and
`FIG. 8 is a block diagram of an imaging array sensor that
`includes an interface having an addressable memory.
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`DETAILED DESCRIPTION OF THE INVENTION
`
`The imaging computer system illustrated in FIG. 1
`includes a central processing unit (CPU) 10, other memory
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`interrupt signal S, as an interrupt to the CPU 10 allows the
`processor to multi-task. It performs a buffer 44 unload opera
`tion when the interrupt is asserted, and carries out other
`programmed tasks at all other times.
`Access to the array registers 49 is controlled by the array
`register command bus, 58. Data is exchanged with the system
`data bus 15. The content of the registers 49 defines the number
`of rows and columns to be employed in the imaging array 21.
`This information is communicated to the array address gen
`erator 22 by the row and column boundary signals B and B.
`The above interface 13 signals the CPU 10 through the
`interrupt signal S, when it has an amount of data approaching
`the limits of its storage capacity. The CPU then responds by
`having the data downloaded onto the system bus 15. It is
`important for the CPU to respond to the interface faster then
`the imaging array 21 can generate data. In addition, the size of
`the FIFO buffer 44 will also depend on the latency of the CPU
`10, since during the period of time required by the CPU 10 to
`respond to the interrupt signal S, data is being stored in the
`buffer 44. The faster that the CPU 10 is able to respond to the
`interrupt and accept the downloaded data, the Smaller the
`buffer 44 can be and the less space that it will require if
`integrated on the die with the imaging array 21. However, in
`real time control applications, it is important that the interface
`13 and the CPU 10 be matched so that the data from all frames
`scanned by the imaging array 21 is properly and completely
`transferred to the CPU 10. This requirement may be relaxed
`Somewhat for camera type applications where the necessity of
`capturing all frames is not required.
`In a further embodiment of the present invention as illus
`trated in FIG. 6, the interface 73 would interact with the CPU
`10 and other system components through a bus arbitration
`unit 61. Rather then send an interrupt signal S, to the CPU 10,
`the interface 73 sends a bus request signal S to the bus
`arbitration unit 61 and receives an arbitration acknowledge
`ment signal S when the bus 15 is available to it for down
`loading data. As illustrated in FIG. 6, the other units, CPU 10
`and components 11 in the system have their own arbitration
`request lines 62 and arbitration acknowledgement lines 63.
`The Bus Arbitration Unit 61 receives all the requests for the
`bus 15 and selects one unit that is acknowledged as the current
`bus master.
`The required components in the interface 73 that are
`required in order for it to be compatible with a bus arbitration
`system are shown in FIG. 7. A Bus Request Generator 64
`functions in the same manner as the Interrupt Generator 48
`shown in FIG. 2. A bus request signal S is generated in the
`same manner as the interrupt S. If S-2S and the bus request
`enable signal S is valid, the generator 64 asserts the bus
`request signal S to the bus arbitration unit 61.
`An arbitration acknowledge signal S. notifies the inter
`face 73 that the interface 73 may assert command of the bus
`15. The arbitration acknowledge signal S is applied to the
`chip command decoder 45 and a bus command unit 65. The
`arbitration acknowledge signal S. deactivates the command
`decoder 45 for the duration that the interface controls the bus
`15. On receiving the arbitration acknowledge signal S, the
`bus command unit 65 will activate an output address unit 66
`via the request output address signal S and receive from it
`the next address on the output address signal S. This
`address is sent out onto the system address and control line
`16. At the same time the bus command unit 65 asserts the
`necessary read or write signal on the FIFO read control 47 line
`67.
`The address may represent a location in the CPU 10, how
`ever, one advantage of this arrangement is that the address
`may be to a location in one of the system components 11 Such
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`arranged as a shift register series 53. Since the total number of
`valid outputs may vary due to the differing rates of storage
`and access, the bus 51 is connected to each register 52. An
`increment/decrement counter 54 is used to count the occur
`rences of FIFO buffer 44 writes and FIFO buffer 44 reads.
`Counter 54 has access to the pixel clock C. and a FIFO read
`signal S. The FIFO counter 54 outputS is applied to buffer
`output 55 and to the Register address decoder 56. The decoder
`uses the counter output S, and pixel clock C in determining
`when to assert the appropriate register write signal on lines
`57. The read signal S is connected to the shift registers 52 to
`shift the registers by a number of registers depending on the
`read signal S value. The same number of registers, from the
`end of the buffer, asserts data D, on the system data bus 15
`during this operation.
`There are basically three types of FIFO buffers, each of
`which may be used with the present invention. The first type
`of buffer 44 is the one shown in FIG. 5 where stored data is
`removed from buffer register series 53 from the first register
`52 on the right hand end and data from the bus 51 is written
`into the last available shift register 52 from the left end of the
`buffer register series 53. A second type of buffer is one where
`the data is written into the first register on the left hand end of
`the buffer register series and data is taken out of the buffer
`register series from the first register with data in the series
`looking at it from the right end of the register series. The third
`type of buffer is one in which data from the data bus is written
`into the last available shift registerlooking from the left end of
`the buffer register series and data is taken out of the buffer
`register series from the first register with data in the series
`looking at it from the right end of the register series. In all
`three cases, data is removed from the buffer in the same
`sequence that it is entered into the buffer.
`Referring again to FIG. 2, the interface 13 includes devices
`45 to 49 to support the FIFO buffer 44. The devices include a
`Chip Command Decoder 45, FIFO Configuration Registers
`46, FIFO Read Control 47, an Interrupt Generator 48 and
`Array Registers 49.
`The CPU 10 accesses the registers 46 and 49 and FIFO
`buffer 44 through the Chip Command Decoder 45 by assert
`ing the necessary read or write commands, along with the
`address on the system address and command bus 16. The
`command decoder 45 identifies any buffer or register being
`addressed and asserts the necessary read or write signal on the
`FIFO read control 47 line 56, the FIFO configuration register
`46 command bus 57, or the array register 49 command bus 58.
`The signal on line 56 permits the FIFO read control 47 to
`generate a FIFO read signal S in response to the output bus
`width signal S. Variation of the FIFO 44 output bus width
`register provides compatibility with a variety of system bus
`configurations such as 8-bit or 32-bit.
`The FIFO configuration registers 46 include the FIFO out
`put bus width, the FIFO limit value, the FIFO interrupt mask,
`and the FIFO interrupt register. All of these registers are
`connected to the system data bus 15 and are read/write
`capable, except the FIFO interrupt register, which is read only
`and determines its value from the interrupt generator as signal
`S. The reading and writing of these registers is controlled by
`the FIFO register command bus 57. The output of the FIFO
`configuration registers include FIFO limit signal S, from the
`FIFO limit register, the interrupt enable signal S from the
`FIFO interrupt mask, and the output bus width signal St.
`from the FIFO output bus width register.
`The interrupt generator 48 compares the FIFO counter
`output S, and the FIFO limit St. If S-2S and if the interrupt
`enable signal S is valid, the generator 48 asserts the interrupt
`signal S, to the CPU 10 via the interrupt bus 17. The use of an
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`transferring image data from the FIFO memory to the
`processor in response to the interrupt signal.
`2. The method of claim 1, further comprising:
`generating a FIFO limit signal, the interrupt enable signal,
`and an output bus width signal.
`3. The method of claim 1, wherein said transferring image
`data comprises transferring image data from the FIFO
`memory to the processor in response to receiving a command
`from the processor.
`4. The method of claim 1, further comprising:
`storing the image data in the FIFO memory at a first rate
`based on clocking signals associated with the image
`array; and
`transferring the image data from the FIFO memory at a
`second rate that is faster than the first rate.
`5. The method of claim 1, further comprising:
`storing the image data in the FIFO memory at a first rate
`associated with the image array; and
`transferring the image data from the FIFO memory to the
`processor at a second rate associated with the processor.
`6. The method of cl