Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 1 of 31 PageID #: 151
`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 1 of 31 PageID #: 151
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`EXHIBIT E
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`EXHIBIT E
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`

`

`(12) United States Patent
`Choo et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,080,330 B1
`Jul.18, 2006
`
`US00708033 OB1
`
`(*) Notice:
`
`(54) CONCURRENT MEASUREMENT OF
`CRITICAL DIMIENSION AND OVERLAY IN
`SEMCONDUCTOR MANUFACTURING
`(75) Inventors: Bryan Choo, Mountain View, CA (US);
`Bharath Rangarajan, Santa Clara, CA
`(US); Bhanwar Singh, Morgan Hill,
`CA (US); Carmen Morales, San Jose,
`CA (US)
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 433 days.
`(21) Appl. No.: 10/379,738
`(22) Filed:
`Mar. 5, 2003
`(51) Int. Cl.
`(2006.01)
`G06F 7/50
`(52) U.S. Cl. ............................... 71614, 71619, 71621
`(58) Field of Classification Search
`s
`s 71.6/4
`- - - - - - - - - -716/19 2O 2
`See application file for complete search history s
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`5,042,009 A *
`
`8, 1991 KaZerounian et al. .. 365,185.18
`
`6,650,424 B1 * 1 1/2003 Brill et al. .................. 356,601
`2002/0018217 A1
`2/2002 Weber-Grabau et al. .... 356,601
`2002/0158193 A1* 10/2002 Sezginer et al. ........ 250,237 G
`OTHER PUBLICATIONS
`Kynett et al..." A in-system reprogrammable 32 Kx8 CMOS
`Flash Memory”, Oct. 1988, IEEE Jpurnal of Solid-State
`Circuits, vol. 23, iss. 5, pp. 1157-1163.*
`* cited by examiner
`Primary Examiner Sun James Lin
`(74) Attorney, Agent, or Firm—Amin & Turocy, LLP
`(57)
`ABSTRACT
`
`A SV Stem and methodology are disclosed for monitoring and
`Ring a E. fabrication process. O. O
`more structures formed on a wafer matriculating through the
`process facilitate concurrent measurement of critical dimen
`sions and overlay via scatterometry or a scanning electron
`microscope (SEM). The concurrent measurements mitigate
`fabrication inefliciencies, thereby reducing time and real
`estate required for the fabrication process. The measure
`ments can be utilized to generate feedback and/or feed
`forward data to selectively control one or more fabrication
`components and/or operating parameters associated there
`with to achieve desired critical dimensions and to mitigate
`overlay error.
`
`25 Claims, 18 Drawing Sheets
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 2 of 31 PageID #: 152
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`STAR
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`A1 1400
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`GNERAINITIAIZATIONS
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`GENERATEGRID MAP
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`402
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`1404
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`FORMSTRUCTUREAT GRD
`MAPPELOCATIONS
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`/ 1406
`
`MEASURE CRITICAL DIMENSIONS
`AND OVERLAY CONCURRENTLY
`
`ALL GRD BLOCKS
`MeASURED
`
`
`
`YES
`
`COMPAREMEASUREMENTSTO
`ACCEPTABLEVALUES
`
`142
`
`
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`
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`
`
`O
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`420
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`ADJUSPRFED FORWARD
`
`y
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`1422
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`PROCEEASNORMA
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`ADJUST PERFEEDBACK
`
`

`

`U.S. Patent
`
`Jul.18, 2006
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`Sheet 1 of 18
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`US 7,080,330 B1
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`WE_LSÅS
`TlO?H_LNO O
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 3 of 31 PageID #: 153
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 4 of 31 PageID #: 154
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`U.S. Patent
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`Jul. 18 2006
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`Sheet 2 of 18
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`

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`U.S. Patent
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`Jul.18, 2006
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`Sheet 3 of 18
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`US 7,080,330 B1
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`
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`(Y)
`O
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 5 of 31 PageID #: 155
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`

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`U.S. Patent
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`Jul.18, 2006
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`Sheet 4 of 18
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`U.S. Patent
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`Jul.18, 2006
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`Sheet S of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 7 of 31 PageID #: 157
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 8 of 31 PageID #: 158
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 7 of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 9 of 31 PageID #: 159
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`U.S. Patent
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 10 of 31 PageID #: 160
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`U.S. Patent
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 11 of 31 PageID #: 161
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 12 of 31 PageID #: 162
`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 12 of 31 PageID #: 162
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`U.S. Patent
`
`Jul. 18, 2006
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`Sheet 10 of 18
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`US 7,080,330 B1
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`U.S. Patent
`
`Jul.18, 2006
`
`Sheet 11 of 18
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`US 7,080,330 B1
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`START
`
`1400
`A?
`
`GENERAL INITIALIZATIONS
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`GENERATE GRID MAP
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`FORMSTRUCTURE AT GRID
`MAPPED LOCATIONS
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`1402
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`1404
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`1406
`
`MEASURE CRITICAL DIMENSIONS
`AND OVERLAY CONCURRENTLY
`
`1410
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`ALL GRD BLOCKS
`MEASURED7
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`YES
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`COMPARE MEASUREMENTS TO
`ACCEPTABLE VALUES
`
`1412
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 13 of 31 PageID #: 163
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`1422
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`1418
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`Fig. 14
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`

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`U.S. Patent
`
`Jul. 18, 2006
`
`Sheet 12 of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 14 of 31 PageID #: 164
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`SURFACE
`NORMAL
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`SPECULARLY
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`REFLECTED EED Fig. 15
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`MICROPROCESSOR
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`

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`U.S. Patent
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`Jul.18, 2006
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`Sheet 13 of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 15 of 31 PageID #: 165
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 14 of 18
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 16 of 31 PageID #: 166
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 15 of 18
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`US 7,080,330 B1
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 16 of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 18 of 31 PageID #: 168
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 17 of 18
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`US 7,080,330 B1
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 19 of 31 PageID #: 169
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`U.S. Patent
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`Jul.18, 2006
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`Sheet 18 of 18
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`US 7,080,330 B1
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`Measured Tan Psi signal
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 20 of 31 PageID #: 170
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`

`

`US 7,080,330 B1
`
`1.
`CONCURRENT MEASUREMENT OF
`CRITICAL DIMIENSION AND OVERLAY IN
`SEMCONDUCTOR MANUFACTURING
`
`TECHNICAL FIELD
`
`The present invention generally relates to monitoring
`and/or controlling a semiconductor fabrication process, and
`in particular to a system and methodology for concurrently
`measuring critical dimensions and overlay during the fab
`rication process and controlling operating parameters to
`refine the process in response to the measurements.
`
`BACKGROUND
`
`In the semiconductor industry, there is a continuing trend
`toward higher device densities. To achieve these high den
`sities, there has been and continues to be efforts toward
`Scaling down device dimensions (e.g., at Submicron levels)
`on semiconductor wafers. In order to accomplish Such high
`device packing density, Smaller and Smaller feature sizes are
`required in integrated circuits (ICs) fabricated on Small
`rectangular portions of the wafer, commonly known as dies.
`This may include the width and spacing of interconnecting
`lines, spacing and diameter of contact holes, the Surface
`geometry Such as corners and edges of various features as
`well as the surface geometry of other features. To scale down
`device dimensions, more precise control of fabrication pro
`cesses are required. The dimensions of and between features
`can be referred to as critical dimensions (CDs). Reducing
`CDs, and reproducing more accurate CDS facilitates achiev
`ing higher device densities through scaled down device
`dimensions and increased packing densities.
`The process of manufacturing semiconductors or ICs
`typically includes numerous steps (e.g., exposing, baking,
`developing), during which hundreds of copies of an inte
`grated circuit may be formed on a single wafer, and more
`particularly on each die of a wafer. In many of these steps,
`material is overlayed or removed from existing layers at
`specific locations to form desired elements of the integrated
`circuit. Generally, the manufacturing process involves cre
`ating several patterned layers on and into a Substrate that
`ultimately forms the complete integrated circuit. This lay
`ering process creates electrically active regions in and on the
`semiconductor wafer Surface. The layer to layer alignment
`and isolation of Such electrically active regions depends, at
`least in part, on the precision with which features can be
`placed on a wafer. If the layers are not aligned within
`acceptable tolerances, overlay errors can occur compromis
`ing the performance of the electrically active regions and
`adversely affecting chip reliability.
`
`2
`etry or a scanning electron microscope (SEM). The concur
`rent measurements mitigate fabrication inefficiencies as two
`operations are combined into one. The combined measure
`ments facilitate a reduction in, among other things, time and
`real estate required for the fabrication process. The mea
`Surements can be utilized to generate control data that can be
`fed forward and/or backward to selectively adjust one or
`more fabrication components and/or operating parameters
`associated therewith to bring critical dimensions within
`acceptable tolerances and to mitigate overlay errors.
`To the accomplishment of the foregoing and related ends,
`certain illustrative aspects of the invention are described
`herein in connection with the following description and the
`annexed drawings. These aspects are indicative, however, of
`but a few of the various ways in which one or more of the
`principles of the invention may be employed and the present
`invention is intended to include all Such aspects and their
`equivalents. Other advantages and novel features of the
`invention will become apparent from the following detailed
`description of the invention when considered in conjunction
`with the drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram Schematically illustrating at a
`high level a system for monitoring and controlling a semi
`conductor fabrication process in accordance with one or
`more aspects of the present invention.
`FIG. 2 is a cross sectional side view of a structure in
`accordance with one or more aspects of the present inven
`tion that facilitates concurrent measurement of critical
`dimensions and overlay with scatterometry.
`FIG. 3 is a top view of a structure, such as that depicted
`in FIG. 2, that can be utilized to concurrently measure
`critical dimensions and overlay with scatterometry.
`FIG. 4 is a cross sectional side view of a structure in
`accordance with one or more aspects of the present inven
`tion that facilitates concurrent measurement of critical
`dimensions and overlay with a scanning electron microscope
`(SEM).
`FIG. 5 is a top view of a structure, such as that depicted
`in FIG. 4, that can be utilized to concurrently measure
`critical dimensions and overlay with SEM.
`FIG. 6 is a cross sectional side view of an alternative
`structure that facilitates concurrent measurement of critical
`dimensions and overlay with SEM.
`FIG. 7 illustrates a portion of a system for monitoring a
`semiconductor fabrication process with scatterometry
`according to one or more aspects of the present invention.
`FIG. 8 illustrates a system for monitoring and controlling
`a semiconductor fabrication process according to one or
`more aspects of the present invention.
`FIG. 9 illustrates a portion of a system for monitoring a
`semiconductor fabrication process with SEM according to
`one or more aspects of the present invention.
`FIG. 10 illustrates another system for monitoring and
`controlling a semiconductor fabrication process according to
`one or more aspects of the present invention.
`FIG. 11 illustrates a perspective view of a grid mapped
`wafer according to one or more aspects of the present
`invention.
`FIG. 12 illustrates plots of measurements taken at grid
`mapped locations on a wafer in accordance with one or more
`aspects of the present invention.
`
`10
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`15
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`Case 4:20-cv-00991 Document 1-5 Filed 12/31/20 Page 21 of 31 PageID #: 171
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`SUMMARY OF THE INVENTION
`
`The following presents a simplified summary of the
`invention in order to provide a basic understanding of some
`aspects of the invention. This Summary is not an extensive
`overview of the invention. It is intended to neither identify
`key or critical elements of the invention nor delineate the
`Scope of the invention. Its purpose is merely to present some
`concepts of the invention in a simplified form as a prelude
`to the more detailed description that is presented later.
`According to one or more aspects of the present invention,
`one or more structures formed on a wafer matriculating
`through a semiconductor fabrication process facilitate con
`current measurement of overlay and one or more critical
`dimensions in the fabrication process with either scatterom
`
`

`

`US 7,080,330 B1
`
`10
`
`15
`
`3
`FIG. 13 illustrates a table containing entries correspond
`ing to measurements taken at respective at grid mapped
`locations on a wafer in accordance with one or more aspects
`of the present invention.
`FIG. 14 is flow diagram illustrating a methodology for 5
`monitoring and controlling an IC fabrication process accord
`ing to one or more aspects of the present invention.
`FIG. 15 illustrates an exemplary scatterometry system
`suitable for implementation with one or more aspects of the
`present invention.
`FIG. 16 is a simplified perspective view of an incident
`light reflecting off a surface in accordance with one or more
`aspects of the present invention.
`FIG. 17 is another simplified perspective view of an
`incident light reflecting off a Surface in accordance with one
`or more aspects of the present invention.
`FIG. 18 illustrates a complex reflected and refracted light
`produced when an incident light is directed onto a surface in
`accordance with one or more aspects of the present inven
`tion.
`FIG. 19 illustrates another complex reflected and
`refracted light produced when an incident light is directed
`onto a Surface in accordance with one or more aspects of the
`present invention.
`FIG. 20 illustrates yet another complex reflected and
`refracted light produced when an incident light is directed
`onto a Surface in accordance with one or more aspects of the
`present invention.
`FIG. 21 illustrates phase and/or intensity signals recorded so
`from a complex reflected and refracted light produced when
`an incident light is directed onto a surface in accordance
`with one or more aspects of the present invention.
`
`4
`FIG. 1 illustrates a system 100 for monitoring and con
`trolling an integrated circuit (IC) fabrication process accord
`ing to one or more aspects of the present invention. The
`system 100 includes a control system 102, fabrication com
`ponents 104 of the process, a measurement system 106 and
`a wafer 108 undergoing the fabrication process. The wafer
`108 has one or more structures 110 formed therein according
`to one or more aspects of the present invention. The control
`system 102 is operatively coupled to the measurement
`system 106 and the fabrication components 104 and selec
`tively controls of the fabrication components 104 and/or one
`or more operating parameters associated therewith (e.g., via
`feed forward and/or feedback) based upon readings taken by
`the measurement system 106. The measurement system 106
`includes either a scatterometry system or a scanning electron
`microscope (SEM) system (not shown) which interacts with
`the structure 110 to concurrently measure critical dimen
`sions and overlay. These concurrent measurements can be
`utilized to monitor and control the fabrication process while
`mitigating the amount of test equipment, real estate and time
`required for the fabrication process. The measurements can,
`in particular, be utilized for generating feedback and/or
`feed-forward data for mitigating overlay and/or bringing
`critical dimensions within acceptable tolerances.
`It is to be appreciated that any of a variety of fabrication
`components and/or operating parameters associated there
`with can be selectively controlled based upon the readings
`taken by the measurement system 106. By way of example
`and not limitation, this can include, but is not limited to,
`temperatures associated with the process, pressures associ
`ated with the process, concentration of gases and chemicals
`within the process, composition of gases, chemicals and/or
`other ingredients within the process, flow rates of gases,
`chemicals and/or other ingredients within the process, tim
`ing parameters associated with the process and excitation
`voltages associated with the process. By way of further
`example, parameters associated with high-resolution photo
`lithographic components utilized to develop ICs with small
`closely spaced apart features can be controlled to mitigate
`overlay errors and achieve desired critical dimensions. In
`general, lithography refers to processes for pattern transfer
`between various media and in semiconductor fabrication, a
`silicon slice, the wafer, is coated uniformly with a radiation
`sensitive film, the photoresist. The photoresist coated sub
`strate is baked to evaporate any solvent in the photoresist
`composition and to fix the photoresist coating onto the
`Substrate. An exposing source (such as light, X-rays, or an
`electron beam) illuminates selected areas of the surface of
`the film through an intervening master template for a par
`ticular pattern. The lithographic coating is generally a radia
`tion-sensitized coating Suitable for receiving a projected
`image of the Subject pattern. Once the image from the
`intervening master template is projected onto the photore
`sist, it is indelibly formed therein.
`Light projected onto the photoresist layer during photo
`lithography changes properties (e.g., Solubility) of the layer
`such that different portions thereof (e.g., the illuminated or
`un-illuminated portions, depending upon the photoresist
`type) can be manipulated in Subsequent processing steps.
`For example, regions of a negative photoresist become
`insoluble when illuminated by an exposure source such that
`the application of a solvent to the photoresist during a
`Subsequent development stage removes only non-illumi
`nated regions of the photoresist. The pattern formed in the
`negative photoresist layer is, thus, the negative of the pattern
`defined by opaque regions of the template. By contrast, in a
`positive photoresist, illuminated regions of the photoresist
`
`25
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`35
`
`The present invention is now described with reference to
`the drawings, wherein like reference numerals are used to
`refer to like elements throughout. In the following descrip- 40
`tion, for purposes of explanation, numerous specific details
`are set forth in order to provide a thorough understanding of
`the present invention. It may be evident, however, to one
`skilled in the art that one or more aspects of the present
`invention may be practiced with a lesser degree of these 4s
`specific details. In other instances, well-known structures
`and devices are shown in block diagram form in order to
`facilitate describing one or more aspects of the present
`invention.
`The term “component as used herein includes computer- 50
`related entities, either hardware, a combination of hardware
`and software, software, or software in execution. For
`example, a component may be a process running on a
`processor, a processor, an object, an executable, a thread of
`execution, a program and a computer. By way of illustration, 55
`both an application running on a server and the server can be
`components. By way of further illustration, both a stepper
`and a process controlling the stepper can be components.
`It is to be appreciated that various aspects of the present
`invention may employ technologies associated with facili- 60
`tating unconstrained optimization and/or minimization of
`error costs. Thus, non-linear training systems/methodologies
`(e.g., back propagation, Bayesian, fuzzy sets, non-linear
`regression, or other neural networking paradigms including
`mixture of experts, cerebella model arithmetic computer 65
`(CMACS), radial basis functions, directed search networks
`and function link networks) may be employed.
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`etching stage wherein an etchant, as well as other ingredi
`ents, are applied to the surface of the wafer by an excitation
`Voltage or otherwise. The etchant removes or etches away
`portions of the wafer exposing during the development
`process. Portions of the wafer under less soluble areas of the
`photoresist are protected from the etchants. The less soluable
`portions of the photoresist are those portions that are not
`affected by the developer during the development process
`and that are not affected by the etchant during the etching
`process. These insoluble portions of the photoresist are
`removed in Subsequent processing stage(s) to completely
`reveal the wafer and the pattern(s) formed therein. The
`concentration of materials utilized in etching can thus be
`controlled to achieve desired critical dimensions and to
`mitigate overlay for instance by affecting the accuracy with
`which selected portions of the wafer are etched away.
`Parameters relating to the type of template utilized to
`transfer an image onto a wafer can also be controlled to
`affect critical dimensions, layer to layer alignment and
`overlay. Where the template is a reticle, the pattern is
`transferred to only one (or a few) die per exposure, as
`opposed to where the template is a mask and all (or most) die
`on the wafer are exposed at once. Multiple exposures
`through a reticle are often performed in a step and Scan
`fashion. After each exposure, a stage to which the wafer is
`mounted is moved or stepped to align the next die for
`exposure through the reticle and the process is repeated. This
`process may need to be performed as many times as there are
`die in the wafer. Thus, stepper movement can be controlled
`to mitigate overlay error (e.g., by feeding fed forward and/or
`backward measurements to a stepper motor). The pattern
`formed within the reticle is often an enlargement of the
`pattern to be transferred onto the wafer. This allows more
`detailed features to be designed within the reticle. Energy
`from light passed through the reticle can, however, heat the
`reticle when the image is exposed onto the wafer. This can
`cause mechanical distortions in the reticle due to thermal
`expansion and/or contraction of the reticle. Such distortions
`may alter the geometry of intricate features (e.g., by nar
`rowing a line) and/or interfere with layer to layer registration
`to Such a degree that a resulting circuit does not operate as
`planned when the image is transferred onto the wafer.
`Moreover, since the pattern is usually an enlargement of the
`pattern to be transferred onto the wafer, it typically has to be
`reduced (e.g., via a de-magnifying lens system) during the
`lithographic process. Shrinking an already distorted feature
`(e.g., a narrowed line) can have a deleterious effect on
`critical dimensions. Thus, while Such a template may be
`effective to transfer more intricate pattern designs, it calls for
`highly accurate alignment and imaging to mitigate overlay
`errors and maintain critical dimensions to within acceptable
`tolerances. Temperature controls can thus be employed to
`mitigate thermally induced mechanical distortions in the
`reticle.
`Additionally, parameters relating to film growth or depo
`sition components (e.g., producing metals, oxides, nitrides,
`poly, oxynitrides or insulators) can be controlled to achieve
`desired critical dimensions and mitigate overlay. Such films
`can be formed through thermal oxidation and nitridation of
`single crystal silicon and polysilicon, the formation of
`silicides by direct reaction of a deposited metal and the
`Substrate, chemical vapor deposition (CVD), physical vapor
`deposition (PVD), low pressure CVD (LPCVD), plasma
`enhanced CVD (PECVD), rapid thermal CVD (RTCVD),
`metal organic chemical vapor deposition (MOCVD) and
`pulsed laser deposition (PLD). The rates of flow, tempera
`ture, pressures, concentrations and species of materials
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`become soluble and are removed via application of a solvent
`during development. Thus, the pattern formed in the positive
`photoresist is a positive image of opaque regions on the
`template. Controlling the degree to which a photoresist is
`exposed to illumination (e.g., time, intensity) can thus affect
`the fidelity of pattern transfer and resulting critical dimen
`sions and overlay. For example, overexposure can create
`features that are too thin, resulting in spaces which are larger
`than desired, while underexposure can create features that
`are too wide, resulting in spaces which are Smaller than
`desired.
`The type of illumination utilized to transfer the image
`onto a wafer can also be controlled to affect critical dimen
`sions. For instance, as feature sizes are driven Smaller and
`Smaller, limits are approached due to the wavelengths of the
`optical radiation. As such, that type of radiation and thus the
`wavelengths of radiation utilized for pattern transfers can be
`controlled to adjust critical dimensions and mitigate overlay.
`For instance, radiation having more conducive wavelengths
`(e.g., extreme ultraviolet (EUV) and deep ultraviolet (DUV)
`radiation having wavelengths within the range of 5-200 nm)
`can be utilized for lithographic imaging in an effort to
`accurately achieve Smaller feature sizes. However, Such
`radiation can be highly absorbed by the photoresist material.
`Consequently, the penetration depth of the radiation into the
`photoresist can be limited. The limited penetration depth
`requires use of ultra-thin photoresists so that the radiation
`can penetrate the entire depth of the photoresist in order to
`effect patterning thereof. The performance of circuits formed
`through photolithographic processing is, thus, also affected
`30
`by the thickness of photoresist layers. The thickness of
`photoresist layers can be reduced through chemical
`mechanical polishing (CMP). In general, CMP employs
`planarization techniques wherein a Surface is processed by a
`polishing pad in the presence of an abrasive or non-abrasive
`liquid slurry. The slurry employed reacts with the photoresist
`at the surface/subsurface range. Preferably the degree of
`reaction is not great enough to cause rapid or measurable
`dissolution (e.g., chemical etching) of the photoresist, but
`merely sufficient to cause a minor modification of chemical
`bonding in the photoresist adequate to facilitate Surface layer
`removal by applied mechanical stress (e.g., via use of a CMP
`polishing pad). Thus, critical dimensions and overlay can be
`affected by controlling the concentration, rate of flow and
`degree of abrasiveness of slurry applied during the CMP
`45
`process as well as the amount of pressure applied between
`the polishing pad and water during the process.
`Depending upon the resist system utilized, post exposure
`baking may also be employed to activate chemical reactions
`in the photoresist to affect image transfer. The temperatures
`and/or times that portions of the wafer are exposed to
`particular temperatures can be controlled to regulate the
`uniformity of photoresist hardening (e.g., by reducing stand
`ing wave effects and/or to thermally catalyze chemical
`reactions that amplify the image). Higher temperatures can
`cause faster baking and faster hardening, while lower tem
`peratures can cause slower baking and correspondingly
`slower hardening. The rate and uniformity of photoresist
`hardening can affect critical dimensions and overlay, Such
`as, for example, by altering the consistency of a line width.
`Accordingly, time and temperature parameters can be con
`trolled during post exposure baking to affect critical dimen
`sions and overlay.
`Operating parameters of an etching stage can similarly be
`controlled to achieve desired critical dimensions and to
`mitigate overlay. After illumination, the pattern image is
`transferred into the wafer from the photoresist coating in an
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`Supplied during the semiconductor fabrication process can
`thus be controlled to govern film formation which bears on
`critical dimensions and overlay.
`Scatterometry or scanning electron microscope (SEM)
`techniques can be employed in accordance with one or more
`aspects of the present invention to concurrently measure
`critical dimensions and overlay at different points in an IC
`fabrication process to determine what effect, if any, the
`various processing components are having on the fabrication
`process. Different grating and/or feature heights and/or
`depths may, for example, be measured to generate different
`signatures that may be indicative of the effect that one or
`more processing components are having upon the fabrica
`tion process and which operating parameters of which
`processing components, if any, should thus be adjusted to
`rectify any undesirable processing. The processing compo
`nents and/or operating parameters thereof can be controlled
`based upon feedback/feed forward information generated
`from the measurements. For example, at a first point in time
`a first signature may be generated that indicates that desired
`critical dimensions have not yet been achieved but are
`developing within acceptable tolerances, but that an overlay
`error is occurring. Thus, the process may be adapted in an
`attempt to mitigate overlay error, but not affect developing
`critical dimensions. Then, at a second point in time a second
`signature may be generated that indicates that an overlay
`error is no longer occurring, but that the desired critical
`dimensions still have not been achieved. Thus, the process
`may be allowed to continue until a later point in time when
`a corresponding signature indicates that the desired critical
`dimensions have been achieved without overlay error.
`Turning to FIG. 2, a cross sectional side vi