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Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 1 of 104
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`PACT XPP SCHWEIZ AG
`
`Plaintiff,
`
`v.
`
`INTEL CORPORATION
`
`Defendant.
`
`Case No. 6:19-cv-00273
`
`JURY TRIAL DEMANDED
`
`Plaintiff PACT XPP Schweiz AG, for its Complaint against Intel Corporation (“Intel” or
`
`COMPLAINT
`
`“Defendant”), hereby alleges as follows:
`
`PARTIES
`
`1.
`
`Plaintiff PACT XPP Schweiz AG is a Swiss corporation, with its principal place of
`
`business in Switzerland. PACT XPP Schweiz AG is the assignee of all patents identified in this
`
`Complaint including all rights to sue for past and future damages for infringement of said patents.
`
`2.
`
`On information and belief, Defendant Intel is a corporation duly organized and
`
`existing under the laws of the State of Delaware, having a regular and established place of business
`
`in the Western District of Texas, including at 1300 S. Mopac Expressway, Austin, Texas 78746.1
`
`3.
`
`Intel, founded in 1968, has over an 80% market share in computer processor
`
`technology, and over $70 Billion in revenues producing $29.4 Billion of cash from operations and
`
`returned nearly $16.3 Billion to shareholders in 2018 based on a gross profit margin of 61.7% of
`
`1 https://www.intel.com/content/www/us/en/location/usa.html;
`https://www.intel.com/content/www/us/en/corporate-responsibility/intel-in-texas.html.
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`1
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 2 of 104
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`revenues. Intel’s two major operating segments are the PC Client Group, which produced over
`
`$37 Billion in revenue for 2018 and focuses on the processors found in consumer-grade netbooks
`
`and desktops, and the Data Center Group, which produced over $32 Billion in revenue and focuses
`
`on processors found in enterprise-level servers.
`
`NATURE OF THE ACTION
`
`4.
`
`This is a civil action for patent infringement of the following patents by Defendant
`
`Intel: U.S. Patent Nos. 7,928,763 (“the ’763 Patent”), 8,301,872 (“the ’872 Patent”), 8,312,301
`
`(“the ’301 Patent”), 8,471,593 (“the ’593 Patent”), 8,686,549 (“the ’549 Patent”), 8,819,505
`
`(“the ’505 Patent”), 9,037,807 (“the ’807 Patent”), 9,075,605 (“the ’605 Patent”), 9,170,812
`
`(“the ’812 Patent”), 9,250,908 (“the ’908 Patent”), 9,436,631 (“the ’631 Patent”), and 9,552,047
`
`(“the ’047 Patent”) (collectively, the “Asserted Patents”). This action is based upon the Patent
`
`Laws of the United States, 35 U.S.C. § 1 et seq.
`
`JURISDICTION AND VENUE
`
`5.
`
`This Court has jurisdiction over the subject matter of this action pursuant to 28
`
`U.S.C. §§ 1331 and 1338(a).
`
`6.
`
`This Court has personal jurisdiction over Intel because Intel manufactures products
`
`that are and have been used, offered for sale, sold, and purchased in the Western District of Texas,
`
`and Intel has committed, and continues to commit, acts of infringement in the Western District of
`
`Texas, has conducted business in the Western District of Texas, and/or has engaged in continuous
`
`and systematic activities in the Western District of Texas.
`
`7.
`
`Under 28 U.S.C. §§ 1391(b)-(d) and 1400(b), venue is proper in this judicial district
`
`because Intel maintains a regular and established place of business in this district and has
`
`committed acts of infringement within this judicial district giving rise to this action.
`
`
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`2
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 3 of 104
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`FACTUAL BACKGROUND
`
`8.
`
`PACT XPP Schweiz’s predecessor and assignor PACT XPP TECHNOLOGIES
`
`AG (Lichtenstein) (hereinafter collectively referred to as “PACT”) was founded in 1996 in
`
`Germany by Martin Vorbach. Mr. Vorbach (the lead inventor on all of PACT’s patents) has been
`
`experimenting with parallel computing since the mid-1980s. Mr. Vorbach embarked on the design
`
`of a completely different type of a multi-core computer architecture—that was the forerunner of
`
`Intel’s multi-core processors. Mr. Vorbach focused his designs on multi-core processing systems
`
`including how to handle more complex algorithms with large amounts of data involving multiple
`
`processors on a single chip. Because of this, he encountered unique challenges that the general
`
`CPU market would not face for years to come and was granted over 70 U.S. patents. On
`
`information and belief, Intel’s multi-core processors at issue were not released until 2011, years
`
`after the priority dates of the Asserted Patents.
`
`9.
`
`For example, one challenge Mr. Vorbach had to solve was how to move and access
`
`data in a multi-core system from one core to the next for large pipelined operations. This led to
`
`his development of bus architectures for multicore processors with multiple paths, including those
`
`using ring bus systems, for both configuring cores and accessing data in the cores and in local
`
`memory including the patents identified herein.
`
`10.
`
`It was not until 2011 that Intel released its “Sandy Bridge” chip architecture accused
`
`of infringement in this Complaint. Sandy Bridge included a ring-based interconnect for
`
`communication between multiple processor cores, processor graphics and cache system. The ring
`
`bus architecture takes up less space on the die while also scaling well for larger core counts—in
`
`contrast to Intel’s earlier dual core designs. Intel coupled this with a last level cache (LLC) that
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`could be alternately shared among the cores. In 2017, Intel introduced a mesh bus architecture,
`
`which is a modified version of the ring bus that also implements Mr. Vorbach’s invention.
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`
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 4 of 104
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`
`
`
`This architecture has been incorporated into most of Intel’s Core Series processor
`
`
`
`11.
`
`family—the i3, i5, i7, and i9 processors—found in computers and on information and belief other
`
`processors manufactured and sold by Intel. Starting with the second generation (code-named
`
`Sandy Bridge, released 2011), these processors have contained a variant of the above-described
`
`ring bus (or equivalents) and LLC feature set including the Sandy Bridge, Ivy Bridge, Haswell,
`
`Broadwell, Skylake, Kaby Lake, Coffee Lake architectures and, on information and belief, other
`
`processors including ring bus architecture (or equivalents). According to Intel’s most recent
`
`
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`4
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 5 of 104
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`reported financial results for 2018,2 its revenue was over $32 Billion for its Data Center Group
`
`and $37.0 Billion for its PC center group.
`
`12.
`
`Another contribution Mr. Vorbach made to the multi-core system is to change the
`
`clock frequencies of part of the multi-core system in a particular way to take advantage of the
`
`processing power of certain cores and in the meantime achieve power efficiency. This invention
`
`was adopted by Intel in its Turbo Boost technology many years later. For example, Turbo Boost
`
`2.0 was introduced in 2011 with the Sandy Bridge microarchitecture, and Turbo Boost Max 3.0
`
`was introduced in 2016 with the Broadwell microarchitecture. On information and belief, Turbo-
`
`Boost-enabled processors have been manufactured since 2008.
`
`13.
`
`Another contribution Mr. Vorbach made to the multi-core system is a stacking
`
`technique, according to which the multi-core processors and the bus system are stacked on a
`
`plurality of dies in an efficient way. Intel just adopted this stacking technique in recent
`
`announcements.
`
`14.
`
`In December 2018, Intel hosted an Architecture Day conference in California for
`
`analysts and media that allowed Intel’s top executives, architects and fellows to reveal their next-
`
`generation technologies to a captive audience. During the conference, Intel announced that it had
`
`created a new 3D packaging technology, called “Foveros.” Foveros is expected to extend die
`
`stacking beyond passive interposers and stacked memory to high-performance logic, such as CPU.
`
`In January 2019, during the CES conference, Intel made further announcement of a new product,
`
`Lakefield, that implements the Foveros technology. The Foveros technology, however, takes
`
`
`2 https://www.intc.com/investor-relations/investor-education-and-news/investor-news/press-
`release-details/2019/Intel-Reports-Fourth-Quarter-2018-Financial-Results/default.aspx
`
`
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`5
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 6 of 104
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`advantage of PACT’s invention disclosed in U.S. Patent No. 8,686,549, which, on information and
`
`belief, Intel has been aware of since 2015.
`
`15.
`
`PACT does not make or sell products in the United States that implement the
`
`asserted patents, and to PACT’s knowledge no PACT licensed products made or sold in the United
`
`States implement the asserted patents.
`
`INTEL HAS TOUTED THE BENEFITS OF THE INFRINGING TECHNOLOGY
`
`16.
`
`Intel itself has touted the improvements realized by the incorporation of the accused
`
`technologies.
`
`17.
`
`In Intel’s technical materials, it marketed the ring bus and L3 cache architecture by
`
`pointing to their specific advantages, such as robustness, scalability, and modularity:
`
`18.
`
`Regarding Turbo Boost, Intel states on its official website that “Intel® Turbo Boost
`
`Technology 2.0 accelerates processor and graphics performance for peak loads, automatically
`
`allowing processor cores to run faster than the rated operating frequency if they’re operating below
`
`
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`6
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 7 of 104
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`power, current, and temperature specification limits.”3 “Turbo Boost Max Technology 3.0 . . .
`
`enhances it with a massive frequency boost on your fastest cores for more flexibility to get the best
`
`from your processor.” 4 “As the name implies, processors with this feature will enable extra
`
`performance when you need it most. . . . With this exciting new technology, end users can game
`
`faster, be more productive, and do more, because it’s Intel.”5
`
`19.
`
`Intel also touted the Foveros technology on its official website: “Foveros paves the
`
`way for devices and systems combining high-performance, high-density and low-power silicon
`
`process technologies. Foveros is expected to extend die stacking beyond traditional passive
`
`interposers and stacked memory to high-performance logic, such as CPU, graphics and AI
`
`processors for the first time. The technology provides tremendous flexibility as designers seek to
`
`‘mix and match’ technology IP blocks with various memory and I/O elements in new device form
`
`factors. It will allow products to be broken up into smaller ‘chiplets,’ where I/O, SRAM and power
`
`delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked
`
`on top. . . . Foveros is the next leap forward following Intel’s breakthrough Embedded Multi-die
`
`Interconnect Bridge (EMIB) 2D packaging technology, introduced in 2018.”6
`
`THE ASSERTED PATENTS
`
`20.
`
`On April 19, 2011, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’763 Patent, titled “Multi-Core Processing System.” The ’763 Patent names Martin Vorbach
`
`as the sole inventor. The ’763 Patent has been in full force and effect since its issuance. PACT
`
`
`3 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-technology.html
`4 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-max-technology.html
`5 https://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-
`boost-max-technology.html
`6 https://newsroom.intel.com/articles/new-intel-architectures-technologies-target-expanded-
`market-opportunities/#gs.uIfUyfYJ
`
`
`
`7
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`owns by assignment the entire right, title, and interest in and to the ’763 Patent, including the right
`
`to seek damages for past, current, and future infringement thereof. PACT is the sole owner of
`
`the ’763 Patent. A copy of the ’763 Patent is attached hereto as Exhibit A.
`
`21.
`
`On October 30, 2012, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’872 Patent, titled “Pipeline Configuration Protocol and Configuration Unit Communication.”
`
`The ’872 Patent names Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, and Armin
`
`Nuckel as co-inventors. The ’872 Patent has been in full force and effect since its issuance. PACT
`
`owns by assignment the entire right, title, and interest in and to the ’872 Patent, including the right
`
`to seek damages for past, current, and future infringement thereof. PACT is the sole owner of
`
`the ’872 Patent. A copy of the ’872 Patent is attached hereto as Exhibit B.
`
`22.
`
`On November 13, 2012, the U.S. Patent and Trademark Office duly and legally
`
`issued the ’301 Patent, titled “Methods and Devices for Treating and Processing Data.” The ’301
`
`Patent names Martin Vorbach and Volker Baumgarte as co-inventors. The ’301 Patent has been
`
`in full force and effect since its issuance. PACT owns by assignment the entire right, title, and
`
`interest in and to the ’301 Patent, including the right to seek damages for past, current, and future
`
`infringement thereof. PACT is the sole owner of the ’301 Patent. A copy of the ’301 Patent is
`
`attached hereto as Exhibit C.
`
`23.
`
`On June 25, 2013, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’593 Patent, titled “Logic Cell Array and Bus System.” The ’593 Patent names Martin Vorbach,
`
`Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nuckel, Volker Baumgarte, Prashant
`
`Rao, and Jens Oertel as co-inventors. The ’593 Patent has been in full force and effect since its
`
`issuance. PACT owns by assignment the entire right, title, and interest in and to the ’593 Patent,
`
`
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`8
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 9 of 104
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`including the right to seek damages for past, current, and future infringement thereof. PACT is
`
`the sole owner of the ’593 Patent. A copy of the ’593 Patent is attached hereto as Exhibit D.
`
`24.
`
`On April 1, 2014, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’549 Patent, titled “Reconfigurable Elements.” The ’549 Patent names Martin Vorbach as the
`
`sole inventor. The ’549 Patent has been in full force and effect since its issuance. PACT owns by
`
`assignment the entire right, title, and interest in and to the ’549 Patent, including the right to seek
`
`damages for past, current, and future infringement thereof. PACT is the sole owner of the ’549
`
`Patent. A copy of the ’549 Patent is attached hereto as Exhibit E.
`
`25.
`
`On August 26, 2014, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’505 Patent, titled “Data Processor Having Disabled Cores.” The ’505 Patent names Martin
`
`Vorbach and Robert Munch as co-inventors. The ’505 Patent has been in full force and effect
`
`since its issuance. PACT owns by assignment the entire right, title, and interest in and to the ’505
`
`Patent, including the right to seek damages for past, current, and future infringement thereof.
`
`PACT is the sole owner of the ’505 Patent. A copy of the ’505 Patent is attached hereto as Exhibit
`
`F.
`
`26.
`
`On May 19, 2015, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’807 Patent, titled “Processor Arrangement on a Chip Including Data Processing, Memory, and
`
`Interface Elements.” The ’807 Patent names Martin Vorbach as the sole inventor. The ’807 Patent
`
`has been in full force and effect since its issuance. PACT owns by assignment the entire right,
`
`title, and interest in and to the ’807 Patent, including the right to seek damages for past, current,
`
`and future infringement thereof. PACT is the sole owner of the ’807 Patent. A copy of the ’807
`
`Patent is attached hereto as Exhibit G.
`
`
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`9
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 10 of 104
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`27.
`
`On July 7, 2015, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’605 Patent, titled “Methods and Devices for Treating and Processing Data.” The ’605 Patent
`
`names Martin Vorbach and Volker Baumgarte as co-inventors. The ’605 Patent has been in full
`
`force and effect since its issuance. PACT owns by assignment the entire right, title, and interest
`
`in and to the ’605 Patent, including the right to seek damages for past, current, and future
`
`infringement thereof. PACT is the sole owner of the ’605 Patent. A copy of the ’605 Patent is
`
`attached hereto as Exhibit H.
`
`28.
`
`On October 27, 2015, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’812 Patent, titled “Data Processing System Having Integrated Pipelined Array Data Processor.”
`
`The ’812 Patent names Martin Vorbach, Jurgen Becker, Markus Weinhardt, Volker Baumgarte,
`
`and Frank May as co-inventors. The ’812 Patent has been in full force and effect since its issuance.
`
`PACT owns by assignment the entire right, title, and interest in and to the ’812 Patent, including
`
`the right to seek damages for past, current, and future infringement thereof. PACT is the sole
`
`owner of the ’812 Patent. A copy of the ’812 Patent is attached hereto as Exhibit I.
`
`29.
`
`On February 2, 2016, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’908 Patent, titled “Multi-Processor Bus and Cache Interconnection System.” The ’908 Patent
`
`names Martin Vorbach, Volker Baumgarte, Frank May, and Armin Nuckel as co-inventors.
`
`The ’908 Patent has been in full force and effect since its issuance. PACT owns by assignment
`
`the entire right, title, and interest in and to the ’908 Patent, including the right to seek damages for
`
`past, current, and future infringement thereof. PACT is the sole owner of the ’908 Patent. A copy
`
`of the ’908 Patent is attached hereto as Exhibit J.
`
`30.
`
`On September 6, 2016, the U.S. Patent and Trademark Office duly and legally
`
`issued the ’631 Patent, titled “Chip Including Memory Element Storing Higher Level Memory
`
`
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`10
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`Data on a Page by Page Basis.” The ’631 Patent names Martin Vorbach as the sole inventor.
`
`The ’631 Patent has been in full force and effect since its issuance. PACT owns by assignment the
`
`entire right, title, and interest in and to the ’631 Patent, including the right to seek damages for
`
`past, current, and future infringement thereof. PACT is the sole owner of the ’631 Patent. A copy
`
`of the ’631 Patent is attached hereto as Exhibit K.
`
`31.
`
`On January 24, 2017, the U.S. Patent and Trademark Office duly and legally issued
`
`the ’047 Patent, titled “Multiprocessor Having Runtime Adjustable Clock and Clock Dependent
`
`Power Supply.” The ’047 Patent names Martin Vorbach and Volker Baumgarte as co-inventors.
`
`The ’047 Patent has been in full force and effect since its issuance. PACT owns by assignment
`
`the entire right, title, and interest in and to the ’047 Patent, including the right to seek damages for
`
`past, current, and future infringement thereof. PACT is the sole owner of the ’047 Patent. A copy
`
`of the ’047 Patent is attached hereto as Exhibit L.
`
`THE ACCUSED INTEL INSTRUMENTALITIES
`
`32.
`
`Intel has infringed the Asserted Patents through the manufacture, use (including
`
`testing), sale, offer for sale, advertisement, importation, shipment and distribution, service,
`
`installation, and/or maintenance of Intel Core processors with Sandy Bridge and above
`
`microarchitectures (the “Accused Core Instrumentalities”), Intel Xeon processors with Sandy
`
`Bridge and above microarchitectures (the “Accused Xeon Instrumentalities”), and Intel Celeron
`
`Processors with Sandy Bridge and above microarchitectures (the “Accused Celeron
`
`Instrumentalities”) and on information and belief other processors incorporating ring bus
`
`architecture or equivalents (such as mesh bus architcture).
`
`33.
`
`The Accused Core Instrumentalities are Intel Core processors with Sandy Bridge
`
`and above microarchitectures, including, but not limited to, Core i3, Core i5, Core i7, Core i9, and
`
`
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`11
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`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 12 of 104
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`other core processors with the microarchitectures of Sandy Bridge, Ivy Bridge, Haswell, Broadwell,
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`Skylake, Kaby Lake, Coffee Lake, Cannon Lake, Ice Lake, and above.
`
`34.
`
`The Accused Xeon Instrumentalities are Intel Xeon processors with Sandy Bridge
`
`and above microarchitectures, including, but not limited to, E3, E5, E7, and other Xeon processors
`
`with the microarchitectures of Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake,
`
`and above.
`
`35.
`
`Other accused instrumentalities include the Accused Turbo Boost Instrumentalities,
`
`the Accused Stacking Instrumentalities, and the Accused ’505 Instrumentalities as defined and
`
`discussed in corresponding sections below.
`
`COUNT I – INFRINGEMENT OF U.S. PATENT NO. 7,928,763
`
`36.
`
`PACT incorporates each of the above paragraphs 1-35 as though fully set forth
`
`herein.
`
`37.
`
`PACT is informed and believes, and thereon alleges, that Intel has infringed and
`
`unless enjoined will continue to infringe one or more claims of the ’763 Patent, in violation of 35
`
`U.S.C. § 271, by, among other things, making, using (including testing), offering to sell, and
`
`selling within the United States, supplying or causing to be supplied in or from the United States,
`
`and importing into the United States, without authority or license, Intel products with the infringing
`
`features, including the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and
`
`the Accused Celeron Instrumentalities.
`
`38.
`
`For example,
`
`the Accused Core
`
`Instrumentalities,
`
`the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities embody every limitation of at least
`
`claim 1 of the ’763 Patent, literally or under the doctrine of equivalents, as set forth below. The
`
`further descriptions below, which are based on publicly available information, are preliminary
`
`examples and are non-limiting.
`
`
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`“A multi-processor chip, comprising”
`
`39.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities are multi-core processors, and hence, a multi-processor chip.
`
`“a plurality of data processing cells, each adapted for sequentially executing at least one of
`
`algebraic and logic functions and having”
`
`40.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include a plurality of cores, each of which is adapted for
`
`sequentially executing at least one of algebraic and logic functions as shown in the figure below:
`
`
`
`“at least one arithmetic logic unit; at least one data register file; a program pointer; and at least
`
`one instruction decoder”
`
`41.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include multi-core processors further including multiple ALUs,
`
`general purpose registers, instruction pointer, and decoders, thus, including the recited arithmetic
`
`logic unit, at least one data register file, a program pointer, and at least one instruction decoder.
`
`“a plurality of memory cells”
`
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`42.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include Last Level Caches that constitute a plurality of memory
`
`cells.
`
`“at least one interface unit”
`
`43.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include a System Agent and/or components within or connected
`
`or attached to the System Agent and/or the Last Level Caches (such as cache box) that constitute
`
`at least one interface unit.
`
`“at least one Memory Management Unit (MMU); and”
`
`44.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include memory management functionalities, and thus, at least
`
`one Memory Management Unit (MMU).
`
`“a bus system for interconnecting the plurality of data processing cells, the plurality of memory
`
`cells, and the at least one interface unit, wherein the bus system is adapted for programmably
`
`interconnecting at runtime at least one of data processing cells and memory cells with at least
`
`one of memory cells and one or more of the at least one interface unit.”
`
`45.
`
`The Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities include a ring bus system (or equivalents) programmably
`
`interconnecting at runtime the cores, the LLCs and/or the interface unit identified above as shown
`
`in the figure below:
`
`
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`14
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`
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`46.
`
`In violation of 35 U.S.C. § 271, Intel has infringed and is currently infringing,
`
`directly and/or through intermediaries, the ’763 Patent by making, using, selling, offering for sale,
`
`and/or importing into the United States, without authority, products that practice at least claim 1
`
`of the ’763 Patent. These products include the Accused Core Instrumentalities, the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities, and any other products that
`
`incorporate the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`Accused Celeron Instrumentalities. Intel has infringed and is currently infringing literally and/or
`
`under the doctrine of equivalents.
`
`47.
`
`On information and belief, PACT asserts that Intel was aware of this patent before
`
`this lawsuit was filed, and at least as of the service of the Complaint in PACT XPP Schweiz AG v.
`
`Intel Corporation, 1-19-cv-00267 (DED), Intel had actual knowledge of its infringement of
`
`the ’763 Patent.
`
`48.
`
`PACT is informed and believes, and thereon alleges, that Intel, subsequent to the
`
`time it first learned of the ’763 Patent and at least as of the time of service of the Complaint in
`
`PACT XPP Schweiz AG v. Intel Corporation, 1-19-cv-00267 (DED), specifically intended to
`
`induce patent infringement by third-party original equipment manufacturers (OEMs), customers,
`
`and users of the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the
`
`
`
`15
`
`

`

`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 16 of 104
`
`Accused Celeron Instrumentalities and had knowledge that the inducing acts would cause
`
`infringement or is willfully blind to the possibility that their inducing acts would cause
`
`infringement. Intel has sold and continues to sell the Accused Core Instrumentalities, the Accused
`
`Xeon Instrumentalities, and the Accused Celeron Instrumentalities to OEMs making OEM
`
`products (e.g., computers, servers, laptops, tablets, etc.), knowing that the Accused Core
`
`Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities
`
`will be included in the OEM products and sold to customers in the United States in violation of
`
`U.S. patent law, and/or to original design manufacturers (ODMs), knowing that the Accused Core
`
`Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities
`
`will ultimately be included in OEM products and sold to customers in the United States.
`
`49.
`
`Indeed, Intel’s “Intel Inside” campaign has informed customers through advertising
`
`and stickers on the OEM products themselves that the products contain the Accused Core
`
`Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities.
`
`Intel also knows that many such OEM products that contain the Accused Core Instrumentalities,
`
`the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities are made outside
`
`the United States and are imported into the United States in violation of U.S. patent law. Intel also
`
`knows that U.S. customers of the OEMs use the OEM products containing the Accused Core
`
`Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities
`
`in the United States in violation of U.S. patent law.
`
`50.
`
`Intel also publicly provides documentation, including datasheets available through
`
`Intel’s publicly accessible ARK service and software developer’s manuals, instructing customers
`
`on uses of Intel’s products that infringe the ’763 Patent. See, e.g., http://ark.intel.com. In addition,
`
`Intel specifically advertises and promotes the infringing use of Intel’s products, including the ring
`
`
`
`16
`
`

`

`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 17 of 104
`
`bus system and its equivalent. See, e.g., https://software.intel.com/en-us/articles/how-memory-is-
`
`accessed.
`
`51.
`
`On information and belief, Intel’s customers directly infringe the ’763 Patent by,
`
`for example, making, using, offering to sell, and selling within the United States, and importing
`
`into the United States, without authority or license, products containing the Accused Core
`
`Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities.
`
`52.
`
`Intel contributes to the infringement of the ’763 Patent in violation of 35 U.S.C.
`
`§ 271(c). As stated above, on information and belief Intel was aware of the ’763 Patent before this
`
`lawsuit was filed but Intel was aware of the ’763 Patent at least as of the time of service of the
`
`Complaint in PACT XPP Schweiz AG v. Intel Corporation, 1-19-cv-00267 (DED). Intel thus offers
`
`to sell and sells within the United States the Accused Core Instrumentalities, the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities knowing that those products
`
`constitute a material part of the claimed invention because Intel incorporates the accused
`
`components (ring bus system, multi-cores, LLCs, etc.) into the Accused Core Instrumentalities,
`
`the Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities.
`
`53.
`
`Intel knows that the Accused Core Instrumentalities, the Accused Xeon
`
`Instrumentalities, and the Accused Celeron Instrumentalities are especially made or especially
`
`adapted for use in infringing the ’763 Patent because the Accused Core Instrumentalities, the
`
`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities all contain the
`
`infringing components (ring bus system, multi-cores, LLCs, etc.). Furthermore, because the
`
`Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron
`
`Instrumentalities contain the infringing components (ring bus system, multi-cores, LLCs, etc.),
`
`they are not a staple article or commodity of commerce suitable for substantial non-infringing use.
`
`
`
`17
`
`

`

`Case 6:19-cv-00273-ADA Document 1 Filed 04/23/19 Page 18 of 104
`
`54.
`
`In addition, Intel offers to sell and sells the Accused Core Instrumentalities, the
`
`Accused Xeon Instrumentalities, and the Accused Celeron Instrumentalities to Original Equipment
`
`Manufacturers (OEMs) and/or Original Design Manufacturers (ODMs) who then incorporate the
`
`Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused Celeron
`
`Instrumentalities into infringing products which are used, sold, offered for sale, and/or imported
`
`in the United States in an infringing manner. Accordingly, Intel is liable as a contributory infringer.
`
`55.
`
`In the alternative, to the extent Intel does not meet all of the limitations of the ’763
`
`Patent by making the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and
`
`the Accused Celeron Instrumentalities in the United States, Intel infringes under 35 U.S.C. §
`
`271(f)(1) and (f)(2) by supplying from the United States a substantial portion of the components
`
`of the Accused Core Instrumentalities, the Accused Xeon Instrumentalities, and the Accused
`
`Celeron Instrumentalities (for example, structures or components contained in semiconductor
`
`wafers or dies or the like), and actively induces the combination of components outside the United
`
`States in a manner that would infringe the ’763 Patent (for example, by packaging or assembly, or
`
`by incorporation into computers, laptops, servers, tablets, or the like by ODMs or OEMs). Intel
`
`further supplies from the United States com

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