`Case 6:20-cv-00194-ADA Document 1-1 Filed 03/17/20 Page 1 of 15
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`EXHIBIT 1
`EXHIBIT 1
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`Case 6:20-cv-00194-ADA Document 1-1 Filed 03/17/20 Page 2 of 15
`case 6:20'CV'00194'ADA DC’CL‘mfillllllllllllIll-IllIlllllllllfllllllllllllllilllllillllllllllll||||||||
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`US009858218B1
`
`(12) United States Patent
`US 9,858,218 B1
`Lee
`(45) Date of Patent:
`*Jan. 2, 2018
`
`(10) Patent No.:
`
`(54)
`
`MEMORY MODULE AND METHODS FOR
`HANDSHAKING WITH A MEMORY
`CONTROLLER
`
`(56)
`
`References Cited
`U. S. PATENT DOCUMENTS
`
`(71)
`
`Applicant: Netlist, Inc., Irvine, CA (US)
`
`(72)
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`Inventor: Hyun Lee, Ladera Ranch, CA (US)
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`(73)
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`Assignee: Netlist, Inc., Irvine, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21)
`
`Appl. No.: 15/088,115
`
`(22)
`
`Filed:
`
`Apr. 1, 2016
`
`Related US. Application Data
`
`(63)
`
`Continuation of application No. 13/942,721, filed on
`Jul. 16, 2013, now Pat. No. 9,311,116, which is a
`(Continued)
`
`Int. Cl.
`
`(51)
`
`G06F 12/00
`G06F 13/16
`
`US. Cl.
`
`(52)
`
`(2006.01)
`(2006.01)
`(Continued)
`
`(58)
`
`CPC .......... G06F 13/1694 (2013.01); G06F 9/445
`(2013.01); G06F 12/0646 (2013.01);
`(Continued)
`Field of Classification Search
`CPC
`G11C 5/00; G11C 16/26; G11C 2029/4402;
`G11C 29/78; G11C 7/1066
`(Continued)
`
`3,560,935 A
`4,672,570 A
`
`2/1971 Beers
`6/1987 Benken
`(Continued)
`
`OTHER PUBLICATIONS
`
`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
`00548, Exhibit 20017Declarati0n of Robert J. Murphy, filed Sep.
`6, 2017.
`
`(Continued)
`
`Primary Examiner 7 Mardochee Chery
`(74) Attorney, Agent, or Firm 7 Maschoff Brennan
`
`(57)
`
`ABSTRACT
`
`According to certain aspects, a memory module is coupled
`to a memory controller of a host computer system via an
`interface. The interface includes data, address and control
`signal pins and an output pin in addition to the data, address
`and control signal pins. The memory module receives a first
`command from the memory controller via the address and
`control signal pins, and enters a first mode in response to the
`first command. The memory module in the first mode
`responds to at least one initialization sequence, and sends a
`first output signal via the output pin to indicate a status of the
`at least one initialization sequence to the memory controller.
`The memory module enters a second mode in which the
`memory module performs memory operations including
`memory read/write operations according to an industry
`standard. During the read/write operations,
`the memory
`module communicates data with the memory controller via
`the data signal pins in response to second memory com-
`mands received via the address and control signal pins. The
`memory module may output a second output signal related
`to the read/write operations via the output pin.
`
`22 Claims, 3 Drawing Sheets
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`4O
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`Case 6:20-cv-00194-ADA Document 1-1 Filed 03/17/20 Page 3 of 15
`Case 6:20-cv-00194-ADA Document 1—1 Filed 03/17/20 Page 3 of 15
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`US 9,858,218 B1
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`Page 2
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`Related U.S. Application Data
`
`continuation of application No. 12/815,339, filed on
`Jun. 14, 2010, now Pat. No. 8,489,837.
`
`(60) Provisional application No. 61/186,799, filed on Jun.
`12, 2009.
`
`(51)
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`Int. Cl.
`G06F 13/24
`G06F 12/06
`G06F 9/445
`G11C 16/26
`G11C 5/00
`G11C 29/44
`G11C 29/00
`G11C 7/10
`(52) U.S. Cl.
`CPC ................ G06F 13/24 (2013.01); G11C 5/00
`(2013.01); G11C 7/1066 (2013.01); G11C
`16/26 (2013.01); G11C 29/78 (2013.01); G11C
`2029/4402 (2013.01)
`
`(58) Field of Classification Search
`USPC ............................................... 711/116; 713/1
`See application file for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,388,074 A
`5,438,536 A
`5,450,576 A
`5,511,152 A
`5,684,979 A
`5,835,733 A
`6,693,840 B2
`6,754,787 B2
`6,763,437 B1
`6,886,109 B2
`7,024,518 B2
`7,065,688 B1
`7,093,115 B2
`7,155,579 B1
`7,266,633 B2
`7,489,163 B2
`7,539,909 B2
`7,586,350 B2
`7,757,101 B2
`8,074,034 B2
`8,359,521 B2
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`2003/0115427 A1*
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`2/1995 Buckenmaier
`8/1995 Salzman
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`11/1997 Grimes
`11/1998 Walsh et a1.
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`7/2004 Nguyen et a1.
`4/2005 Olarig et a1.
`4/2006 Halbert et a1.
`6/2006 Moyes et a1.
`8/2006 Poisner et a1.
`12/2006 Neils et a1.
`9/2007 James
`2/2009 Goodnow et a1.
`5/2009 LeClerg et a1.
`9/2009 Chung et a1.
`7/2010 Nonaka et a1.
`12/2011 Sartore
`1/2013 Kim et a1.
`4/2013 Sokolov et a1.
`6/2003 Roohparvar ............. G11C 7/02
`711/154
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`2005/0071580 A1
`2005/0193161 A1
`2006/0062047 A1
`2006/0262586 A1
`2007/0091702 A1
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`3/2005 LeClerg et a1.
`9/2005 Lee et a1.
`3/2006 Bhakta et a1.
`11/2006 Solomon et a1.
`4/2007 Nikitin
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`2007/0136523 A1
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`2010/0042778 A1*
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`2010/0142383 A1*
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`6/2010
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`2010/0202240 A1
`2011/0022789 A1
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`8/2010
`1/2011
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`Bonella et a1.
`Rothman et a1.
`Fahr et a1.
`Grundy
`Gower et a1.
`Tanguay ............. G06F 13/1694
`7 1 1/105
`.................... H04L 43/50
`370/250
`
`Goishi
`
`Moshayedi et a1.
`Fujimoto
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20027Dep0siti0n of Donald Alpert, Ph.D. filed
`Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20037Defendants’ Opening Claim Construction
`Brief filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20047P1aintiff Netlist, Inc.’s Opening Claim Con-
`struction Brief filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20057P1aintiff Netlist, Inc.’s Amended Opening
`Claim Construction Brief filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20067Defendants’ Reply Claim Construction Brief
`filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20077P1aintiff Netlist, Inc.’s Responsive Claim
`Construction Brief filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20087United States International Trade Commis-
`sion Open Sessions filed Sep. 6, 2017.
`Inter Partes Review ofL .8. Pat. \10. 8,489,837, Case \10. IPR2017-
`00548, Exhibit 20097C0mputer Desktop Encyclopedia Sep. 6,
`2017.
`Inter partes review Case No. IPR2017-00548, Petition for Inter
`Partes Review of U.S. Pat. No. 8,489,837, filed Dec. 30, 2016.
`Inter partes review Case No. IPR2017-00548, Exhibit 1003 “Dec-
`laration of Donald Alpert”, filed Dec. 30, 2016.
`Inter partes review Case No. IPR2017-00548, Exhibit 1010 “5400
`MCH Datasheet”, filed Dec. 30, 2016.
`Inter partes review Case No.
`IPR2017-00548, Exhibit 1011
`“Microsoft Computer Dictionary (5th Ed. 2002)”, filed Dec. 30,
`2016.
`IPR2017-00548, Patent Owner’s
`Inter partes review Case No.
`Preliminary Response filed Apr. 9, 2017.
`Inter partes review Case No. IPR2017-00548, Trial Instituted docu-
`ment dated May 15, 2017.
`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
`00548, Petitioner’s Objections to Evidence, filed Sep. 13, 2017.
`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
`00548, Notice of Deposition of Robert J. Murphy, filed Sep. 25,
`2017.
`
`* cited by examiner
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`
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`Case 6:20-cv-00194-ADA Document 1-1 Filed 03/17/20 Page 4 of 15
`Case 6:20-cv-00194-ADA Document 1-1 Filed 03/17/20 Page 4 of 15
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`U.S. Patent
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`Jan. 2, 2018
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`Sheet 1 013
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`US 9,858,218 B1
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`U.S. Patent
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`Jan. 2, 2018
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`Sheet 2 of 3
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`US 9,858,218 B1
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`100
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`Provide first memory module
`
`Cause the first memory
`module to enter initialization mode
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`102
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`104
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`106
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`108
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`the at least one first output to a second state
`
`Drive the at least one first output to a first state
`while the memory module executes initialization
`sequence
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`Upon completion of initialization sequence, drive
`
`Figure 4
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`
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`U.S. Patent
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`Jan. 2, 2018
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`Sheet 3 of 3
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`US 9,858,218 B1
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`200
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`\4
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`202
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`Provide first memory module
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`204
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`Cause the memory module to enter initialization
`mode
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`206
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`Receive notification signal
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`Figure 5
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`US 9,858,218 B1
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`1
`MEMORY MODULE AND METHODS FOR
`HANDSHAKING WITH A MEMORY
`CONTROLLER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of US. application Ser.
`No. 13/942,721, filed Jul. 16, 2013, now US. Pat. No.
`9,311,116, which is a continuation of US. application Ser.
`No. 12/815,339, filed Jun. 14, 2010, now US. Pat. No.
`8,489,837, which claims the benefit of priority from US.
`Provisional App. No. 61/186,799, filed Jun. 12, 2009, each
`of which is incorporated in its entirety by reference herein.
`
`FIELD OF THE DISCLOSURE
`
`The present disclosure relates to the operation of memory
`modules. Specifically, the present disclosure relates to sys-
`tems and methods for handshaking with a memory module
`during or upon completion of initialization.
`
`BACKGROUND OF THE DISCLOSURE
`
`Memory subsystems such as memory modules are gen-
`erally involved in the initialization procedure for computer
`systems, including servers, personal computers, and the like.
`For example, during system-wide initialization, the memory
`subsystems may undergo internal initialization procedures,
`or the system memory controller may otherwise interact
`with the memory subsystems during the initialization pro-
`cedure. As part of this interaction,
`the system memory
`controller may request that the memory subsystem perform
`one or more requested tasks during system initialization.
`
`SUMMARY
`
`According to certain aspects, a memory module is
`coupled to a memory controller of a host computer system
`via an interface. The interface includes data, address and
`control signal pins and an output pin in addition to the data,
`address and control signal pins. The memory module
`receives a first command from the memory controller via the
`address and control signal pins, and enters a first mode in
`response to the first command. The memory module in the
`first mode responds to at least one initialization sequence,
`and sends a first output signal via the output pin to indicate
`a status of the at least one initialization sequence to the
`memory controller. The memory module enters a second
`mode in which the memory module performs memory
`operations including memory read/write operations accord-
`ing to an industry standard. During the read/write opera-
`tions,
`the memory module communicates data with the
`memory controller via the data signal pins in response to
`second memory commands received via the address and
`control signal pins. The memory module may output a
`second output signal related to the read/write operations via
`the output pin.
`According to certain aspects, a memory module is
`coupled to a memory controller of a host computer system
`via an interface. The interface includes data, address and
`control signal pins and an output pin in addition to the data,
`address and control signal pins. The memory module per-
`forms an internal procedure in a first mode in response to a
`first command from the memory controller whereby the
`memory controller hands off control of the internal proce-
`dure to the first memory module. The memory module sends
`
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`2
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`a first output signal via the output pin to indicate a status of
`the internal procedure to the memory controller. The
`memory module enters a second mode in which the memory
`module performs standard operations including one or more
`of memory read/write, pre-charge,
`refresh operations
`according to an industry standard. The memory module may
`output a second output signal related to the standard opera-
`tions via the output pin.
`In another aspect, a memory module is operable in a first
`mode and in a second mode. The memory module operates
`according to an industry standard in the second mode by
`performing standard operations including memory read/
`write operations in response to address and control signals
`from a memory controller of a host computer system. The
`memory module comprises a standard interface including
`data, address and control signal pins and an output pin in
`addition to the data, address and control signal pins. The
`memory module enters the first mode in response to a first
`command from the memory controller, in which the memory
`module responds to at least one initialization sequence. The
`memory module further comprises a notification circuit to
`output a notification signal indicating a status of the at least
`one initialization sequence to the memory controller via the
`output pin.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows an example host computer system including
`an example memory module configured to perform hand-
`shaking with a memory controller of the host computer
`system according to certain embodiments described herein.
`FIG. 2 shows an example host computer system including
`example first and second memory modules configured to
`perform handshaking with a system memory controller of
`the host computer system according to certain embodiments
`described herein.
`
`FIG. 3 shows a host computer system including example
`first and second memory modules configured to perform
`handshaking with a memory controller of the host system,
`where the notification circuits of the first and second
`
`memory modules have another example configuration
`according to certain embodiments described herein.
`FIG. 4 and FIG. 5 show example methods of using at least
`one memory module according to certain embodiments
`described herein.
`
`DETAILED DESCRIPTION
`
`Existing initialization schemes have certain inefficiencies
`which lead to wasted time and expense. Thus, there is a need
`to reduce the time and complexity involved in system
`memory controller interactions with memory subsystems
`during initialization. Certain embodiments described herein
`advantageously satisfy at least a portion of this need by
`providing a system and method which utilizes a feedback
`path from a memory subsystem such as a memory module
`to a system memory controller, such as a Memory Controller
`Hub (MCH) of a computer system during initialization.
`In general, there is no existing method of handshaking
`between the MCH (e.g., system memory controller) and a
`memory subsystem (e.g., memory module) during initial-
`ization. For example, in conventional systems, the system
`memory controller does not monitor the error-out signal
`from the memory subsystem. This causes the MCH to
`perform blind execution. In a typical server (e. g., an Intel or
`AMD or other chipset based server), the lack of any hand-
`shaking between the MCH and the memory subsystem
`
`
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`US 9,858,218 B1
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`3
`during the server initialization period has not been a serious
`issue since the MCH generally has complete control over the
`initialization procedure. However, one possible configura-
`tion for LR-DIMM (Load Reduced DIMM) includes the
`MCH handing over one or more parts of the initialization
`operation sequence to the memory subsystem. This raises an
`unprecedented issue not addressed in conventional systems
`because, in such proposed configurations, the system can
`benefit from the MCH handshaking with the memory sub-
`system controller, as described more fully below.
`Such an LR-DIMM configuration may have the MCH
`inserting a waiting period of predetermined length during
`which the MCH is idle and the memory subsystem controller
`undergoes initialization. However, one shortcoming of this
`LR-DIMM configuration would be that it requires the MCH
`to be in standby (idle, or wait) while the memory subsystem
`controller completes its task. Under such an arrangement,
`since the time to complete a task can be dependent on the
`density, speed and configuration of the memory subsystem,
`and these parameters may be unknown to the MCH, the
`MCH may have to insert a single, predetermined standby
`period. In addition, if there are multiple occasions that the
`MCH needs to hand off control to the memory subsystem
`controller, the required MCH wait periods can be different
`from one occasion to another, and it complicates the corre-
`lation between the MCH and the memory subsystem con-
`troller. For example, the MCH according to such a scheme
`may give control
`to the local memory controller of a
`memory subsystem (e.g., memory module) for execution of
`a training sequence. The MCH may wait for a pre-deter-
`mined period of time and then assume that the local memory
`controller has completed the training sequence. However,
`depending on the memory subsystem parameters (e.g.,
`memory capacity, speed, number of ranks, etc.), the time for
`actually completing the training sequence may vary and may
`be longer or shorter than predetermined period of time.
`In general, handshaking can be implemented in at least
`two ways; polling and notifying. In the polling method, the
`MCH reads a status register in the memory subsystem
`controller to find out if the memory subsystem controller has
`completed the required or requested operation. For example,
`a status register may be read out through a serial interface
`such as System Management Bus (SMBus). However, a
`register polling method is generally inefficient because the
`system memory controller does not know exactly when the
`memory subsystem will have completed the required or
`requested operation. Thus, the system memory controller
`may wait longer than necessary to poll the memory subsys-
`tem,
`thereby delaying the overall
`initialization process.
`Additionally,
`the problem may be compounded because
`multiple training sequences or other initialization sequences
`may be run on the memory subsystem during a particular
`initialization period,
`resulting in accumulation of such
`unnecessary delays. Moreover, polling generally involves
`scheduling polling intervals during which the system
`memory controller
`is not performing other operations,
`resulting in further inefficiency.
`Alternatively, the notifying method is an advantageous
`handshaking method between the MCH and the memory
`subsystem controller. According to a notifying method, the
`memory subsystem controller sends a signal to the MCH
`when the memory subsystem controller completes the
`required or requested operation. This method allows the
`MCH to execute one or more independent commands while
`it is waiting for a notification signal from the memory sub
`system controller.
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`5
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`4
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`Certain embodiments described herein provide a method
`of establishing a handshake mechanism based on notifica-
`tion signaling. In certain embodiments, this mechanism can
`be implemented by adding a new interface (notifying) signal
`between the MCH and the memory subsystem controller, or
`by adding an additional functionality to an existing, non-
`timing critical signal without altering the memory subsystem
`hardware. In either case, the interface between the MCH and
`the memory subsystem controller of certain embodiments
`can be an open drain signaling from the memory subsystem
`controller to the MCH, although a variety of other configu-
`rations are possible. As will be appreciated by persons
`skilled in the art, the terms MCH, system memory controller,
`and memory subsystem are used generally interchangeable
`throughout this disclosure, and the terms memory module,
`memory subsystem controller, and local memory controller
`are used generally interchangeably throughout this disclo-
`sure.
`
`FIG. 1 illustrates an example host computer system 16
`including an example memory module 10 according to
`certain embodiments described herein. The memory module
`10 can comprise at least one output 12 configured to be
`operatively coupled to a system memory controller 14 of the
`host computer system 16.
`In certain embodiments,
`the
`memory module 10 is configured to operate in at least two
`modes comprising an initialization mode during which the
`memory module 10 executes at
`least one initialization
`sequence, and an operational mode. The memory module 10
`may further include a controller circuit 18. In some embodi-
`ments, the controller circuit 18 is configured to cause the
`memory module 10 to enter the initialization mode. The
`memory module 10 can further include a notification circuit
`20 configured to drive the at least one output 12 while the
`memory module 10 is in the initialization mode to provide
`at least one notification signal to the memory controller 14
`indicating at least one status of the at least one initialization
`sequence.
`The memory module 10 may comprise a printed-circuit
`board (PCB) 22.
`In certain embodiments,
`the memory
`module 10 has a memory capacity of512-MB, 1-GB, 2-GB,
`4-GB, 8-GB, 16-GB, or higher. Other memory capacities are
`also compatible with certain embodiments described herein.
`In addition, memory modules 10 having widths of 4 bytes,
`8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits, 256
`bits, as well as other widths (in bytes or in bits), are
`compatible with embodiments described herein. The PCB
`22 can have an industry-standard form factor. For example,
`the PCB 22 can have a low profile (LP) form factor with a
`height of 30 millimeters and a width of 133.35 millimeters.
`In certain other embodiments, the PCB 20 has a very high
`profile (VHP) form factor with a height of 50 millimeters or
`more. In certain other embodiments, the PCB 22 has a very
`low profile (VLP) form factor with a height of 18.3 milli-
`meters. Other form factors including, but not limited to,
`small-outline (SO-DIMM), unbuffered (UDIMM), regis-
`tered (RDIMM), fully-buffered (FBDIMM), mini-DIMM,
`mini-RDIMM, VLP mini-DIMM, micro-DIMM,
`and
`SRAM DIMM are also compatible with certain embodi-
`ments described herein. In other embodiments, certain non-
`DIMM form factors are possible such as, for example, single
`in-line memory module (SIMM), multi-media card (MMC),
`and small computer system interface (SCSI).
`In certain embodiments, the memory module 10 is opera-
`tively coupled to (e.g., in electrical communication with) the
`host computer system 16. In certain other embodiments, the
`memory module 10 may communicate with the host com-
`puter system 16 using some other type of communication,
`
`
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`5
`such as, for example, optical communication. Examples of
`host computer systems 16 include, but are not limited to,
`blade servers, 1U servers, personal computers (PCs), and
`other applications in which space is constrained or limited.
`The PCB 22 can comprise an interface (not shown) that is
`configured to be in electrical communication with the host
`computer system 16. For example, the interface can com-
`prise a plurality of edge connections which fit into a corre-
`sponding slot connector of the host system 16. The interface
`of certain embodiments provides a conduit for power volt-
`age as well as data, address, and control signals between the
`memory module 10 and the host system 16. For example, the
`interface can comprise a standard 240-pin DDR2 edge
`connector. The at least one output 12 may be routed over the
`interface, for example.
`The memory module 10 may also comprise one or more
`memory elements (not shown), such as dynamic random-
`access memory (DRAM) elements, for example. Types of
`DRAM elements compatible with certain embodiments
`described herein include, but are not
`limited to, DDR,
`DDR2, DDR3, DDR4, and synchronous DRAM (SDRAM).
`In addition, memory elements having bit widths of 4, 8, 16,
`32, as well as other bit widths, are compatible with certain
`embodiments described herein. Memory elements compat-
`ible with certain embodiments described herein have pack-
`aging which include, but are not limited to, thin small-
`outline package (TSOP), ball-grid-array (BGA), fine-pitch
`BGA (FBGA), micro-BGA (uBGA), mini-BGA (mBGA),
`and chip-scale packaging (CSP). In certain embodiments,
`the memory module 10 may also include one or more
`non-volatile memory elements, such as one or more flash
`memory elements. Types of flash memory elements com-
`patible with certain embodiments described herein include,
`but are not limited to, NOR flash, NAND flash, ONE-NAND
`flash, and multi-level cell (MLC).
`The controller circuit 18 of certain embodiments gener-
`ally controls the operation of the memory module 10. For
`example, the controller circuit 18 may control the memory
`elements of the memory module 10 and/or communicate
`with the system memory controller 14. For example, the
`controller circuit 18 may receive and process address and
`command signals (e.g., read, write commands) from the
`system memory controller 14 and transmit appropriate
`address and commands to the memory elements in response.
`See, e.g., US. Pat. Appl. Publ. Nos. 2006/0062047 A1 and
`2006/0262586 A1, each of which is incorporated in its
`entirety by reference herein. In certain embodiments, the
`controller circuit 18 comprises a local memory controller.
`Additionally, depending on the architecture of the memory
`module 10, such as for an FB-DIMM, the controller circuit
`18 may comprise an advanced memory bulfer (AMB). The
`controller circuit 18 can comprise one or more of a field-
`programmable gate array (FPGA), a programmable-logic
`device (PLD), an application-specific integrated circuit
`(ASIC), a custom-designed semiconductor device, and a
`complex programmable logic device (CPLD), for example.
`In certain embodiments, the controller circuit 18 comprises
`various discrete electrical elements, while in certain other
`embodiments, the controller circuit 18 comprises one or
`more integrated circuits.
`As discussed, the memory module 10 is configured to
`operate in at least two modes comprising an initialization
`mode during which the memory module 10 executes at least
`one initialization sequence, and an operational mode. In one
`embodiment, for example,
`the at
`least one initialization
`sequence may comprise one or more training sequences. The
`initialization sequence (e.g., comprising one or more train-
`
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`ing sequences) may be initiated by the system memory
`controller 14. In some embodiments, the controller circuit 18
`is configured to cause the memory module 10 to enter the
`initialization mode. For example, the controller circuit 18
`may be configured to execute a routine implementing the at
`least one initialization sequence when the appropriate signal
`or command is received from the memory controller 14 or
`is otherwise received from the host computer system 16
`(e.g., upon receipt of a reset signal).
`In certain embodiments, for example, the computer sys-
`tem 16 is coupled to a plurality of memory modules 10, 26
`including the memory module 10 and at least a second
`memory module 26, and the memory controller 14 (e.g.,
`MCH) trains each module 10, 26 separately, in series. In one
`example scenario, the memory controller 14 issues a first
`command to the memory module 10, and, in response, the
`memory module 10 executes an initialization sequence (e. g.,
`one or more training sequences). Upon completion of the
`initialization sequence, the first memory module 10 advan-
`tageously issues a notification to the memory controller 14
`in accordance with embodiments described herein.
`In
`
`response, the memory controller 14 issues a second com-
`mand, this time to the memory module 26, and, in response,
`the memory module 26 executes an initialization sequence
`(e.g., one or more training sequences). Upon completion of
`the initialization sequence, the second memory module 26,
`similar to the first memory module 10, advantageously
`issues a notification to the memory controller 14 in accor-
`dance with embodiments described herein.
`In response,
`where there are more than two memory modules 10, 26, the
`memory controller 14 issues a third command to a third
`memory module (not shown), and so forth. One example
`computer system 16 capable of implementing such a sce-
`nario is configured to execute an Intel Basic Input/Output
`System (BIOS), and comprises a plurality of memory mod-
`ules 10, 26 having an LRDIMM configuration. In such an
`example system, the Intel BIOS causes the system memory
`controller 14 to initialize the LRDIMM memory modules
`10, 26 serially.
`The operational mode is the normal mode of the memory
`module 10. For example, during the operational mode, the
`memory module 10 is generally accessed by the system
`memory controller 14 of the host computer 16 during
`standard computer operation not associated with initializa-
`tion. For example, the system memory controller 14 may
`cause the memory module 10 to perform standard operations
`such as memory read/write, pre-charge, refresh, etc., while
`in operational mode, although it will be appreciated that one
`or more of these operations can also be performed by the
`memory module 10 while in initialization mode in certain
`embodiments.
`
`The notification circuit 20 can be configured to drive the
`at least one output 12, while the memory module 10 is in the
`initialization mode or after the memory module 10 com-
`pletes one or more initialization sequences, to provide the at
`least one notification signal to the memory controller 14
`indicating at least one status of the at least one initialization
`sequence. While shown in FIGS. 1-3 as forming a part of the
`controller circuit 18, the notification circuit 20 may be a
`physically and/or
`logically separate circuit
`in certain
`embodiments. While a variety of configurations are possible,
`the notification circuit 20 may comprise one or more tran-
`sistors, one or more logic elements (e.g., AND, OR, NOR,
`NAND, XOR gates, and the like), or a combination thereof.
`In some embodiments, the notification circuit 20 may addi-
`tionally or alternatively comprise one or more of an FPGA,
`
`
`
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`Case 6:20-cv-00194-ADA Document 1—1 Filed 03/17/20 Page 10 of 15
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`US 9,858,218 B1
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`7
`PLD, CPLD, ASIC, custom-designed semiconductor device,
`discrete electrical elements, and an integrated circuit.
`The at least one status of certain embodiments comprises
`completion of the at least one initialization sequence, such
`that the at least one notification signal is indicative of the
`completion of the at least one initialization sequence. The at
`least one status of certain embodiments comprises execution
`of the at least one initialization sequence. For example, the
`at least one status may indicate that the at least one initial-
`ization sequence is currently being executed.
`In some
`embodiments, the at least one status may provide an indi-
`cation that a certain task has been completed by the memory
`module 10, such as a training task requested by the system
`memory controller 14. In certain embodiments, the notifi-
`cation circuit 20 can be configured to drive the at least one
`output 12 to a first state indicative of execution of the at least
`one initialization sequence or to a second state indicative of
`completion of the at least one initialization sequence. As one
`example, the first state may be a high or low logic level, and
`the second state may be a high impedance state. In another
`case, the first state is a high or low logic level, and the
`second state is the inverse logic level of the first state.
`The at least one output 12 of certain embodiments is
`configured to be operatively coupled to at least one interrupt
`of the system memory controller 14, and the system memory
`controller 14 is responsive to the at least one notification
`signal indicating completion of the at least one initialization
`sequence. For example, the system memory controller 14
`may trigger execution of an interrupt routine upon receipt of
`the notification signal on the output 12. The interrupt routine
`generally executes the appropriate operations for the at least
`one status indicated by the at least one notification signal.
`For example, if the at least one status indicates that the at
`least one initialization sequence is complete, execution of
`the interrupt routine may cause the system memory control-
`ler 14 to notify the host computer system 16 that the system
`initialization, or a portion thereof,
`is completed. In one
`embodiment, for example, the execution of the interrupt
`routine cau