Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 1 of 12
` Exhibit 5


`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 2 of 12
`(12) United States Patent
`De Jong et al.
`US 6,807,505 B2
`Oct. 19, 2004
`(10) Patent No.:
`(45) Date of Patent:
`(75) Inventors: Franciscus G. M. DeJong, Eindhoven
`(NL); Mathias N. M. Muris,
`Eindhoven (NL); Robertus M. W.
`Raaijmakers, Eindhoven (NL);
`Guillaume E. A. Lousberg, Eindhoven
`(73) Assignee: Koninklijke Philips Electronics N.V.,
`Eindhoven (NL)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(*) Notice:
`(21) Appl. No.: 10/621,002
`(22) Filed:
`Jul. 16, 2003
`Prior Publication Data
`US 2004/0059535 A1 Mar. 25, 2004
`Related U.S. Application Data
`(62) Division of application No. 09/402,154, filed as application
`No. PCT/IB99/00172 on Jan. 29, 1999, now Pat. No. 6,622,
`Foreign Application Priority Data
`Feb. 22, 1998
`(EP) ............................................ 98.20O288
`May 6, 1998
`(EP) ............................................ 982O1482
`Nov. 30, 1998
`(EP) ............................................ 982O4042
`(51) Int. Cl. ................................................ G01R 31/28
`(52) U.S. Cl. ........................................ 702/118; 324/500
`(58) Field of Search ............................. 702/57–59, 108,
`702/117, 118; 324/500, 512, 527; 326/16,
`106; 714/25, 27, 30, 718, 719, 726, 727,
`References Cited
`5,103,450 A * 4/1992 Whetsel ...................... 714/724
`5,416.409 A * 5/1995 Hunter ..........
`... 324/158.1
`5,781,559 A * 7/1998 Muris et al. ................ 714/726
`3/1994 ........... GO1 R/31/04
`2278689 A * 12/1994 ........... GO1 R/31/28
`* cited by examiner
`Primary Examiner Marc S. Hoff
`Assistant Examiner-Craig Steven Miller
`An electronic circuit comprises a plurality of input/output
`(I/O) nodes for connecting the electronic circuit to a further
`electronic circuit via interconnects. A main unit implements
`a normal mode function of the electronic circuit. A test unit
`tests the interconnects. The electronic circuit has a normal
`mode in which the I/O nodes are logically connected to the
`main unit and a test mode in which the I/O nodes are
`logically connected to the test unit. In the test mode the test
`unit is operable as a low complexity memory via the I/O
`9 Claims, 3 Drawing Sheets
`130 KA


`U.S. Patent
`Oct. 19, 2004
`Sheet 1 of 3
`US 6,807,505 B2
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 3 of 12


`U.S. Patent
`Oct. 19, 2004
`Sheet 2 of 3
`US 6,807,505 B2
`FG. 3
`Input bus (1:n)
`Output buS (1:m)
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 4 of 12


`U.S. Patent
`Oct. 19, 2004
`Sheet 3 of 3
`US 6,807,505 B2
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 5 of 12


`US 6,807,505 B2
`This application is a divisional of Ser. No. 09/402,154
`filed Sep. 29, 1999 now U.S. Pat. No. 6,622,108 which is a
`371 of PCT/IB99/00172 filed Jan. 29, 1999.
`The invention relates to an electronic circuit comprising:
`a plurality of input/output (I/O) nodes for connecting the
`electronic circuit to a further electronic circuit via
`interconnects, a main unit for implementing a normal mode
`function of the electronic circuit, and a test unit for testing
`the interconnects, the electronic circuit having a normal
`mode in which the I/O nodes are logically connected to the
`main unit and a test mode in which the I/O nodes are
`logically connected to the test unit.
`The invention further relates to a method of testing
`interconnects between a first electronic circuit and a Second
`electronic circuit, the first electronic circuit comprising a
`main unit implementing a normal mode function of the first
`electronic circuit, and a test unit for testing the
`interconnects, the method comprising the Steps of logically
`connecting the test unit to the interconnects, and putting test
`data on the interconnects by the Second electronic circuit.
`Such a circuit is known from "Boundary-Scan test, a
`practical approach”, H. Bleeker, P. van den Eijnden and F. de
`Jong, Kluwer, Boston, 1993, ISBN 0-7923-9296-5, FIGS.
`1-19, which shows an integrated (IC) in accordance with the
`boundary-scan test standard IEEE Std. 1149.1. The known
`circuit has a main unit or core logic that is responsible for
`providing Some arbitrary Specified function in a normal
`mode of the circuit. The known circuit further has a test unit
`for in a test mode performing an interconnect test, i.e. a test
`whether the circuit is properly connected to a further circuit
`via its I/O nodes or IC pins. Efficient interconnect test of
`miniaturised and/or complex circuit assemblies is a neces
`Sary part of the production process of Such assemblies. The
`boundary-Scan test technique is accepted as Standardised
`Solution for interconnect test. It is available in most of the
`leading microprocessor families and is Supported for
`in-house developed application Specific ICs through auto
`mated tools in the IC design process.
`The test unit of the known boundary-Scan circuit includes
`a test control unit or Test Access Port controller and a shift
`register or boundary-Scan register along the circuit
`boundary, cells of the shift register being connected to I/O
`nodes corresponding to the interconnects to be tested. The
`test control unit has a State machine controlling States of the
`shift register, examples of Such States being a shift State for
`shifting in/out data into the shift register and a capture State
`for capturing data originating from the interconnects into the
`shift register. The shift register is accessible from outside the
`circuit via a Test Data In (TDI) node and a Test Data Out
`(TDO) node. A Test Clock signal (TCK) and a Test Mode
`Select signal (TMS) are provided from outside the circuit to
`the test control unit for Stepping through the various States.
`In the normal mode of the known circuit, the I/O nodes are
`logically connected to the main unit, thereby allowing the
`circuit to perform its normal mode function. In the test mode
`of the known circuit, the I/O nodes are logically connected
`to the test unit, thereby giving the test unit access to the
`Provided that also the further circuit is equipped with a
`test unit in accordance with the boundary-Scan test Standard,
`the interconnects between the two circuits can be tested
`according to the Standard boundary-Scan test method.
`Hereto, appropriate test data is first shifted into the shift
`registers of the two circuits and is Subsequently applied to
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 6 of 12
`the interconnects. Then, response data originating from the
`interconnects is captured into the shift registers and Subse
`quently shifted out of the shift registers for observation.
`From the response data it can be determined whether the
`circuits are properly interconnected. For a single intercon
`nect this means that to one of its ends a signal is applied and
`at the other end it is observed whether that signal is
`transmitted. In this way, an open circuit in an interconnect
`can be found. Additionally, a number of test patterns will be
`applied to the interconnects in order to check for short
`circuits between neighbouring interconnects, or between an
`interconnect and a power Supply line. ESSentially, intercon
`nect testing comes down to applying test data to one end of
`an interconnect and observing response data at another end,
`in Such a way that open circuits and Short circuits are
`A problem with the boundary-Scan approach is that for
`Some circuits pin count and pin compatibility considerations
`inhibit the addition of extra pins to a circuit design for the
`TCK, TMS, TDI, TDO and the optional TRSTN signals.
`Moreover, the price-pressure in Some Semiconductor fields
`is Such that it is considered to be too expensive to reserve
`area for interconnect test of the size as required by
`boundary-Scan circuitry.
`It is an object of the invention to provide a circuit as
`Specified in the preamble, that allows interconnect testing
`with reduced overhead in terms of required I/O nodes and/or
`area. This object is achieved according to the invention in an
`electronic circuit, which is characterised in that in the test
`mode the test unit is operable as a low complexity memory
`via the I/O nodes. Low complexity memories are those
`memories that do not have to be put through a complex
`initialisation process before they can be accessed, and that
`have simple acceSS protocols without dynamic restrictions.
`Such a test unit enables an alternative procedure for apply
`ing test data to one end of an interconnect and observing
`response data at the other end. If the low complexity
`memory has a read-only character and holds pre-stored test
`data at a number of addresses, the test unit produces this
`pre-stored test data at its Side of the interconnects when
`address data and appropriate control data are applied to it by
`the further circuit via the interconnects. The further circuit
`then receives response data, which should be identical to the
`pre-stored test data. In this way, both the interconnects that
`are used to carry the address and control data and the
`interconnects that are used to carry the pre-stored data itself
`are tested. It is important that particular input data for the test
`unit, i.e. the address, result in output data from the test unit
`that are known a priori, i.e. the Stored data. If the low
`complexity memory allows both read and write access, the
`further circuit can apply test data to its Side of the intercon
`nects in a write mode of the test unit, thereby Storing the test
`data in the test unit. In a Subsequent read mode of the test
`unit, the further circuit can read back response data.
`Whether the test unit has a read-only or a read/write
`behaviour, it does not need a State machine like the
`boundary-Scan State machine and can therefore be imple
`mented consuming leSS area. Moreover, the simple operation
`of the test unit allows less pins or even no pins at all to be
`reserved for controlling the test unit in the test mode. For
`both a read-only and a read/write test unit, a Subset of the
`interconnects is used as a data bus for exchanging the
`Storage data. At least in the case that the test unit has a
`read/write behaviour, a further Subset of the interconnects is
`used as a control bus, including, for example, control lines
`for controlling the read and/or write process. At least in the
`case that the test unit has a read-only behaviour, a still


`further Subset of the interconnects is used as an address bus
`for Selecting the Storage location to read from. An important
`aspect of the invention is that one is free how to map the data
`bus, the control bus and/or the address bus on the intercon
`nects to be tested.
`Access to the control bus, the address bus, and the data
`bus during test mode could be provided, for example, Via
`boundary-scan circuitry of the further circuit. Then, with
`ordinary boundary-Scan test equipment, data can be shifted
`in and out of the further circuit. In this way, data to be
`Supplied to the control bus and/or the address bus and data
`returned by the test unit on the data bus can be handled. As
`a further example, if the further circuit is a programmed
`microprocessor or Application-Specific IC (ASIC), the fur
`ther circuit could perform the interconnect test in a Stand
`alone fashion, without the need for external equipment for
`feeding the further circuit with the test data and for evalu
`ating the response data. It is noted that the further circuit
`alternatively could consist of two or more Separate circuits,
`together operating the test unit as a low complexity memory.
`An embodiment of the electronic circuit according to the
`invention is defined in claim 2. A Read-Only Memory
`(ROM) is a suitable device for holding the data required by
`the interconnect test. When control data, in the form of an
`address and, if necessary, a limited number of further control
`Signals, is applied to the circuit, the ROM outputS data
`pre-stored at that address on the data bus. It will be clear that
`in this way both the data bus, the address bus and, if present,
`the control bus are tested. A Small number of test patterns
`pre-stored in the ROM would normally suffice for an inter
`connect test capable of detecting open circuits in intercon
`nects and short circuits between interconnects. It will further
`be clear that for the test unit being operable as a low
`complexity memory, it is not required that the test unit is
`implemented as a real ROM table. Especially if only a small
`number of test patterns is used, the test unit could be
`implemented as a combinatorial circuit, leading to more
`efficient area usage.
`An embodiment of the electronic circuit according to the
`invention is defined in claim 3. In relation with Such a
`read/write register, the control bus at least controls whether
`the register is in a read mode or in a write mode, and the data
`bus is used for both Supplying the data to be written to the
`test unit and for receiving the data to be read back from the
`test unit. In this embodiment, no address bus is needed since
`only a single register is used.
`An embodiment of the electronic circuit according to the
`invention is defined in claim 5. The test circuit of this
`embodiment requires comparatively little area of the Sub
`Strate on which it is manufactured. Furthermore, it enables
`to test the interconnects in a single type of test and with a
`very good test coverage, i.e. a Small Set of patterns Suffices
`to detect the possible defects in the interconnects.
`Furthermore, the diagnostic resolution of the test is very
`good Since almost all faults have a unique signature.
`High complexity memory devices are those devices
`which have complex protocols for reading from and writing
`into their memory array. Therefore, as opposed to low
`complexity memories, high complexity memories are not
`Suited as test units for interconnect testing, as the process of
`eXchanging data is too complex and therefore takes too
`much time. Examples of high complexity memory devices
`are Synchronous Dynamic Random Access memories
`(SDRAMs) and non-volatile memory like flash memory
`devices. Besides complex access protocols, high complexity
`memories often need initialisation and have dynamic restric
`tions. The initialisation is troubleSome for testing because
`US 6,807,505 B2
`(almost) all control lines and address lines have to be
`connected correctly to Succeed in initialisation. Although
`interconnect problems with control and address lines can be
`detected because the failing initialisation will block all
`access to the devices, the diagnosis of the failure, i.e. exactly
`which of the pins is not connected correctly has a very low
`The dynamic restrictions of SDRAMs, usually identified
`by the refresh time and the maximum RAS pulse width,
`hamper interconnect test because the test patterns (i.e.
`writing into and reading from the memory array) have to
`meet the dynamic requirements. The Speed of application of
`test patterns using a boundary-Scan circuit is determined by
`the length of the boundary-Scan register and the maximum
`test clock frequency. The test clock frequency is determined
`either by the circuit implementation of the boundary-Scan
`circuit in the ICs on the board or by the maximum speed of
`the boundary-Scan tester.
`For these reasons, high complexity memories form a
`class of circuits that could very well benefit from adding a
`low complexity memory for enabling efficient interconnect
`testing. This is especially true because boundary-Scan is
`hardly available in memory devices due to pin count and/or
`pin compatibility considerations.
`An embodiment of the circuit according to the invention
`is described in claim 6. This particular way of activating the
`test mode is possible because in most SDRAMs the first
`action to be performed after power up is prescribed to be a
`write action. Thus at power up, by utilising the read action
`for activating the test mode, the normal operation of the
`SDRAM is not effected. As an alternative, the circuit in
`accordance with the invention can be brought into test mode
`via a particular combination of input Signals on the I/O
`nodes, or via a dedicated node that is dedicated to this
`Non-volatile memories like flash memory devices ham
`per interconnect test, because writing into the memory array
`for test purposes is not allowed when the device is already
`pre-programmed. This test would destroy the functional
`data. An un-programmed device can be written into but has
`to be erased afterwards. Erasure of large memory blocks can
`take up to Several Seconds, lengthening considerably the
`board interconnect test.
`By including a test unit in accordance with the invention,
`high complexity memories, including non-volatile
`memories, can undergo an efficient interconnect test. One
`could use the normal mode data bus, address bus and/or
`control bus for the test mode as well. To also test intercon
`nects that provide Signals that are specific for the high
`complexity memory functionality, and therefore are not
`needed to control the test unit in the test mode, either the
`data bus or the address bus can be extended with these
`interconnects. The invention enables interconnect testing
`using test patterns which take only milliseconds to execute
`and for which test pattern generators are commercially
`Low complexity memory types like Static Random
`Access Memories (SRAMs) and (Programmable) ROMs
`can readily be tested for their connectivity using neighbour
`ing circuits equipped with boundary-Scan or neighbouring
`microprocessors and/or ASICS. For interconnect testing of
`Such low complexity memories no extra measures in the
`form of added test units have to be taken.
`It is a further object of the invention to provide a method
`as Specified in the preamble, which performs the intercon
`nect test with reduced overhead in terms of required I/O
`nodes and/or area. This object is achieved according to the
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 7 of 12


`US 6,807,505 B2
`because of the required extra pins. Another reason for not
`using boundary-Scan for interconnect testing of devices like
`circuit 100 is the enormous preSSure on cost. As a result, the
`IC area available for extra features like interconnect testing
`is very limited. In accordance with the invention, as an
`alternative to an ordinary boundary-Scan test unit, the test
`unit 120 is operable as a low complexity memory. Such a test
`unit can be implemented very efficiently in terms of IC area
`and requires leSS or even Zero extra pins.
`A low complexity memory can have a read-only behav
`iour or a read/write behaviour. In accordance with the
`invention, a test unit has either kind of behaviour, or both
`kinds of behaviour in Subsequent phases of an interconnect
`test. In the circuit 100, during a first part of a preferred
`interconnect test, the test unit 120 has a read-only behaviour
`and during a Subsequent Second part of the interconnect test,
`the test unit 120 has a read/write behaviour. This two-step
`approach enables a thorough interconnect test that is espe
`cially suited for SDRAMs like the circuit 100. The first part
`of the interconnect test aims at testing the address bus of the
`circuit 100 and is functionally described by:
`1. After power up of the circuit 100, a test mode is active
`which allows read access to the test unit 120. The test unit
`120 is then operable as a ROM table. Alternatively, the
`test mode is activated by other means, Such as a particular
`combination or Sequence of Signals applied to the I/O
`nodes 130, 140 of the circuit 100.
`2. Read access to the test unit 120 is controlled by CSn=0,
`OEn=0 and WEn=1, and validated by a defined edge of
`the CLK and active level of the clock enable CKE.
`3. The test unit's ROM table is addressed by the extended
`address bus which is defined as the actual address bus,
`extended with the control signals RAS, CAS, DQML and
`4. The width of the ROM table is equal to the width of the
`data bus plus possible additional outputs of the circuit
`5. Each of the primary addresses (all but one address bits
`equal to 0, one address bit equal to 2) reads the all 1
`data word. All other extended addresses read the all '0'
`data word.
`The table below shows the contents of the ROM table for
`the SDRAM device of circuit 100, with 12 bit wide address
`bus, RAS, CAS, DOML and DQMU and four data pins.
`invention in a method, which is characterised in that the
`putting Step comprises operating the first electronic circuit as
`a low complexity memory by the Second electronic circuit.
`Although the invention is presented in the context of
`boundary-Scan testing, which mainly applies to testing inter
`connects between ICS on a carrier, Such as a printed circuit
`board (PCB), the principles of the invention are equally
`applicable to the testing of interconnects between any two
`circuits, Such as interconnects between cores within a Single
`IC or interconnects between ICs on distinct PCBs that are
`inserted into a cabinet.
`The invention and its attendant advantages will be further
`elucidated with the aid of exemplary embodiments and the
`accompanying Schematic drawings, whereby:
`FIG. 1 shows an embodiment of a circuit in accordance
`with the invention,
`FIG. 2 shows a way to provide access during intercon
`nect test to a circuit that is testable in accordance with the
`FIG. 3 shows a further way to provide access during
`interconnect test to a circuit that is testable in accordance
`with the invention,
`FIG. 4 shows an alternative embodiment of the
`FIG. 5 schematically shows the test unit for five inputs
`and two outputs, and
`FIG. 6 schematically shows an alternative for the test unit
`for five inputs and two outputs.
`Corresponding features in the various Figures are
`denoted by the same reference Symbols.
`FIG. 1 shows an embodiment of a circuit 100 in accor
`dance with the invention. The circuit 100 has I/O nodes 130,
`140, through which the circuit 100 is connectable to external
`circuits. An I/O node may be an input node, i.e. a node only
`Suitable to receive Signals, an output node, i.e. a node only
`Suitable to Send Signals, or a bi-directional node, i.e. a node
`Suitable to either receive or Send Signals. For performing its
`intended normal mode function, the circuit 100 has a main
`unit 110, which is, by way of example, assumed to be an
`SDRAM. Thus, the circuit 100 is in fact an SDRAM device.
`It is further assumed that the circuit 100 is part of an
`assembly, whereas interconnects between the circuit 100 and
`further parts of the assembly should be testable. Hereto, the
`circuit 100 has a test unit 120, which is connected to the
`main unit 110 via in parallel connections and to the I/O nodes
`130. In a normal mode of the circuit 100, the test unit 120
`is transparent, and Signals can pass freely between the I/O
`nodes 130 and the main unit 110. In a test mode of the circuit
`100, the main unit 110 is logically disconnected from the I/O
`nodes 130 and the test unit 120 is in control. It is noted that
`preferably, but not necessarily, all I/O nodes are arranged for
`interconnect testing. To indicate this, the I/O nodes 140 are
`not connected to the test unit 120, and therefore, the test unit
`120 does not offer testability for interconnects correspond
`ing to these I/O nodes 140.
`SDRAM devices have a highly standardised pin lay-out.
`FIG. 1 does not give an exact representation of Such a
`pin-layout, but it Schematically shows which I/O nodes are
`generally present on an SDRAM device. The circuit 100 has
`a data bus D0-D3, an address bus A0-A11, and a control bus
`including a Chip Select pin (CSn), an Output Enable pin
`(OEn), Write Enable pin (WEn), Clock pin (CLK), Clock
`Enable pin (CKE), Row Address Strobe pin (RAS), Column
`Address Strobe pin (CAS), and Data I/O Mask pins (DQML
`and DQMH). The precise functions of these pins are not
`relevant for the invention. However, the standardised pin
`lay-out obstructs the addition of boundary-Scan circuitry
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 8 of 12
`extended address
`data bus
`"any other address'
`With the above described functional behaviour of the
`circuit 100 after power up, an efficient test for the extended


`address bits consist of just reading all primary addresses (16
`in the above case) and one other address. The test Sequence
`covers the following faults:
`1. any Stuck-at 1 on an extended address pin
`2. any Stuck-at 0 on an extended address pin
`3. any 2-net AND-type short between any pair of address
`4. any 2-net OR-type short between any pair of address pins
`5. any Stuck-at 1 on a data pin
`6. any Stuck-at 0 on a data pin
`An interconnect with a stuck-at fault remains at either
`logic high or logic low, no matter what Signals are applied
`to it. A 2-net AND-type short between a first and a second
`interconnect causes the two interconnects to carry the same
`logic value as determined by either one of the interconnects.
`A 2-net OR-type short between a first and a second inter
`connect causes the two interconnects to carry complemen
`tary logic values as determined by either one of the inter
`The above test Sequence provides a diagnostic resolution
`down to a single pin. Note that this test concept is indepen
`dent from the number of extended address lines or the
`number of data lines, nor is there any relation assumed
`between the two numbers.
`The Second part of the interconnect test aims at testing for
`Shorts between the interconnects making up the data bus,
`and is functionally described by:
`1. Write acceSS is provided to a command register, which is
`loaded with the value of the (actual) address bus.
`2. There will be a certain combination of address bits, which,
`after being loaded into the aforementioned command
`register, Select a Single write/read register that logically
`forms part of the test unit, with a width equal to the width
`of the data bus. This combination of address bits is to be
`determined by the manufacturer of the device and to be
`Specified in the data Sheet.
`This single write/read register can then be used to write
`data and read data. Algorithms are available to generate a
`minimal set of test patterns which cover all AND-type and
`OR-type shorts between any pair of data lines. The table
`below shows a set of test patterns for a 16-bit wide data bus.
`Case 6:21-cv-00263-ADA Document 1-5 Filed 03/16/21 Page 9 of 12
`For dynamic memory devices, like the circuit 100, the
`above described two parts of the interconnect test have read
`and write access to the test unit which is not affected with
`any dynamic requirements. It will be clear that many vari
`ants can be imagined to either part. Moreover, one can also
`choose to implement only one of the above described two
`parts of the interconnect test. For flash devices, for example,
`the first part of the interconnect test is applicable for
`unprogrammed devices. The manufacturer may choose not
`to offer this facility for already programmed devices, to
`accomplish compatibility with EPROM devices (these
`access the main memory array when a first read is done after
`power up).
`US 6,807,505 B2
`AS mentioned above, the mechanism for Switching the
`circuit from the normal mode into the test mode may be
`implemented in different ways. In the SDRAM embodiment,
`the circuit is brought into the test mode by performing a read
`action after power up. Such a read action after power up, is
`a special action which does not form part of the normal
`actions for the circuit and has been given the Special
`meaning of a command for Switching into the test mode. In
`general, any pattern or Sequence of patterns applied to one
`or more I/O nodes of the circuit can be given the Special
`meaning of a command for going into test mode, provided
`that this pattern or Sequence is not used in the normal mode
`of the circuit. An alternative is to provide the circuit with a
`dedicated test control node, in addition to the I/O nodes, to
`control whether the circuit is to behave in the normal
`operational mode or in the test mode. The actual Signal value
`on the test control node, in relation with predefined values
`corresponding to the respective modes, brings the circuit
`into the desired mode.
`FIG. 2 shows a way to provide acceSS during interconnect
`test to a circuit 200 that is testable in accordance with the
`invention. The circuit 200 includes a test unit 205 that is
`operable as a low complexity memory. A neighbouring
`circuit 210, which has boundary-Scan circuitry, can provide
`data to and receive data from the circuit 200 via a control and
`address bus 220 and a bi-directional data bus 230.
`Alternatively, when only a ROM behaviour is implemented
`in the test unit 205, the data bus 230 would be unidirectional,
`i.e. from the circuit 200 to the circuit 210.
`A number of interconnects make up the control and
`address bus 220 and the data bus 230. The function of these
`interconnects during a normal mode is irrelevant for the
`invention. When the circuit 200 is a memory device, there
`will also be a 'normal mode data bus. The test mode data
`bus 230 could partly or completely coincide with the normal
`mode data bus. The Same applies to the control and address
`buS 220.
`Via a boundary-scan chain 240 data is shifted into circuit
`210, that data making up read and/or write commands to be
`supplied to the circuit 200. After a read command, the
`boundary-Scan chain 240 captures data Supplied to the data
`bus 230 by the circuit 200. That data Subsequently are
`shifted out to be analysed externally.
`FIG. 3 shows a further way to provide access during
`interconnect test to a circuit 300 that is testable in accor
`dance with the invention. The circuit 300 includes a test unit
`305 that is operable as a low complexity memory via control
`and address bus 320 and data bus 330. A neighbouring
`circuit 310, which is a microprocessor, executes the program
`with the necessary read and write commands. The test
`program and the test data are stored in a memory 340 of the
`circuit 310. Preferably, the circuit 310 also analyses the data
`obtained from the circuit 300. The circuit 310 could alter
`natively be an ASIC.
`The above presented design-for-test method does not
`require any additional pins to the device for test access,
`meeting pin count and pin compatibility requirements of this
`type of memories. Silicon area overhead is limited to the
`(Small) ROM table, or functional equivalent, the read/write
`data register (possibly to be combined with existing logic)
`and the associated decoding logic. Standardisation of this
`approach by a body like EIS or JEDEC would ensure
`compatibility between devices from different manufacturers.
`Boundary-Scan is the preferred design-for-test method for
`testing interconnects on assemblies with ICS. It can be used
`to efficiently test all interconnects between devices with


`US 6,807,505 B2
`The example below is a description of the test unit for an

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