Case: 21-1826 Document: 54 Page: 1 Filed: 11/15/2022
`
`United States Court of Appeals
`for the Federal Circuit
`______________________
`
`VLSI TECHNOLOGY LLC,
`Appellant
`
`v.
`
`INTEL CORPORATION,
`Appellee
`______________________
`
`2021-1826, 2021-1827, 2021-1828
`______________________
`
`Appeals from the United States Patent and Trademark
`Office, Patent Trial and Appeal Board in Nos. IPR2019-
`01198, IPR2019-01199, IPR2019-01200.
`______________________
`
`Decided: November 15, 2022
`______________________
`
`NATHAN NOBU LOWENSTEIN, Lowenstein & Weather-
`wax LLP, Santa Monica, CA, argued for appellant. Also
`represented by KENNETH J. WEATHERWAX.
`
` S. CALVIN WALDEN, Wilmer Cutler Pickering Hale and
`Dorr LLP, New York, NY, argued for appellee. Also repre-
`sented by JEFFREY ANDREW DENNHARDT; MARK
`CHRISTOPHER FLEMING, JOHN V. HOBGOOD, STEPHANIE LIN,
`Boston, MA; RONALD GREGORY ISRAELSEN, Washington,
`DC.
` ______________________
`
`
`

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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`Before CHEN, BRYSON, and HUGHES, Circuit Judges.
`BRYSON, Circuit Judge.
`Appellee Intel Corporation filed three petitions for in-
`ter partes review (“IPR”) of U.S. Patent No. 7,247,552 (“the
`’552 patent”), which is owned by appellant VLSI Technol-
`ogy LLC. The Patent Trial and Appeal Board instituted
`the IPR proceedings, and in a combined Final Written De-
`cision, the Board found all of the challenged claims of the
`’552 patent to be unpatentable. For the reasons set forth
`below, we affirm in part, reverse in part, and remand.
`I
`A
`The ’552 patent is directed to “[a] technique for allevi-
`ating the problems of defects caused by stress applied to
`bond pads” of an integrated circuit. ’552 patent, Abstract.
`An integrated circuit, sometimes referred to as a “chip”
`or “die,” contains numerous electronic circuits that are in-
`tegrated on a flat piece of semiconductor called a “sub-
`strate.” The specification of the ’552 patent discloses an
`integrated circuit that includes several metal “interconnect
`layers” positioned above the substrate and frequently sur-
`rounded by “dielectric” or insulating material. See id. at
`col. 3, ll. 1–10 & Fig. 1. The integrated circuits described
`in the ’552 patent also include one or more “bond pads” that
`sit above the interconnect layers and are used to attach the
`chip to another electronic component, such as a computer
`motherboard. See id. at col. 3, ll. 22–25.
`When a chip is attached to another electronic compo-
`nent, forces are exerted on the chip’s bond pad. Id. at Ab-
`stract & col. 5, ll. 53–57. Those forces can result in damage
`to the interconnect layers and to the dielectric material
`that surrounds those layers. See id. at Abstract & col. 1, ll.
`39–42. As such, dedicated support structures made of
`metal layers and vias are connected to and provide support
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`for the bond pad. See id. at col. 1, ll. 53–61. In the prior
`art, these metal support layers were linked to the bond pad,
`and thus were not “functionally independent,” i.e., they
`could not be “used for wiring or interconnects unrelated to
`the pad.” Id. at col. 1, ll. 58–64.
`The ’552 patent discloses improvements to the struc-
`tures of an integrated circuit that reduce the potential for
`damage to the interconnect layers and dielectric material
`when the chip is attached to another electronic component
`while also “permit[ing] each of the interconnect layers un-
`derlying [the pad] to be functionally independent in the cir-
`cuit if desired.” See id. at col. 3, line 64 through col. 4, line
`7. Specifically, the ’552 patent discloses that only “a pre-
`determined minimum amount of metal or a minimum den-
`sity” is needed to “adequately support” the bond pad. See
`id. at col. 3, line 64 through col. 4, line 4. If the function-
`ally independent interconnect layers underneath the pad
`are insufficient to reach a predetermined minimum den-
`sity, “dummy metal lines”—i.e., metal lines that do not
`serve any electrical purpose—may be added to increase the
`metal density of the interconnect layers. See id. at col. 4,
`ll. 13–56; see also id. at Fig. 3.
`Claim 1 is the only independent apparatus claim of the
`’552 patent and is representative of the claimed invention.
`It recites as follows:
`1. An integrated circuit, comprising:
`a substrate having active circuitry;
`a bond pad over the substrate;
`a force region at least under the bond pad char-
`acterized by being susceptible to defects due to
`stress applied to the bond pad;
`a stack of interconnect layers, wherein each in-
`terconnect layer has a portion in the force region;
`and
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`a plurality of interlayer dielectrics separating
`the interconnect layers of the stack of interconnect
`layers and having at least one via for interconnect-
`ing two of the interconnect layers of the stack of in-
`terconnect layers;
`wherein at least one interconnect layer of the
`stack of interconnect layers comprises a functional
`metal line underlying the bond pad that is not elec-
`trically connected to the bond pad and is used for
`wiring or interconnect to the active circuitry, the at
`least one interconnect layer of the stack of inter-
`connect layers further comprising dummy metal
`lines in the portion that is in the force region to ob-
`tain a predetermined metal density in the portion
`that is in the force region.
`’552 patent, claim 1. Claim 2 depends from claim 1, and
`claim 11 is a method claim generally similar to claim 1.
`Claim 20 also plays a role in this appeal. It recites as
`follows:
`20. A method of making an integrated circuit hav-
`ing a plurality of bond pads, comprising:
`
`developing a circuit design of the integrated
`circuit;
`developing a layout of the integrated circuit ac-
`cording to the circuit design, wherein the layout
`comprises a plurality of metal-containing intercon-
`nect layers that extend under a first bond pad of
`the plurality of bond pads, at least a portion of the
`plurality of metal-containing interconnect layers
`underlying the first bond pad and not electrically
`connected to the bond pad as a result of being used
`for electrical interconnection not directly connected
`to the bond pad;
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`modifying the layout by adding dummy metal
`lines to the plurality of metal-containing intercon-
`nect layers to achieve a metal density of at least
`forty percent for each of the plurality of metal-con-
`taining interconnect layers; and
`forming the integrated circuit comprising the
`dummy metal lines.
`’552 patent, claim 20.
`
`B
`In 2018, VLSI brought suit in the United States Dis-
`trict Court for the District of Delaware, charging Intel with
`infringing the ’552 patent. The district court subsequently
`conducted a claim construction hearing. In the course of
`the hearing, the court construed the term “force region,”
`which appears in independent claims 1 and 11 of the ’552
`patent. Citing a passage from the ’552 patent, the district
`court construed “force region” to mean a “region within the
`integrated circuit in which forces are exerted on the inter-
`connect structure when a die attach is performed.” J.A.
`6017, 6356; see also ’552 patent, col. 3, ll. 49–52.
`In June 2019, after the district court action was filed
`but before the claim construction proceedings in that ac-
`tion, Intel filed its petitions for IPR, challenging the valid-
`ity of claims 1, 2, 11, and 20 of the ’552 patent. In the
`petition directed to claims 1 and 2, Intel proposed a con-
`struction of “force region” that was consistent with the
`claim construction that Intel subsequently offered to the
`district court and that the district court adopted, i.e., a “re-
`gion within the integrated circuit in which forces are ex-
`erted on the interconnect structure when a die attach is
`performed.” J.A. 6588–89.
`VLSI did not oppose Intel’s proposed construction be-
`fore the Board. It soon became evident, however, that al-
`though the parties purported to agree on the construction
`to be given to the term “force region,” their agreement was
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`merely apparent, because they disagreed as to the meaning
`of the term “die attach.”
`Intel argued that the term “die attach” refers to any
`method of attaching the chip to another electronic compo-
`nent, and that the term “die attach” therefore includes at-
`tachment by a method known as wire bonding. J.A. 6594
`(Petition in IPR2019-1198); J.A. 6789–93 (Petitioner’s Re-
`ply to Patent Owner’s Preliminary Response); J.A. 7063–
`70 (Petitioner’s Reply); J.A. 7286–87 (Oral Hearing before
`the Board). VLSI, on the other hand, argued that the term
`“die attach” refers to a method of attachment known as “flip
`chip” bonding, and does not include wire bonding. See J.A.
`6720–29 (Patent Owner’s Preliminary Response); J.A.
`7005–14 (Patent Owner’s Response); J.A. 7100–05 (Patent
`Owner’s Sur-Reply to Petitioner’s Reply to the Patent
`Owner’s Response); see also J.A. 7299–7300 (Oral Hearing
`before the Board in which counsel for Intel noted that alt-
`hough the parties agreed on the construction of “force re-
`gion,” they disagreed on the meaning of the term “die
`attach”).
`Applying its proposed restrictive definition of “die at-
`tach,” VLSI distinguished Intel’s principal prior art refer-
`ence for the “force region” limitation, U.S. Patent
`Publication No. 2004/0150112 (“Oda”). That reference dis-
`closes attaching a chip to another component using wire
`bonding. Based on its contention that the term “die attach”
`does not encompass attachment by wire bonding, VLSI ar-
`gued that Oda does not disclose a “force region” within the
`meaning of the claims of the ’552 patent as construed by
`the district court.
`In its Institution Decisions, the Board stated that
`“based on the current record,” it disagreed with VLSI that
`the method of performing a “die attach” cannot include the
`method of wire bonding. J.A. 6846, 20006. The Board
`pointed out that Intel had provided argument and evidence
`that wire bonding is a type of die attach, and that Oda
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`therefore disclosed a “force region” under Intel’s claim con-
`struction, i.e., a region within the integrated circuit in
`which forces are exerted on the interconnect structure
`when a die attach is performed. J.A. 6846–47, 20006–07.
`In addition, the Board noted that Intel asserted that the
`“force region” includes regions directly under the bond pad,
`and that VLSI’s proposed construction during the district
`court proceeding also included regions directly under the
`bond pad. J.A. 6845, 20005–06. The Board then stated
`that a construction of “force region” that includes regions
`at least under the bond pad “is consistent with the plain
`language of claim[s] 1” and 11. See J.A. 6845, 20005.
`In its Final Written Decision, unlike in the Institution
`Decisions, the Board did not resolve the parties’ dispute re-
`garding the meaning of the term “die attach.” Instead, the
`Board construed the term “force region” as “including at
`least the area directly under the bond pad.” Intel Corp. v.
`VLSI Tech. LLC, Nos. IPR2019-01198, IPR2019-01199,
`IPR2019-01200, 2021 WL 388740, at *6 (P.T.A.B. Feb. 3,
`2021). The Board also found that the ’552 patent specifica-
`tion made clear in several places that the term “force re-
`gion” was not limited to flip chip bonding, but could include
`wire bonding as well. Id. at *7. Based on that finding, the
`Board concluded that Oda disclosed the “force region” ele-
`ment of claims 1, 2, and 11, and that those claims were un-
`patentable for obviousness. Id. at *12–13.
`With respect to claim 20 of the ’552 patent, the parties
`disagreed over the construction of the limitation providing
`that the “metal-containing interconnect layers” are “used
`for electrical interconnection not directly connected to the
`bond pad.” VLSI argued that the phrase requires a connec-
`tion to active circuitry or the capability to carry electricity.
`Id. at *8. Intel argued that the claim does not require that
`the interconnection actually carry electricity. See id. The
`Board sided with Intel; it found that “[c]laim 20 does not
`recite ‘active circuitry’” and declined “to import [that] limi-
`tation into claim 20.” Id. at *9. The Board therefore
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`construed the phrase to encompass interconnect layers
`that are “electrically connected to each other but not elec-
`trically connected to the bond pad.” Id. at *10.
`Intel relied principally upon U.S. Patent No. 7,102,223
`(“Kanaoka”) as teaching the “used for electrical intercon-
`nection” limitation in claim 20 as construed by the Board.
`Figure 45 of Kanaoka discloses a die that has a series of
`interconnect layers, some of which are connected to each
`other by vertical metal structures called “vias.” J.A. 7655;
`see also Appellee’s Br. 6–7. Because the interconnect layers
`disclosed in Kanaoka were electrically connected to one an-
`other but not to the bond pad, the Board found that Ka-
`naoka disclosed the “used for electrical interconnection”
`limitation of claim 20. Intel, 2021 WL 388740, at *28.
`Based on its analysis, the Board concluded that all the
`challenged claims (claims 1, 2, 11, and 20) of the ’552 pa-
`tent were unpatentable. Id. at *29. VLSI appealed.
`II
`VLSI raises two principal issues on appeal. First, VLSI
`argues that the Board erred in its treatment of the “force
`region” limitation of claims 1, 2, and 11. Second, VLSI ar-
`gues that the Board erred in construing the phrase “used
`for electrical interconnection” in claim 20 to encompass a
`metallic structure that is not connected to active circuitry.
`We affirm with respect to the first issue, and we reverse
`and remand with respect to the second.
`A
`1
`With regard to the “force region” limitation, VLSI ar-
`gues that the Board erred in declining to adopt the con-
`struction of “force region” that was proposed by Intel and
`adopted by the district court. Specifically, VLSI argues
`that the Board failed to acknowledge and give appropriate
`weight to the district court’s claim construction. VLSI
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`bases its argument principally on the Patent and Trade-
`mark Office procedures that require the Board to “con-
`sider” prior claim construction determinations by a district
`court and give such prior constructions appropriate weight.
`See 37 C.F.R. § 42.100(b); see also Power Integrations, Inc.
`v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir. 2015); Patent
`Trial and Appeal Board, Consolidated Trial Practice Guide
`46–47 (Nov. 2019); Changes to the Claim Construction
`Standard for Interpreting Claims in Trial Proceedings Be-
`fore the Patent Trial and Appeal Board, 83 Fed. Reg.
`51,340, 51,354 (Oct. 11, 2018).
`We reject VLSI’s argument regarding the asserted reg-
`ulatory violation for several reasons. First, while it is true
`that the Board did not specifically mention the district
`court’s claim construction in its Final Written Decision, the
`Board was clearly well aware of that construction, as the
`district court’s construction was the subject of repeated and
`extensive discussion in the briefing and in the oral hearing
`before the Board. See J.A. 6720 (Patent Owner’s Prelimi-
`nary Response); J.A. 6954, 7001 (Patent Owner’s Re-
`sponse); J.A. 7099–7100 (Patent Owner’s Sur-reply); J.A.
`7328, 7333–35 (Oral Hearing).
`Second, the Board did not reject the district court’s con-
`struction. Instead, in light of the arguments made by the
`parties before the Board, it was clear that the apparent
`agreement as to the district court’s construction concealed
`a fundamental disagreement between the parties as to the
`proper construction of “force region.” The Board recognized
`that simply adopting Intel’s proposed construction would
`not resolve the true dispute between the parties, which
`turned on whether the term “force region,” as used in the
`’552 patent, was limited to flip chip bonding or covered wire
`bonding as well. See J.A. 6838, 6846–47. Although the dis-
`trict court defined the term “force region” with reference to
`“die attach” processes, the district court did not decide—
`and was not asked to decide—whether the term “die at-
`tach,” as used in the patent, included wire bonding or was
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`limited to flip chip bonding. See generally VLSI Tech. LLC
`v. Intel Corp., No. 18-cv-966, Dkt. No. 228 (D. Del. Aug. 19,
`2019) (Joint Claim Construction Brief). Thus, the Board
`addressed an argument not made to the district court, and
`it reached a conclusion not at odds with the conclusion
`reached by the district court. See Consolidated Trial Prac-
`tice Guide 47 (noting that the “facts and circumstances of
`each case will be analyzed as appropriate”).
`Finally, we conclude that the Board’s treatment of the
`term “force region” was not erroneous, for the reasons we
`address below. Because the parties’ positions before the
`Board made it clear that the Board needed to go beyond the
`district court’s claim construction in order to resolve the
`parties’ dispute, it was unnecessary for the Board to advert
`to the district court’s claim construction. Therefore, even
`if it might have been useful for the Board to begin by ex-
`pressly acknowledging the district court’s claim construc-
`tion, the Board was not required to do so, and any failure
`to do so was at most harmless error.
`2
`As to the merits of the Board’s claim construction, we
`conclude that the Board’s claim construction of “force re-
`gion” and its application of that construction to the Oda
`reference were not inconsistent with the proper construc-
`tion of “force region.”
`Both Intel and the district court relied on a passage
`from column 3 of the ’552 patent as providing support for
`Intel’s proposed construction of the term “force region.”
`That passage explains that “[t]he force region 64 is a region
`within the integrated circuit 10 in which forces are exerted
`on the interconnect structure when a die attach is per-
`formed.” ’552 patent, col. 3, ll. 49–52. Like the Board, we
`conclude that the passage in column 3 is directed to the
`embodiment disclosed in Figures 1 and 2 of the ’552 patent.
`See Intel, 2021 WL 388740, at *7. Thus, even if the term
`“die attach,” as used in the ’552 patent, were construed to
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`include only flip chip bonding, that would not affect the
`construction of the term “force region.” As we have repeat-
`edly cautioned, claims should not be limited “to preferred
`embodiments or specific examples in the specification.” Te-
`leflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313, 1328
`(Fed. Cir. 2002) (quoting Comark Commc’ns, Inc. v. Harris
`Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998)). It was there-
`fore unnecessary for the Board to determine whether the
`term “die attach,” as used in column 3 of the ’552 patent,
`excludes wire bonding.
`Even if the term “die attach,” as used in column 3 of the
`’552 patent, is understood to refer to flip chip bonding in
`particular and not to other forms of attachment such as
`wire bonding, other portions of the specification make clear
`that the invention is not limited to flip chip bonding. The
`specification specifically calls out wire bonding mecha-
`nisms, stating that examples of an interconnect pad within
`the scope of the invention “include, but are not limited to,
`a wire bond pad, a probe pad, a flip-chip bump pad, a test
`point or other packaging or test pad structures that may
`require underlying structural support.” ’552 patent, col. 2,
`ll. 42–45.
`In addition, as the Board noted, other language in the
`specification indicates that the claimed “force region” is not
`limited to attachment processes that use flip chip bonding.
`See Intel, 2021 WL 388740, at *7. For example, with re-
`spect to another embodiment of the invention, the specifi-
`cation states that “[i]n another form the force region is a
`region in which the interconnect layers . . . are susceptible
`to stress from the bond pad due to assembly or other pro-
`cesses.” ’552 patent, col. 6, ll. 25–29 (emphasis added).
`Likewise, the specification elsewhere states that a force re-
`gion “is identified around and under the bond pad charac-
`terized by being susceptible to defects due to contacts to the
`bond pad.” Id. at col 5, ll. 55–57. Based on those portions
`of the specification, the Board found that the Oda reference
`reads on the “force region” limitation.
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`We conclude that the correct construction of the term
`“force region” is the definition provided in column 6 of the
`’552 patent. That is, “force region” is construed to mean “a
`region in which the interconnect layers are susceptible to
`stress from the bond pad due to assembly or other pro-
`cesses.” See ’552 patent, col. 6, ll. 25–29. Under that con-
`struction, stresses on the interconnect layers resulting
`from any assembly process, including wire bonding, would
`fall within the scope of the term “force region.” The Board’s
`treatment of that limitation is not inconsistent with our
`construction. In fact, the Board relied on the same lan-
`guage from column 6 of the ’552 patent in concluding that
`the Oda reference discloses the “force region” of claim 1.
`Intel, 2021 WL 388740, at *13.
`The Board was able to resolve the case by construing
`the term “force region” to include at least the area directly
`under the bond pad and by not limiting the term to situa-
`tions in which the flip chip bonding method is used. That
`construction is not inconsistent with our construction. The
`Board therefore properly found that the Oda reference, in
`combination with other references cited to the Board, made
`claims 1, 2, and 11 unpatentable.
`3
`VLSI raises two other challenges to the Board’s con-
`struction of the term “force region.” First, it contends that
`defining “force region” to mean a region at least directly
`under the bond pad is legally flawed because the definition
`restates a requirement that is already in the claims, which
`refer in the case of claim 1 to a “force region at least under
`the bond pad” and in the case of claim 11 to “a force region
`at least under the first bond pad of the plurality of bond
`pads.” That construction, according to VLSI, would violate
`the principle that construing claims to include features of
`the term that are already recited in the claims “would
`make those expressly recited features redundant,” and that
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`“[i]deally” such constructions should be avoided. Apple,
`Inc. v. Ameranth, 842 F.3d 1229, 1237 (Fed. Cir. 2016).
`While a construction that introduces redundancy into
`a claim is disfavored, it is not foreclosed. See SimpleAir,
`Inc. v. Sony Ericsson Mobile Commc’ns AB, 820 F.3d 419,
`429 (Fed. Cir. 2016). That is particularly true where, as in
`this case, intrinsic evidence makes it clear that the “redun-
`dant” construction is correct. To be sure, the claim lan-
`guage in question could have been drafted more precisely.
`But the meaning of the claim limitation referring to the
`force region is clear: The claim identifies a region that is
`“at least under the bond pad” and is “characterized by be-
`ing susceptible to defects due [to] stress applied to the bond
`pad,” and it refers to that region as the “force region.”
`Thus, the “force region” limitation is best understood as
`containing a definition of the force region, just as would be
`the case if the language of the limitation had read “a region,
`referred to as a force region, at least under the bond
`pad . . .” or “a force region, i.e., a region at least under the
`bond pad . . . .” As such, that language from the claims is
`best viewed not as redundant, but merely as clumsily
`drafted.
`VLSI’s second argument is that when the parties to an
`IPR proceeding agree to a particular construction of a claim
`term, the Board is bound by that construction, regardless
`of whether the construction to which the parties agree is
`actually the proper construction of that term. See Oral Ar-
`gument at 14:22–22:04; see also Appellant’s Reply Br. 12–
`14. In support of its argument regarding that prohibition,
`VLSI cites the Supreme Court’s decision in SAS Institute
`v. Iancu, 138 S. Ct. 1348 (2018), and our decisions in Kon-
`inklijke Philips N.V. v. Google LLC, 948 F.3d 1330 (Fed.
`Cir. 2020), and In re Magnum Oil Tools International, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016).
`We disagree with VLSI’s reading of those cases. In
`SAS, the Court held that the petition “guide[s] the life of
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`the litigation” in an IPR proceeding. SAS, 138 S. Ct. at
`1356. In Koninklijke, we reaffirmed the principle that “it
`is the petition, not the Board’s discretion, that defines the
`metes and bounds of an [IPR].” Koninklijke, 948 F.3d at
`1336. And in Magnum Oil, we held that “the Board must
`base its decision on arguments that were advanced by a
`party, and to which the opposing party was given a chance
`to respond.” Magnum Oil, 829 F.3d at 1381. Each of those
`cases stands for the proposition that the petition defines
`the scope of the IPR proceeding and that the Board must
`base its decision on arguments that were advanced by a
`party and to which the opposing party was given a chance
`to respond. None of those cases prohibits the Board from
`construing claims in accordance with its own analysis. To
`the contrary, we have held that the Board is not limited to
`the claim constructions proffered by the parties, but may
`adopt its own claim construction of a disputed claim term.
`See, e.g., WesternGeco LLC v. ION Geophysical Corp., 889
`F.3d 1308, 1328–29 (Fed. Cir. 2018); Uniloc 2017 LLC v.
`Facebook Inc., 989 F.3d 1018, 1032–33 (Fed. Cir. 2021).
`Although the parties may have agreed to apply the lan-
`guage of the district court’s construction of “force region,”
`this was not a case in which the parties actually agreed on
`the proper claim construction. As we explained above, it is
`true that Intel proposed to construe “force region” as “a re-
`gion within the integrated circuit in which forces are ex-
`erted on the interconnect structure when a die attach is
`performed,” and that VLSI did not oppose that construc-
`tion. But the parties’ purported agreement concealed a
`fundamental disagreement about the meaning of that con-
`struction. Because of the parties’ very different under-
`standings of the meaning of the term “die attach,” it was
`clear in the Board proceedings that there was no real
`agreement on the proper claim construction. In that
`
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`15
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`situation, it was proper for the Board to adopt its own con-
`struction of a disputed claim term.1
`For the foregoing reasons, we conclude that the Board’s
`analysis of the “force region” limitation was not erroneous.
`Because VLSI raises no other challenges to the Board’s de-
`cision that claims 1, 2, and 11 are unpatentable,2 we affirm
`the Board’s decision with respect to those claims.
`B
`VLSI next argues that the Board erred in construing
`the phrase “used for electrical interconnection not directly
`connected to the bond pad,” which appears in claim 20 of
`the ’552 patent. The Board held that this phrase encom-
`passes interconnect layers that are “electrically connected
`to each other but not electrically connected to the bond pad”
`or to any other active circuitry. Id. at *10. VLSI argues
`that the Board should have construed the phrase to require
`
`
`In its reply brief, VLSI argues that judicial estoppel
`1
`and waiver preclude Intel from advocating for the Board’s
`claim construction. Given that the proceedings before the
`Board revealed that the parties disagreed as to the mean-
`ing of the term “die attach,” it was appropriate for the
`Board to adopt, and Intel to advocate for, a construction
`that captured the essence of Intel’s position, i.e., that the
`term “force region” referred to a region at least under the
`bond pad that was susceptible to defects due to stress ap-
`plied to the bond pad, regardless of the type of bonding that
`was responsible for causing that stress.
`2 We note that VLSI has expressly waived any due
`process challenge to the Board’s construction of “force re-
`gion.” See Oral Argument at 18:47–18:53. In particular,
`VLSI has not suggested that it lacked notice of the Board’s
`construction of that term or an opportunity to contest that
`construction.
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`16
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
`
`that the interconnect layers be connected to active circuitry
`or have the capability to carry electricity.
`VLSI argues that under its proposed construction, the
`Kanaoka reference does not disclose the “used for electrical
`interconnection” limitation of claim 20, because the metal-
`lic layers are connected by the vias only to one another;
`they do not carry electricity and are not electrically con-
`nected to any other components.
`We agree with VLSI that the Board’s construction of
`the phrase “used for electrical interconnection not directly
`connected to the bond pad” was too broad. Two aspects of
`the claims make this point clear. First, the use of the words
`“being used for” in the claim imply that some sort of actual
`use of the metal interconnect layers to carry electricity is
`required. Second, the recitation of “dummy metal lines”
`elsewhere in claim 20 implies that the claimed “metal-con-
`taining interconnect layers” are capable of carrying elec-
`tricity; otherwise, there would be no distinction between
`the dummy metal lines and the rest of the interconnect
`layer.
`The file history of the ’552 patent provides further sup-
`port for that conclusion. The phrase “used for electrical in-
`terconnection not directly connected to the bond pad” was
`added to claim 20 during prosecution of the ’552 patent.
`The underlined language below was added to claim 20 at
`that time:
`20. A method of making an integrated circuit hav-
`ing a plurality of bond pads, comprising:
`
`developing a circuit design of the integrated
`circuit;
`developing a layout of the integrated circuit ac-
`cording to the circuit design, wherein the layout
`comprises a plurality of metal-containing intercon-
`nect layers that extend under a first bond pad of
`the plurality of bond pads, at least a portion of the
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`Case: 21-1826 Document: 54 Page: 17 Filed: 11/15/2022
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`VLSI TECHNOLOGY LLC v. INTEL CORPORATION
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`17
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`plurality of metal-containing interconnect layers
`underlying the first bond pad and not electrically
`connected to the first bond pad as a result of being
`used for electrical interconnection not directly con-
`nected to the bond pad;
`modifying the layout by adding dummy metal
`lines to the plurality of metal-containing intercon-
`nect layers to achieve a metal density of at least
`forty percent for each of the plurality of metal-con-
`taining interconnect layers; and
`forming the integrated circuit comprising the
`dummy metal lines.
`J.A. 272–73 (emphasis added). The Board observed that
`the amendment to claim 20 appeared to address what “the
`metal interconnect layers could not be attached to (i.e., the
`bond pad), rather than limiting what [they] must be con-
`nected to.” Intel, 2021 WL 388740, at *9.
`The problem with that observation is that it does not
`explain the addition o