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`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 1 of 47
`
`G. Hopkins Guy III (CA Bar No. 124811)
`Email: hop.guy@bakerbotts.com
`Jon V. Swenson (CA Bar No. 233054)
`Email: jon.swenson@bakerbotts.com
`BAKER BOTTS L.L.P.
`1001 Page Mill Road, Bldg One, Suite 200
`Palo Alto, CA 94304
`Telephone: (650) 739-7500
`Fax: (650) 739-7699
`
`
`Attorneys for Plaintiff QuickLogic Corporation.
`
`UNITED STATES DISTRICT COURT
`
`NORTHERN DISTRICT OF CALIFORNIA
`Case No. 5:21-cv-4657
`QUICKLOGIC CORPORATION,
`
`
`COMPLAINT FOR DECLARATORY
`Plaintiff,
`JUDGMENT OF NONINFRINGEMENT
`
`AND NON-BREACH OF CONTRACT
`v.
`
`
`DEMAND FOR JURY TRIAL
`KONDA TECHNOLOGIES, INC., AND
`VENKAT KONDA,
`
`
`
`Defendants.
`
`
`
`
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`
`
`Case No. 5:21-cv-4657
`
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 2 of 47
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`Plaintiff QuickLogic Corporation (“QuickLogic”) seeks a declaratory judgment that it has
`not breached any contractual commitment or infringed on any claim of patents as asserted by Konda
`Technologies, Inc. through the actions of its CEO, Venkat Konda (collectively, “Defendants”).
`There is a live and existing controversy between the parties to this lawsuit. Between April
`and May, 2021, Defendants sent a series of communications to QuickLogic alleging that QuickLogic
`infringed patents identified in the Konda Technologies FPGA Interconnect Patent Portfolio (“Patent
`Portfolio”, Exhibit 2)1 and breached a 2010 Consulting and License Agreement between the parties
`(“the 2010 Agreement”, Exhibit 3).
`After several communications, Defendants sent a cease and desist letter alleging
`unauthorized use of the Patent Portfolio and violation of the 2010 Agreement. (Exhibit 5.) For its
`part, QuickLogic repeatedly offered to discuss Defendants’ allegations to seek informal resolution.
`(Exhibit 6.) Defendants did not engage with QuickLogic to resolve the matter and continued to
`assert, without explanation, particularity or specificity, that QuickLogic was improperly using
`Defendants’ patents and violating the 2010 Agreement. Thus, QuickLogic seeks a declaration from
`this Court that its activities are not infringing the Asserted Patents or violating the 2010 Agreement.
`INTRODUCTION
`1.
`This is an action for a declaratory judgment arising under the patent laws of the
`United States, Title 35 of the United States Code. QuickLogic seeks a declaratory judgment that it
`does not infringe any claim of the Asserted Patents. The action arises from a real and immediate
`controversy between the QuickLogic and the Defendants as to whether QuickLogic infringes any
`claims of the Asserted Patents.
`2.
`On April 30, 2021 the Defendants emailed the CEO of QuickLogic inquiring
`whether QuickLogic was violating the 2010 Agreement through its involvement with an open
`source initiative. (Exhibit 1.) The CEO of QuickLogic replied that because QuickLogic “did not
`commercialize” the Defendants’ “architecture,” QuickLogic did not violate the 2010 Agreement
`
`
`1 The 2010 Agreement licensed to QuickLogic certain patent rights and Defendants’ recent
`assertions do not challenge that QuickLogic is licensed to use those rights. As described later in
`this Complaint, the patents at issue in this case are the “Asserted Patents.”
`1
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`Case No. 5:21-cv-4657
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 3 of 47
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`and thus did not infringe the Patent Portfolio. (Exhibit 1.) Defendants proceeded to send additional
`emails asking for response to their assertion that QuickLogic did use the Patent Portfolio. (Exhibit
`1.) After back and forth communication, Defendants sent a cease and desist letter alleging (1)
`unauthorized use of the Patent Portfolio and (2) violation of the 2010 Agreement. (Exhibit 5.) The
`letter concludes with an explicit statement that “this letter serves as a pre-suit notice for a lawsuit
`against you.” (Exhibit 5.) Therefore, because of the Defendants’ threat of suit, QuickLogic
`believes there is an immediate, substantial, and judiciable controversy whether its programmable
`logic products infringe the Asserted Patents and whether it has breached the 2010 Agreement.
`3.
`The threat of an imminent lawsuit is bolstered by Defendants’ history of bringing
`suits on similar grounds. Defendants’ website demonstrates their strong emphasis and focus on its
`multiple past and present suits against alleged patent infringers. (Exhibit 7.) Eight out of fifteen
`substantive pages of the website are devoted to narrative updates of the suits brought against
`alleged “fraudsters.” (Exhibit 7.) Because of the Defendants’ track record, it is very likely the
`threat of suit in the cease and desist letter is very real. Therefore, a declaratory judgment of patent
`noninfringement would resolve a real and very immediate controversy.
`4.
`The Defendants’ actions have created a real and immediate controversy between
`the Defendants and QuickLogic as to whether their products and/or services infringe any claims of
`the Asserted Patents and as to whether QuickLogic has breached the 2010 Agreement. The facts
`and allegations recited herein show that there is a real, immediate, and justiciable controversy
`concerning these issues.
`
`THE PARTIES
`5.
`QuickLogic Corporation is a Delaware corporation with a place of business at 2220
`Lundy Ave., San Jose, California 95131.
`6.
`On information and belief, Konda Technologies, Inc. is a company incorporated
`and registered under the laws of California with a principal place of business in San Jose,
`California. Konda Technologies holds itself out as an intellectual property licensing company, a
`non-practicing entity.
`7.
`On information and belief, Venkat Konda is an individual who resides in Santa
`Case No. 5:21-cv-4657
`2
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 4 of 47
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`Clara County, California. On information and belief, Venkat Konda is the CEO of Konda
`Technologies, Inc.
`
`JURISDICTIONAL STATEMENT
`8.
`This action arises under the Declaratory Judgment Act, 28 U.S.C. § 2201 et seq.,
`and under the patent laws of the United States, Title 35 of the United States Code.
`9.
`This Court has subject matter jurisdiction over the claims alleged in this action
`under 28 U.S.C. §§ 1331, 1338, 1367, 2201, and 2202 because this Court has exclusive
`jurisdiction over declaratory judgment claims arising under the patent laws of the United States
`pursuant to 28 U.S.C. §§ 1331, 1338, 2201, and 2202. This Court also has supplemental
`jurisdiction over the declaratory judgment claim of non-breach of the 2010 Agreement under 28
`U.S.C. § 1367 because it is related to the patent noninfringement claims such that they form part
`of the same case or controversy to which this court has exclusive jurisdiction over pursuant to 28
`U.S.C. §§ 1331, 1338, 1367, 2201, and 2202.
`10.
`This Court can provide the declaratory relief sought in this Complaint because an
`actual case and controversy exists between the parties within the scope of this Court’s jurisdiction
`pursuant to 28 U.S.C. § 2201. As described in this Complaint, an actual case and controversy
`exists at least because Defendants’ have asserted that QuickLogic infringes the Patent Portfolio
`and has breached the 2010 Agreement. Further, Defendants specified in a cease and desist letter
`that the letter served “as a pre-suit notice for a lawsuit” and that the Defendants “will have no
`choice but to pursue all legal causes of action” if the Plaintiffs did not comply with the letter’s
`demands. (Exhibit 5.)
`11.
`This Court has personal jurisdiction over the Defendants because the Defendants
`have engaged in actions in this District that form the basis of the Plaintiff’s claims against the
`Defendants. First, Konda Technologies, Inc. is incorporated in the state and has its primary place
`of business in the District. Therefore, Konda Technologies, Inc. is subject to general personal
`jurisdiction. Second, the Defendants have entered into several contracts with QuickLogic in the
`District. Third, the Defendants have availed themselves of the District by bringing suit against
`another company, alleging infringement of the U.S. Patent No. 10,003,553. (See, e.g., Case No.
`Case No. 5:21-cv-4657
`3
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 5 of 47
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`5:18-cv-07581-LHK.) Fourth, alleging unauthorized use of the Patent Portfolio and violation of
`the 2010 Agreement entered into within the District, the Defendants have sent an email cease and
`desist letter, which the Defendants characterized as pre-suit notice for a lawsuit.
`12.
`Therefore, the Defendants have availed themselves of the District and have created
`a real, live, immediate, and justiciable case or controversy between the Defendants and the
`Plaintiff.
`13.
`In doing so, the Defendants have established sufficient minimum contacts with the
`Northern District of California such that the Defendants are subject to specific personal
`jurisdiction in this action. Further, the exercise of personal jurisdiction based on these repeated and
`pertinent contacts does not offend traditional notions of fairness and substantial justice.
`14.
`Venue is proper in this District under 28 U.S.C. §§ 1391 and 1400, including
`because, under Ninth and Federal Circuit law, venue in declaratory judgment actions for
`noninfringement of patents is determined under the general venue statute, 28 U.S.C. § 1391.
`15.
`Under 28 U.S.C. § 1391(b)(1), venue is proper in any judicial district where a
`defendant resides, if all defendants are residents of the State in which the district is located.
`Entities with the capacity to sue and be sued, such as the Defendants, are deemed to reside, if
`defendants, in any judicial district in which such defendants are subject to the court’s personal
`jurisdiction with respect to the civil action in question under 28 U.S.C. § 1391(c).
`16.
`As discussed above, on information and belief Defendant Konda is domiciled
`within the Northern District of California and is therefore deemed to reside within this District
`under 28 U.S.C. § 1391. Moreover, the Defendants are subject to personal jurisdiction with respect
`to this action in the Northern District of California, and thus, at least for the purposes of this
`action, the Defendants reside in the Northern District of California and venue is proper under 28
`U.S.C. § 1391.
`17.
`Venue is also proper in this judicial district under 28 U.S.C. § 1400(b) because
`Defendants are located in this judicial district and Konda Technologies, Inc. is incorporated in
`California. Venue is also proper because the alleged acts giving rise to the infringement
`allegations all took place in this District.
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`Case No. 5:21-cv-4657
`
`4
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 6 of 47
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`FACTUAL BACKGROUND
`18.
`Between April and May, 2021, Defendants sent a series of communications to
`QuickLogic ultimately culminating in a cease and desist letter from Defendants alleging
`unauthorized use of the Patent Portfolio and violation of the 2010 Agreement. On April 30, 2021,
`Defendants emailed Brian Faith, CEO of QuickLogic, concerning QuickLogic’s involvement with
`open source initiatives and its compliance with the 2010 Agreement. (Exhibit 1.) The open
`source initiatives are limited to joining the Open Source FPGA Foundation as a founding and
`Premier Member, and the QuickLogic Open Reconfigurable Computing Initiative. (Exhibit 1.)
`Faith confirmed the pursuit of the open source initiatives were in compliance with the 2010
`Agreement. (Exhibit 1.) Despite the confirmation, Defendants sent a cease and desist alleging (1)
`unauthorized use of the Patent Portfolio and (2) violation of the 2010 Agreement. (Exhibit 5.)
`Notably, the letter did not provide explanation to support the conclusory statements. (Exhibit 5.)
`The letter concludes with an explicit statement that “this letter serves as a pre-suit notice for a
`lawsuit against you.” (Exhibit 5.)
`19.
`As apparently conceded in Defendants’ demands, QuickLogic is licensed to certain
`patent rights in the Patent Portfolio pursuant to the 2010 Agreement. Therefore, only the
`unlicensed patents in the Patent Portfolio are at issue in this case. Specifically, U.S. Patent Nos.
`9,374,322 (the “’322 Patent”, Exhibit 8), 9,509,634 (the “’634 Patent”, Exhibit 9), 9,929,977 (the
`“’977 Patent”, Exhibit 10), 10,536,399 (the “’399 Patent”, Exhibit 11), 10,412,025 (the “’025
`Patent”, Exhibit 12) 10,574,594 (the “’594 Patent”, Exhibit 13), 10,992,597 (the “’597 Patent”,
`Exhibit 14), 10,965,618 (the “’618 Patent”, Exhibit 15), and 10,979,366 (the “’366 Patent”,
`Exhibit 16) (collectively, the “Asserted Patents”).2 As to the remainder of the patent rights
`contained in the Patent Portfolio, the 2010 Agreement provides a license to use them. Specifically,
`Section 1.2 of the 2010 Agreement states:
`“Konda hereby grants to QuickLogic a non-exclusive, royalty-free, irrevocable and
`world-wide right, with rights to sublicense through multiple tiers of sublicensees, to
`
`2 U.S. Patent No. 10,003,533 is also a part of the Patent Portfolio, but as described below, it was
`invalidated by the PTAB so it is not at issue in this case.
`5
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`Case No. 5:21-cv-4657
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 7 of 47
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`reproduce, make derivative works of, publicly perform, publicly display and
`distribute in any form or medium . . . and to make, have made, use, import, offer to
`sell, and sell the Konda Intellectual Property incorporated or used in the
`programmable logic of QuickLogic products or used in . . . commercializing
`QuickLogic’s technology.”
`(Exhibit 3 at 1.)
`20.
`Pursuant to Section 8.7 of the 2010 Agreement, QuickLogic attempted to engage in
`Informal Dispute Resolution between May 26, 2021 and June 16, 2021 to resolve the differences
`in opinion regarding the parties’ obligations under the 2010 Agreement. Ex. 17. Section 8.7
`affords the parties 10 business days, starting from QuickLogic’s May 26, 2021 letter, to resolve
`any disputes. Ex. 3 at 5; Ex. 6. QuickLogic unilaterally extended this period another week, to June
`16, 2021, in a good faith effort to resolve the parties’ disagreements. During this time, despite
`correspondence from Defendants on other matters, Defendants repeatedly ignored requests from
`QuickLogic to provide support for Defendants’ claims of alleged infringement and violation of the
`2010 Agreement. See Ex. 17 at 2-3 (requesting support for positions on June 15, 2021); id. at 6
`(same on June 10, 2021), id. at 9 (same on June 9, 2021) (citing Ex. 6). Without explanation,
`Defendants also refused to participate in a videoconference with officers of QuickLogic scheduled
`for June 16, 2021. Defendants’ inability or unwillingness to even provide a basis for their
`allegations doomed any meaningful, good faith Informal Dispute Resolution. Defendants’ conduct
`accordingly necessitated this action.
`21.
`One of the patents recently asserted in the Patent Portfolio is U.S. Patent No.
`10,003,553 (the “’553 Patent”). The ‘553 Patent was invalidated by the Patent Trial and Appeal
`Board (PTAB) on multiple grounds in March 2021. See Flex Logix Techologies Inc. v. Konda, No.
`PGR2019-00037 (P.T.A.B. March 16, 2021). The PTAB held all claims of the ‘553 Patent failed
`to meet the (1) definiteness requirement under 35 U.S.C. § 112(b), (2) written description
`requirement under 35 U.S.C. § 112(a), and (3) enablement requirement under 35 U.S.C. § 112(a).
`Id. at 16, 19, 21. Despite this invalidity finding, the Defendants assert that QuickLogic infringes
`the ‘553 Patent.
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`Case No. 5:21-cv-4657
`
`6
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 8 of 47
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`22.
`QuickLogic understands that Defendants are accusing the following products of
`infringing: (1) EOS S3 family of devices; (2) PolarPro 3/3E family of devices; (3) eFPGA IP cores
`based on the same FPGA architecture as in (1) and (2); and (4) the associated Open Source FPGA
`Software Tools that support them.
`INTRADISTRICT ASSIGNMENT
`23.
`For purposes of intradistrict assignment under Civil Local Rules 3-2(c) and 3-5(b),
`this Intellectual Property Action will be assigned on a district-wide basis. QuickLogic requests
`that the case be assigned to the San Jose Division because both the Plaintiff and Defendants have
`their primary places of business and residence in Santa Clara County. (Exhibits 3 and 5.) In
`particular, QuickLogic requests that the case should be assigned to the Honorable Lucy H. Koh,
`who presided over Konda Technologies, Inc.’s prior lawsuit against another company alleging
`infringement of the ’533 Patent. (See, e.g., Case No. 5:18-cv-07581-LHK.)
`FIRST CLAIM FOR RELIEF
`(Declaratory Judgment That QuickLogic Does Not Infringe The ’322 Patent)
`24.
`QuickLogic repeats and realleges each and every allegation contained in paragraphs
`1 through 23 of this Complaint as if fully set forth herein.
`25.
`In view of the facts and allegations set forth above, there is an actual, justiciable,
`substantial, and immediate controversy between QuickLogic and Defendants regarding
`infringement of the ’322 Patent.
`26.
`QuickLogic seeks a declaration that it does not infringe, and has not infringed, any
`claim of the ’322 Patent.
`27.
`The ’322 Patent is titled “Optimization of multi-stage hierarchical networks for
`practical routing applications” and purports to “significantly optimized multi-stage networks,
`useful in wide target applications, with VLSI layouts using only horizontal and vertical links to
`route large scale sub-integrated circuit blocks having inlet and outlet links, and laid out in an
`integrated circuit device in a two-dimensional grid arrangement of blocks are presented. The
`optimized multi-stage networks in each block employ several rings of stages of switches with inlet
`and outlet links of sub-integrated circuit blocks connecting to rings from either left-hand side only,
`Case No. 5:21-cv-4657
`7
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 9 of 47
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`or from right-hand side only, or from both left-hand side and right-hand side; and employ shuffle
`exchange links where outlet links of cross links from switches in a stage of a ring in one sub-
`integrated circuit block are connected to either inlet links of switches in the another stage of a ring
`in the same or another sub-integrated circuit block.” (Exhibit 8.)
`28.
`Although Defendants have not called out any particular claims as being infringed,
`Claim 1 of the ‘322 Patent is exemplary:
`1. A programmable integrated circuit comprising a plurality of programmable
`logic blocks and a network, and
`said each plurality of programmable logic blocks comprising a plurality of inlet
`links and a plurality of outlet links; and
`said network further comprising a plurality of subnetworks, with each said
`subnetwork coupled with one of said plurality of programmable logic
`blocks; and
`said plurality of subnetworks coupled with said plurality of programmable logic
`blocks arranged in a two-dimensional grid of rows and columns; and
`said each subnetwork comprising r rings, and said each ring comprising yr
`
`stages, where r≧1; yr≧1; and
`Said each stage comprising a switch of size di×do, where di≧2 and do≧2 and
`
`each said switch of size di×do having di incoming links and do outgoing
`links; and
`said each switch comprising a plurality of multiplexers, and said each
`multiplexer is of size p:1 where p>1; and
`Said outlet links are connecting to one or more of the said incoming links of any
`said switch of any stage of any ring of said coupled subnetwork, and said
`inlet links are connecting from one of said outgoing links of any said switch
`of any stage of any ring of said coupled subnetwork; and
`Said incoming links and outgoing links in each said switch in said each stage of
`said each subnetwork comprising a plurality of forward connecting links
`Case No. 5:21-cv-4657
`8
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 10 of 47
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`connecting from switches in lower stage to switches in the immediate
`succeeding higher stage in the same ring, and also comprising a plurality of
`backward connecting links connecting from switches in higher stage to
`switches in the immediate preceding lower stage in the same ring; and
`Said forward connecting links comprising a plurality of straight links connecting
`from a switch in a stage of a ring in a subnetwork to a switch in another
`stage of the same ring in the same subnetwork and also comprising a
`plurality of cross links connecting from a switch in a stage of a ring in a
`subnetwork to a switch in another stage of another ring in the same
`subnetwork or to a switch in another stage of another ring in a different
`subnetwork, and
`Said backward connecting links comprising a plurality of straight links
`connecting from a switch in a stage of a ring in a subnetwork to a switch in
`another stage of the same ring in the same subnetwork and also comprising
`a plurality of cross links connecting from a switch in a stage of a ring in a
`subnetwork to a switch in another stage of another ring the same
`subnetwork or to a switch in another stage of another ring in a different
`subnetwork, and
`Said plurality of multiplexers in one or more said stages are connected so that
`said one or more forward connecting links are fed back into said one or
`more backward connecting links through one or more said multiplexers, and
`also said plurality of multiplexers in one or more said stages are connected
`so that one or more said backward connecting links are fed back into one or
`more said forward connecting links through one or more said multiplexers;
`and
`Said cross links between switches of stages of rings between any two different
`subnetworks are connecting as either vertical links only, or horizontal links
`only, or both vertical links and horizontal links.
`9
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
`
`
`Case No. 5:21-cv-4657
`
`

`

`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 11 of 47
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`(Exhibit 8.)
`29.
`QuickLogic does not infringe Claim 1 or any other claims of the ‘322 Patent and
`seeks such a declaration to resolve the actual dispute between the parties.
`SECOND CLAIM FOR RELIEF
`(Declaratory Judgment That QuickLogic Does Not Infringe The ’634 Patent)
`30.
`QuickLogic repeats and realleges each and every allegation contained in paragraphs
`1 through 29 of this Complaint as if fully set forth herein.
`31.
`In view of the facts and allegations set forth above, there is an actual, justiciable,
`substantial, and immediate controversy between QuickLogic and Defendants regarding
`infringement of the ’634 Patent.
`32.
`QuickLogic seeks a declaration that it does not infringe, and has not infringed, any
`claim of the ’634 Patent.
`33.
`The ’634 Patent is titled “Fast scheduling and optimization of multi-stage
`hierarchical networks” and purports to “Significantly optimized multi-stage networks with
`scheduling methods for faster scheduling of connections, useful in wide target applications, with
`VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit
`blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-
`dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each
`block employ several slices of rings of stages of switches with inlet and outlet links of sub-
`integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand
`side only, or from both left-hand side and right-hand side; and employ multi-drop links where
`outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are
`connected to either inlet links of switches in the another stage of a ring in the same or another sub-
`integrated circuit block.” (Exhibit 9.)
`34.
`Although Defendants have not called out any particular claims as being infringed,
`Claim 1 of the ‘634 Patent is exemplary:
`1. A programmable integrated circuit comprising a plurality of programmable
`logic blocks and a network, and
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
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`Case No. 5:21-cv-4657
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`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 12 of 47
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`said each plurality of programmable logic blocks comprising a plurality of inlet
`links and a plurality of outlet links; and
`said network further comprising a plurality of subnetworks, with each said
`subnetwork coupled with one of said plurality of programmable logic
`blocks; and
`said plurality of subnetworks coupled with said plurality of programmable logic
`blocks arranged in a two-dimensional grid of rows and columns; and
`said each subnetwork comprising r rings, and said each ring comprising yr
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`stages, where r≧1; yr≧1; and
`Said each stage comprising a switch of size di×d0, where di≧2 and do≧2 and
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`each said switch of size di×d0 having di incoming links and d0 outgoing
`links; and
`said each switch comprising a plurality of multiplexers, and said each
`multiplexer is of size p:1 where p>1; and
`Said outlet links are connecting to one or more of the said incoming links of any
`said switch of any stage of any ring of said coupled subnetwork, and said
`inlet links are connecting from one of said outgoing links of any said switch
`of any stage of any ring of said coupled subnetwork; and
`Said incoming links and outgoing links in each said switch in said each stage of
`said each subnetwork comprising a plurality of forward connecting links
`connecting from switches in lower stage to switches in the immediate
`succeeding higher stage in the same ring, and also comprising a plurality of
`backward connecting links connecting from switches in higher stage to
`switches in the immediate preceding lower stage in the same ring; and
`Said forward connecting links comprising a plurality of straight links connecting
`from a switch in a stage of a ring in a subnetwork to a switch in another
`stage of the same ring in the same subnetwork and also comprising a
`plurality of cross links connecting from a switch in a stage of a ring in a
`Case No. 5:21-cv-4657
`11
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
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`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 13 of 47
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`subnetwork to a switch in another stage of another ring in the same
`subnetwork or to a switch in another stage of another ring in a different
`subnetwork, and
`Said backward connecting links comprising a plurality of straight links
`connecting from a switch in a stage of a ring in a subnetwork to a switch in
`another stage of the same ring in the same subnetwork and also comprising
`a plurality of cross links connecting from a switch in a stage of a ring in a
`subnetwork to a switch in another stage of another ring the same
`subnetwork or to a switch in another stage of another ring in a different
`subnetwork, and
`Said plurality of multiplexers in one or more said stages are connected so that
`said one or more forward connecting links are fed back into said one or
`more backward connecting links through one or more said multiplexers, and
`also said plurality of multiplexers in one or more said stages are connected
`so that one or more said backward connecting links are fed back into one or
`more said forward connecting links through one or more said multiplexers;
`and
`Said cross links between switches of stages of rings between any two different
`subnetworks are connecting as either vertical links only, or horizontal links
`only, or both vertical links and horizontal links;
`Said each subnetwork further partitioned into a plurality of slices so that there is
`zero or more connections from one said slice to another said slice with in
`each said subnetwork; said no two slices further having any common outlet
`links connecting from said coupled programmable logic block; said cross
`links are connecting from a said slice of any said subnetwork to a
`corresponding said slice of any other said subnetwork; said some slices of
`said each subnetwork comprising paths only to inlet links of said couple
`programmable logic block and said some other slices of said each
`Case No. 5:21-cv-4657
`12
`COMPLAINT FOR DECLARATORY JUDGMENT OF
`NONINFRINGEMENT AND NON-BREACH OF
`CONTRACT
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`
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`Case 4:21-cv-04657-JSW Document 1 Filed 06/16/21 Page 14 of 47
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`subnetwork comprising paths only to said slices of said another subnetwork.
`(Exhibit 9.)
`35.
`QuickLogic does not infringe Claim 1 or any other claims of the ‘634 Patent and
`seeks such a declaration to resolve the actual dispute between the parties.
`THIRD CLAIM FOR RELIEF
`(Declaratory Judgment That QuickLogic Does Not Infringe The ’977 Patent)
`36.
`QuickLogic repeats and realleges each and every allegation contained in paragraphs
`1 through 35 of this Complaint as if fully set forth herein.
`37.
`In view of the facts and allegations set forth above, there is an actual, justiciable,
`substantial, and immediate controversy between QuickLogic and Defendants regarding
`infringement of the ’977 Patent.
`38.
`QuickLogic seeks a declaration that it does not infringe, and has not infringed, any
`claim of the ’977 Patent.
`39.
`The ’977 Patent is titled “Fast scheduling and optimization of multi-stage
`hierarchical networks” and purports to “Significantly optimized multi-stage networks with
`scheduling methods for faster scheduling of connections, useful in wide target applications, with
`VLSI layouts using only horizontal and vertical links to route large scale sub-integrated circuit
`blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-
`dimensional grid arrangement of blocks are presented. The optimized multi-stage networks in each
`block employ several slices of rings of stages of switches with inlet and outlet links of sub-
`integrated circuit blocks connecting to rings from either left-hand side only, or from right-hand
`side only, or from both left-hand side and right-hand side; and employ multi-drop links where
`outlet links of cross links from switches in a stage of a ring in one sub-integrated circuit block are
`connected to either inlet links of switches in the another stage of a ring in the same or another sub-
`integrated cir