v.
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`
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`Defendant.
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`INTEL CORPORATION,
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`Case 1:18-cv-00966-VAC-CJB Document 1 Filed 06/28/18 Page 1 of 47 PageID #: 1
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
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`
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`VLSI TECHNOLOGY LLC,
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`
`Plaintiff,
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`C.A. No. ______________________
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`JURY TRIAL DEMANDED
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`
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`VLSI TECHNOLOGY LLC'S COMPLAINT FOR PATENT INFRINGEMENT
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`Plaintiff VLSI Technology LLC ("VLSI"), by and through its undersigned counsel,
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`pleads the following against Intel Corporation ("Intel") and alleges as follows:
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`THE PARTIES
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`1.
`
`Plaintiff VLSI is a Delaware limited liability company duly organized and
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`existing under the laws of the State of Delaware. The address of the registered office of VLSI is
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`Corporation Trust Center, 1209 Orange St., Wilmington, DE 19801. The name of VLSI's
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`registered agent at that address is The Corporation Trust Company.
`
`2.
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`VLSI is the assignee and owns all right, title, and interest to U.S. Patent Nos.
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`6,212,633 ("the '633 Patent"), 7,246,027 ("the '027 Patent"), 7,247,552 ("the '552 Patent"),
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`Case 1:18-cv-00966-VAC-CJB Document 1 Filed 06/28/18 Page 2 of 47 PageID #: 2
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`7,523,331 ("the '331 Patent"), and 8,081,026 ("the '026 Patent") (collectively, the "Asserted
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`Patents").
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`3.
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`On information and belief, Defendant Intel is a corporation duly organized and
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`existing under the laws of the State of Delaware, having its principal place of business at 2200
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`Mission College Blvd., Santa Clara, CA 95054.
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`JURISDICTION AND VENUE
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`4.
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`This is an action arising under the patent laws of the United States, 35 U.S.C. § 1
`
`et seq. Accordingly, this Court has subject matter jurisdiction pursuant to 28 U.S.C. §§ 1331 and
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`1338(a).
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`5.
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`This Court has personal jurisdiction over Intel because Intel is incorporated in
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`Delaware. Intel also manufactures products that are and have been used, offered for sale, sold,
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`and purchased in the District of Delaware.
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`6.
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`Under 28 U.S.C. §§ 1391(b)-(d) and 1400(b), venue is proper in this judicial
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`district because Intel is incorporated in this district, has committed acts of infringement within
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`this judicial district giving rise to this action, and does business in this district.
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`FIRST CLAIM
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`(Infringement of U.S. Patent No. 6,212,633)
`
`7.
`
`VLSI re-alleges and incorporates herein by reference Paragraphs 1-6 of its
`
`Complaint.
`
`8.
`
`The '633 Patent, entitled "Secure data communication over a memory-mapped
`
`serial communications interface utilizing a distributed firewall," was duly and lawfully issued
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`April 3, 2001. A true and correct copy of the '633 Patent is attached hereto as Exhibit 1.
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`9.
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`The '633 Patent names Paul S. Levy and Steve Cornelius as co-inventors.
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`10.
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`The '633 Patent has been in full force and effect since its issuance. VLSI owns by
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`assignment the entire right, title, and interest in and to the '633 Patent, including the right to seek
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`damages for past, current, and future infringement thereof.
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`11.
`
`The '633 Patent states that it relates to a "distributed firewall . . . utilized in
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`conjunction with a memory-mapped serial communications interface." Ex. 1 at Abstract.
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`12.
`
`The '633 Patent explains that "Peer-to-peer communications are particularly
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`useful in bandwidth-intensive operations such as video communications. Thus, for example, if a
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`computer CPU is coupled to a video display and a DVD drive through an IEEE 1394 interface,
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`the DVD drive could transmit video information directly to the video display over the interface,
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`thereby eliminating the need for the CPU to process and oversee the transmission." Ex. 1 at 2:51-
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`60.
`
`13.
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`The patent further explains that "one problem associated with . . . memory-
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`mapped communications interfaces, is that there is no provision for secured communications
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`between devices coupled to such interfaces. Each data transmission is broadcast to every node on
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`the interface. Only a node that is indicated as the destination for a data transmission handles the
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`transmission—all other nodes ignore the data transmission. Moreover, data is transmitted
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`without any encryption—a process often used in other environments to scramble transmitted
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`information and thereby prevent unauthorized entities from comprehending any intercepted
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`information." Ex. 1 at 2:60-67.
`
`14.
`
`The '633 Patent states that the "distributed firewall incorporates security managers
`
`in the selected nodes that are respectively configured to control access to their associated nodes,
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`thereby restricting access to such nodes to only authorized entities." Ex. 1 at 3:52-56.
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`15.
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`VLSI is informed and believes, and thereon alleges, that Intel has infringed and
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`unless enjoined will continue to infringe one or more claims of the '633 Patent, in violation of 35
`
`U.S.C. § 271, by, among other things, making, using, offering to sell, and selling within the
`
`United States, supplying or causing to be supplied in or from the United States, and importing
`
`into the United States, without authority or license, Intel products with the infringing features,
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`including Intel products containing Intel On-Chip System Fabric (commonly abbreviated
`
`"IOSF") technology.
`
`16.
`
`The '633 accused products, for example, embody every limitation of at least claim
`
`36 of the '633 Patent, literally or under the doctrine of equivalents, as set forth below. The further
`
`descriptions below, which are based on publicly available information, are preliminary examples
`
`and are non-limiting.
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`["A method of controlling access to first and second nodes from a plurality of nodes
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`coupled to one another over a memory-mapped serial communications interface of
`
`the type supporting peer-to-peer communications between the plurality of nodes,
`
`the method comprising:"]
`
`17.
`
`The '633 accused products implement a method of controlling access to multiple
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`IOSF sideband agents (such as the circuit hosting the TMCSRCCLK, TMCSRCCKL2,
`
`ENCCKRQ, and ICCSEC registers as described on page 181 of the Intel C620 Series Chipset
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`Platform Controller Hub Datasheet, as well as the "Intel ME" and "PMC" circuits).
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`18.
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`This method controls access over a memory-mapped serial communications
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`interface. For example, ICCSEC is memory-mapped at offset 0x1020.
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`
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`19.
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`Furthermore, agents on the IOSFSB, which stands for "IOSF Sideband," use serial
`
`
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`communications.
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`20.
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`For example, Intel's U.S. Patent No. 9,213,666 discussing IOSF sideband explains
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`that "[a] sideband interface . . . can be implemented as a serial message interface (instead of
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`many parallel sideband wires) to simplify structural layout requirements." 6:53-56.
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`21. Moreover, the patent further notes that "on-chip power management control" is an
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`"example[] of communication types that may be sent via a sideband message interface," 6:57-59;
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`"PMC," referenced above in the ICCSEC description, appears to be a type of Power
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`Management Control based on its use of an acronym commonly appropriated for that purpose,
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`further correlating the "IOSFB" reference with IOSF sideband as described in the '666 patent.
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`Similarly, the patent notes that "a manageability engine" (such as Intel's ME) can communicate
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`through an IOSF sideband hub, further correlating the "IOSFSB" reference with IOSF sideband
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`as described in the '666 patent. 15:19-22.
`
`22.
`
`As described in the '666 patent, IOSF sideband can provide communications
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`"between the agents" on the fabric (as stated in the Abstract), i.e., peer-to-peer communication
`
`between nodes on the fabric, such as the circuitry implementing ICCSEC, Intel ME, and PMC.
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`["a) controlling access to the first node using a first security manager disposed in
`
`the first node,"]
`
`23.
`
`The '633 accused products control access to the first node using a first security
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`manager disposed in the first node, such as the Policy Enforcer 371 in each IOSF sideband agent,
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`such as the circuit implementing the PMC, that controls access to the sideband agent, such as the
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`node implementing registers TMCSRCCLK, TMCSRCCKL2, ENCCKRQ, and ICCSEC.
`
`24.
`
`As explained in Intel's U.S. Patent No. 9,805,221 discussing SAI attributes,
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`referenced above in Intel's discussion of ICCSEC in the Intel C620 product, "incoming security
`
`information, which can include, in one embodiment, the SAI, command information and address
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`information, can be provided through input multiplexer 376 to policy enforcer 371 to determine
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`whether access is to be permitted," 7:34-39, with reference to Figure 5 reproduced here:
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`
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`25.
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`The Security Attributes Generator 365 and the Policy Enforcer 371 present in the
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`IOSF agents (such as the Intel ME, the PMC, and the circuit implementing ICCSEC), are a
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`distributed firewall as claimed.
`
`26.
`
`Furthermore, as explained in the '221 patent, functional units "may also be
`
`configured to perform sophisticated access control mechanisms such as dynamic policy
`
`configuration to enable on-the-fly revision of policy values linked to an asset," thus locally
`
`generating an authorization list of authorized nodes as claimed. 8:36-39.
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`["wherein the first node is assigned a segment of memory addresses for the
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`communications interface, the segment of memory addresses including secure and
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`unsecure portions thereof,"]
`
`27.
`
`The first node in the '633 accused products is assigned a segment of memory
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`addresses for the communications interface, the segment of memory addresses including secure
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`and unsecure portions thereof. For example, as shown in the excerpt from page 181 of the Intel
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`C620 Series Chipset Platform Controller Hub Datasheet above, the Lock_ICCG1Dyn and
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`Lock_ICCSEC bits of the ICC Security register control access to certain memory-mapped ICC
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`registers. For example, Lock_ICCG1Dyn controls access to TMCSRCCLK, TMCSRCCLK2,
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`and ENCCKRQ, and when the bit is 1, accesses are denied. In this configuration, the memory-
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`mapped addresses of these registers (at offsets 0x1000, 0x1004, and 01x1008, respectively) are a
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`secure portion of the segment of memory addresses. Analogously, Lock_ICCSEC controls
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`access to the ICC Security Register mapped at offset 0x1000. When this bit is 0, the memory-
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`mapped address of ICCSEC is an unsecure portion of the segment.
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`["and wherein the first security manager is configured to control access only to the
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`secure portion of the segment of memory addresses for the first node; and"]
`
`28.
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`The first security manager of the '633 accused products is configured to control
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`access only to the secure portion of the segment of memory addresses for the first node. For
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`example, as explained on the above-referenced page 181, setting the Lock_ICCG1Dyn and/or
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`Lock_ICCSEC bits trigger SAI-based access controls by the Policy Enforcer only in the IOSF
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`sideband agent corresponding to the circuit implementing the relevant registers.
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`["(b) controlling access to the second node using a second security manager disposed
`
`in the second node"]
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`29.
`
`Access to the second node in the '633 accused products is controlled using a
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`second security manager disposed in the second node. For example, other sideband nodes also
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`control access with their own Policy Enforcer circuits using SAIs, as discussed above, such as
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`Intel ME and PMC.
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`["wherein the first and second security managers define a distributed firewall for
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`the communications interface."]
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`30.
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`The first and second security managers define a distributed firewall for the
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`communication interface in the '633 accused products. For example, by controlling access to
`
`individual nodes as described herein, the Policy Enforcers define a distributed firewall for the
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`IOSF sideband agents.
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`31.
`
`Intel has long had knowledge of the '633 Patent. For example, the '633 Patent has
`
`been cited in multiple Intel patent prosecutions, including during the prosecution of its U.S.
`
`Patent Nos. 7,215,781; 9,507,962; 9,507,963; 9,547,779; and 9,619,672. To the extent Intel
`
`claims it did not have broader actual knowledge of the '633 Patent, Intel has been willfully blind
`
`to that patent's existence based on, for example, its publicly-known corporate policy forbidding
`
`its employees from reading patents held by outside companies or individuals.
`
`32.
`
`VLSI is informed and believes, and thereon alleges, that Intel actively,
`
`knowingly, and intentionally has induced infringement of the '633 Patent by, for example,
`
`controlling the design and manufacture of, offering for sale, selling, supplying, and otherwise
`
`providing instruction and guidance regarding the above-described products with the knowledge
`
`and specific intent to encourage and facilitate infringing uses of such products by its customers
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`both inside and outside the United States (as used in this pleading, "customers" refers to both
`
`direct and indirect customers, including entities that distribute and resell the accused products,
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`alone or as part of a system, and end users of such products and systems). For example, Intel
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`publicly provides documentation, including datasheets available through Intel's publicly
`
`accessible ARK service and software developer's manuals, instructing customers on uses of
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`Intel's products that infringe the methods of the '633 Patent. See, e.g., http://ark.intel.com. On
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`information and belief, Intel’s customers directly infringe the '633 Patent by, for example,
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`making, using, offering to sell, and selling within the United States, and importing into the
`
`United States, without authority or license, products containing the above-described Intel
`
`products.
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`33.
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`VLSI is informed and believes, and thereon alleges, that Intel has contributed to
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`the infringement by its customers of the '633 Patent by, without authority, importing, selling and
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`offering to sell within the United States materials and apparatuses for practicing the claimed
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`invention of the '633 Patent both inside and outside the United States. For example, the above-
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`described products constitute a material part of the inventions of the '633 Patent and are not
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`staple articles or commodities of commerce suitable for substantial noninfringing use. On
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`information and belief, Intel knows that the above-described products constitute a material part
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`of the inventions of the '633 Patent and are not staple articles or commodities of commerce
`
`suitable for substantial noninfringing use. On information and belief, Intel’s customers directly
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`infringe the '633 Patent by, for example, making, using, offering to sell, and selling within the
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`United States, and importing into the United States, without authority or license, products
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`containing the above-described Intel products.
`
`34.
`
`As a result of Intel's infringement of the '633 Patent, VLSI has been damaged.
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`VLSI is entitled to recover for damages sustained as a result of Intel's wrongful acts in an amount
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`subject to proof at trial.
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`35.
`
`To the extent 35 U.S.C. § 287 is determined to be applicable, on information and
`
`belief its requirements have been satisfied with respect to the '633 Patent.
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`36.
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`In addition, Intel's infringing acts and practices have caused and are causing
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`immediate and irreparable harm to VLSI.
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`37.
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`VLSI is informed and believes, and thereon alleges, that the infringement of the
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`'633 Patent by Intel has been and continues to be willful. As noted above, Intel has long had
`
`knowledge of the '633 Patent. Intel has deliberately continued to infringe in a wanton, malicious,
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`and egregious manner, with reckless disregard for VLSI's patent rights. Thus, Intel's infringing
`
`actions have been and continue to be consciously wrongful.
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`38.
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`VLSI is informed and believes, and thereon alleges, that this is an exceptional
`
`case, which warrants an award of attorney's fees to VLSI pursuant to 35 U.S.C. § 285.
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`SECOND CLAIM
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`(Infringement of U.S. Patent No. 7,246,027)
`
`39.
`
`VLSI re-alleges and incorporates herein by reference Paragraphs 1-38 of its
`
`Complaint.
`
`40.
`
`The '027 Patent, entitled "Power optimization of a mixed-signal system on an
`
`integrated circuit," was duly and lawfully issued July 17, 2007. A true and correct copy of the
`
`'027 Patent is attached hereto as Exhibit 2.
`
`41.
`
`42.
`
`The '027 Patent names Marcus W. May and Matthew D. Felder as co-inventors.
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`The '027 Patent has been in full force and effect since its issuance. VLSI owns by
`
`assignment the entire right, title, and interest in and to the '027 Patent, including the right to seek
`
`damages for past, current, and future infringement thereof.
`
`43.
`
`The '027 Patent states that it "relates generally to portable electronic equipment
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`and more particularly to a sensing digital and analog parameters of an integrated circuit to
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`provide power supply optimization." Ex. 2 at 1:7-10.
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`44.
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`The '027 Patent explains "a need exists for an integrated circuit that provides
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`multiple functions through mixed-signal operation and architectures for handheld devices with
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`appropriate optimized power-consumption and with a minimal requirement of external
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`components." Ex. 2 at 2:32-36.
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`45.
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`The '027 Patent provides "a method and apparatus for conserving power of a
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`system-on-a-chip having analog circuitry. An aspect is a method and apparatus for increasing the
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`power supply efficiency of an integrated circuit, by determining an analog variation parameter
`
`that is representative of an integrated circuit fabrication process variance of the integrated circuit.
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`An operational temperature is determined, where the operational temperature is associated with
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`the analog variation parameter. With the analog variation parameter and the operational
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`temperature, an adjustment signal is determined for a power supply level of the integrated circuit,
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`such that power consumption of the integrated circuit is optimized." Ex. 2 at 2:40-51.
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`46.
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`VLSI is informed and believes, and thereon alleges, that Intel has infringed and
`
`unless enjoined will continue to infringe one or more claims of the '027 Patent, in violation of 35
`
`U.S.C. § 271, by, among other things, making, using, offering to sell, and selling within the
`
`United States, supplying or causing to be supplied in or from the United States, and importing
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`into the United States, without authority or license, Intel products with a Power Control Unit
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`(PCU) to compensate for Inverse Temperature Dependence (ITD) in an infringing manner.
`
`47.
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`The '027 accused products embody every limitation of at least claim 18 of the
`
`'027 Patent, literally or under the doctrine of equivalents, as set forth below. The further
`
`descriptions below, which are based on publicly available information, are preliminary examples
`
`and are non-limiting.
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`["A method for increasing power supply efficiency of an integrated circuit,
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`comprising:"]
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`48.
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`The '027 accused products use a method for increasing power supply efficiency of
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`an integrated circuit. For example, the PCU of the '027 accused products is designed to maximize
`
`the power supply efficiency of a microprocessor by using the "optimal voltage at all operating
`
`points" in a manner such as that shown below.
`
`
`
`["determining an analog variation parameter representative of an integrated circuit
`
`fabrication process variance of the integrated circuit; and"]
`
`49.
`
`The '027 accused products use a method that includes determining an analog
`
`variation parameter representative of an integrated circuit fabrication process variance of the
`
`integrated circuit. For example, Intel marketing materials demonstrate that the PCU of the '027
`
`accused products uses thermal sensors to estimate the temperature of the coldest point on the die
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`to compensate for Inverse Temperature Dependence using a process and architecture such as that
`
`described below.
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`
`
`["determining an adjustment signal for a power supply voltage level of the
`
`integrated circuit based on the analog variation parameter, and"]
`
`50.
`
`The '027 accused products use a method that includes determining an adjustment
`
`signal for a power supply voltage level of the integrated circuit based on the analog variation
`
`parameter. For example, Intel marketing materials demonstrate that the PCU interpolates linearly
`
`against test voltages to determine a power supply voltage level through a process that practices
`
`this element.
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`
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`51.
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`As a further example, public statements by Intel engineers also demonstrate that
`
`the PCU uses thermal information to adjust the power supply voltage level: "As temperature is
`
`lowered, the frequency of the chip can degrade because of the ITD effect (Inverse Temperature
`
`Dependence). In this case, information from the thermal sensor is used to raise the supply
`
`voltage to maintain performance." Dr. Peter Shor, http://www.ee.columbia.edu/compact-thermal-
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`sensors-intel-processors-90nm-22nm.
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`["adjusting a regulation signal of a DC-to-DC converter based on the adjustment
`
`signal to optimize power consumption of the integrated circuit."]
`
`52.
`
`The '027 accused products use a method that includes adjusting a regulation
`
`signal of a DC-to-DC converter based on the adjustment signal to optimize power consumption
`
`of the integrated circuit. For example, Intel marketing materials show that the PCU adjusts a
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`regulation signal of a voltage regulator, a DC-to-DC converter in a manner such as that described
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`below.
`
`
`
`53.
`
`As a further example, Intel technical documentation such as the specification
`
`included below demonstrates that '027 accused products adjust a regulation signal to a DC-to-DC
`
`converter via interfaces such as the "processor Serial Voltage IDentification (SVID) interface."
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`
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`https://www.intel.com/content/www/us/en/processors/core/3rd-gen-core-desktop-vol-1-
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`datasheet.html at 75.
`
`54.
`
`Intel has long had knowledge of the '027 Patent. For example, VLSI's predecessor
`
`Freescale provided notice of this patent to Intel on May 30, 2014. To the extent Intel claims it did
`
`not have broader actual knowledge of the '027 Patent, Intel has been willfully blind to that
`
`patent's existence based on, for example, its publicly-known corporate policy forbidding its
`
`employees from reading patents held by outside companies or individuals.
`
`55.
`
`VLSI is informed and believes, and thereon alleges, that Intel actively,
`
`knowingly, and intentionally has induced infringement of the '027 Patent by, for example,
`
`controlling the design and manufacture of, offering for sale, selling, supplying, and otherwise
`
`providing instruction and guidance regarding the above-described products with the knowledge
`
`and specific intent to encourage and facilitate infringing uses of such products by its customers
`
`both inside and outside the United States. For example, Intel publicly provides documentation,
`
`including datasheets available through Intel's publicly accessible ARK service and software
`
`developer's manuals, instructing customers on uses of Intel's products that infringe the methods
`
`of the '027 Patent. See, e.g., http://ark.intel.com. On information and belief, Intel’s customers
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`directly infringe the '027 Patent by, for example, making, using, offering to sell, and selling
`
`within the United States, and importing into the United States, without authority or license,
`
`products containing the above-described Intel products.
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`56.
`
`VLSI is informed and believes, and thereon alleges, that Intel has contributed to
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`the infringement by its customers of the '027 Patent by, without authority, importing, selling and
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`offering to sell within the United States materials and apparatuses for practicing the claimed
`
`invention of the '027 Patent both inside and outside the United States. For example, the above-
`
`described products constitute a material part of the inventions of the '027 Patent and are not
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`staple articles or commodities of commerce suitable for substantial noninfringing use. On
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`information and belief, Intel knows that the above-described products constitute a material part
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`of the inventions of the '027 Patent and are not staple articles or commodities of commerce
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`suitable for substantial noninfringing use. On information and belief, Intel’s customers directly
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`infringe the '027 Patent by, for example, making, using, offering to sell, and selling within the
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`United States, and importing into the United States, without authority or license, products
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`containing the above-described Intel products.
`
`57.
`
`As a result of Intel's infringement of the '027 Patent, VLSI has been damaged.
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`VLSI is entitled to recover for damages sustained as a result of Intel's wrongful acts in an amount
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`subject to proof at trial.
`
`58.
`
`To the extent 35 U.S.C. § 287 is determined to be applicable, on information and
`
`belief its requirements have been satisfied with respect to the '027 Patent.
`
`59.
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`In addition, Intel's infringing acts and practices have caused and are causing
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`immediate and irreparable harm to VLSI.
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`60.
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`VLSI is informed and believes, and thereon alleges, that the infringement of the
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`'027 Patent by Intel has been and continues to be willful. As noted above, Intel has long had
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`knowledge of the '027 Patent. Intel has deliberately continued to infringe in a wanton, malicious,
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`and egregious manner, with reckless disregard for VLSI's patent rights. Thus, Intel's infringing
`
`actions have been and continue to be consciously wrongful.
`
`61.
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`VLSI is informed and believes, and thereon alleges, that this is an exceptional
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`case, which warrants an award of attorney's fees to VLSI pursuant to 35 U.S.C. § 285.
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`THIRD CLAIM
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`(Infringement of U.S. Patent No. 7,247,552)
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`62.
`
`VLSI re-alleges and incorporates herein by reference Paragraphs 1-61 of its
`
`Complaint.
`
`63.
`
`The '552 Patent, entitled "Integrated circuit having structural support for a flip-
`
`chip interconnect pad and method therefor," was duly and lawfully issued July 24, 2007. A true
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`and correct copy of the '552 Patent is attached hereto as Exhibit 3.
`
`64.
`
`The '552 Patent names Scott K. Pozder, Kevin J. Hess, Pak K. Leung, Edward O.
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`Travis, Brett P. Wilkerson, David G. Wontor, and Jie-Hua Zhao as co-inventors.
`
`65.
`
`The '552 Patent has been in full force and effect since its issuance. VLSI owns by
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`assignment the entire right, title, and interest in and to the '552 Patent, including the right to seek
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`damages for past, current, and future infringement thereof.
`
`66.
`
`The '552 Patent states that it "relates to packaged semiconductors and more
`
`particularly to interconnect pads of integrated circuits for making electrical connection to
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`underlying conductive layers." Ex. 3 at 1:18-21.
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`Case 1:18-cv-00966-VAC-CJB Document 1 Filed 06/28/18 Page 20 of 47 PageID #: 20
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`67.
`
`The '552 Patent provides "a method and apparatus for providing structural support
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`for interconnect pad locations in an integrated circuit (IC) by using novel layout techniques in
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`the metallization and dielectric stack underlying the pad. As used herein, an interconnect pad,
`
`formed of metal, is placed at the surface of an integrated circuit where an electrical connection is
`
`made from the pad to one or more underlying interconnect layers. In a typical IC design, multiple
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`interconnect layers separated by interlevel dielectrics are formed in a stack to provide the
`
`required interconnections between devices in the semiconductor substrate." Ex. 3 at 2:31-42.
`
`68.
`
`VLSI is informed and believes, and thereon alleges, that Intel has infringed and
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`unless enjoined will continue to infringe one or more claims of the '552 Patent, in violation of 35
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`U.S.C. § 271, by, among other things, making, using, offering to sell, and selling within the
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`United States, supplying or causing to be supplied in or from the United States, and importing
`
`into the United States, without authority or license, Intel products with metal dummy lines to
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`reinforce regions under bond pads in an infringing manner.
`
`69.
`
`The '552 accused products embody every limitation of at least claim 11 of the
`
`'552 Patent, literally or under the doctrine of equivalents, as set forth below. The further
`
`descriptions below, which are based on publicly available information, are preliminary examples
`
`and are non-limiting.
`
`["A method of making an integrated circuit having a plurality of bond pads,
`
`comprising:"]
`
`70.
`
`The '552 accused products are manufactured using a method of making an
`
`integrated circuit having a plurality of bond pads.
`
`71.
`
`For example, electron micrographs of Intel products, including the i7-4770
`
`processor, show a plurality of bond pads:
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`
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`["developing a circuit design of the integrated circuit;"]
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`72.
`
`The '552 accused products are manufactured using a method that includes
`
`developing a circuit design of the integrated circuit.
`
`73.
`
`For example, electron micrographs of Intel products, including the i7-4770
`
`processor, show a circuit design made up of gates and interconnecting wires:
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`Case 1:18-cv-00966-VAC-CJB Document 1 Filed 06/28/18 Page 22 of 47 PageID #: 22
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`
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`["developing a layout of the integrated circuit according to the circuit design,
`
`wherein the layout comprises a plurality of interconnect layers underlying a first
`
`bond pad of the plurality of bond pads, at least one of the plurality of interconnect
`
`layers not being electrically connected to the first bond pad and used for wiring or
`
`interconnect other than directly to the first bond pad;"]
`
`74.
`
`The '552 accused products are manufactured using a method that includes
`
`developing a layout of the integrated circuit according to the circuit design, wherein the layout
`
`comprises a plurality of interconnect layers underlying a first bond pad of the plurality of bond
`
`pads, at least one of the plurality of interconnect layers not being electrically connected to the
`
`first bond pad and used for wiring or interconnect other than directly to the first bond pad.
`
`75.
`
`For example, electron micrographs of Intel products, including the i7-4770
`
`processor, show several interconnect layers underlying the bond pads.
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`76.
`
`Some, but not all, of the interconnects on various interconnect layers are
`
`electrically connected using vias to the bond pads, in such a way that practices this element.
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`Case 1:18-cv-00966-VAC-CJB Document 1 Filed 06/28/18 Page 24 of 47 PageID #: 24
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`
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`["defining a force region at least under the first bond pad of the plurality of bond
`
`pads, wherein the force region comprises a first portion of each o