Case 1:19-cv-02149-UNA Document 1 Filed 11/15/19 Page 1 of 32 PageID #: 1
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
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`MONTEREY RESEARCH, LLC,
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`ADVANCED MICRO DEVICES, INC.,
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`v.
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`Plaintiff,
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`Defendant.
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`C.A. No. ________________
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`JURY TRIAL DEMANDED
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`))))))))))
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`COMPLAINT FOR PATENT INFRINGEMENT
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`Plaintiff Monterey Research, LLC (“Monterey”), for its Complaint for Patent Infringement
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`against Defendant Advanced Micro Devices, Inc. (“AMD”), alleges as follows:
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`INTRODUCTION
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`1.
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`Monterey is an intellectual property and technology licensing company. Monterey’s
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`patent portfolio comprises over 2,700 active and pending patents worldwide, including approximately
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`2,000 active United States patents. Monterey’s patent portfolio stems from technology developed by
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`a number of leading high-technology companies, including Cypress Semiconductor Corporation,
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`Fujitsu, NVX Corporation, and Ramtron. Those companies developed key innovations that have
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`greatly enhanced the capabilities of computer systems, increased electronic device processing power,
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`and reduced electronic device power consumption. Among other things, those inventions produced
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`significant technological advances, including smaller, faster, and more efficient semiconductors and
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`integrated circuits.
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`2.
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`AMD infringes Monterey’s patents by making, using, selling, offering for sale, and/or
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`importing products (including importing products made by a patented process) throughout the United
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`States, including within this District. AMD’s customers incorporate those products into downstream
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`products that are made, used, sold, offered for sale, and/or imported throughout the United States,
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`including within this District. Those downstream products include, but are not limited to,
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`motherboards, desktop computers, servers, laptop computers, videogame consoles, and other
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`products that include AMD semiconductor devices and integrated circuits.
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`3.
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`AMD has infringed and continues to infringe Monterey’s patents. AMD has thus far
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`refused to license those patents and, instead, has continued to make, use, sell, offer to sell, and/or
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`import Monterey’s intellectual property within the United States without Monterey’s permission.
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`NATURE OF THE CASE
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`4.
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`This action arises under 35 U.S.C. § 271 for AMD’s infringement of Monterey’s
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`United States Patent Nos. 6,534,805 (“the ’805 patent”); 6,629,226 (“the ’226 patent”); 6,651,134
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`(“the ’134 patent”); 6,765,407 (“the ’407 patent”); 6,961,807 (“the ’807 patent”); and 8,373,455 (“the
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`’455 patent”) (collectively, “the Patents-in-Suit”).
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`THE PARTIES
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`5.
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`Plaintiff Monterey is a Delaware limited liability company with offices in New Jersey
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`and California. Monterey maintains a registered agent for service in Delaware: Intertrust Corporate
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`Services Delaware Ltd. located at 200 Bellevue Parkway, Suite 210, Wilmington, Delaware 19808.
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`6.
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`Defendant AMD is a Delaware corporation with a principal place of business at 2485
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`Augustine Drive, Santa Clara, California 95054. AMD is a publicly traded company that may be
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`served through its registered agent for service, The Corporation Trust Company, 1209 Orange Street,
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`Wilmington, Delaware 19801.
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`JURISDICTION AND VENUE
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`7.
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`This Court has jurisdiction over the subject matter of this action under 28 U.S.C. §§
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`1331 and 1338(a) at least because this action arises under the patent laws of the United States,
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`including 35 U.S.C. § 271 et seq.
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`8.
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`Personal jurisdiction exists over AMD at least because AMD is a Delaware
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`corporation organized under the laws of the State of Delaware. AMD also has a registered agent for
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`service of process in Delaware. In addition, AMD has committed, aided, abetted, contributed to,
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`and/or participated in the commission of acts of infringement giving rise to this action within the
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`State of Delaware by, inter alia, directly and/or indirectly making, using, selling, offering for sale,
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`importing products, and/or practicing methods that practice one or more claims of the Patents-in-Suit.
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`Furthermore, AMD has transacted and conducted business in the State of Delaware and with
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`Delaware residents by making, using, selling, offering to sell, and/or importing (including importing
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`products made by a patented process) products and instrumentalities that practice one or more claims
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`of the Patents-in-Suit. Among other things, AMD, directly and/or through intermediaries, uses, sells,
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`ships, distributes, imports into, offers for sale, and/or advertises or otherwise promotes its products
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`throughout the United States, including in the State of Delaware. See, e.g., www.amd.com/en. At
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`least for those reasons, AMD has the requisite minimum contacts within the forum such that the
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`exercise of jurisdiction over AMD would not offend traditional notions of fair play and substantial
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`justice.
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`9.
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`Venue is proper in this Court pursuant to 28 U.S.C. §§ 1391(b) and (c) and 1400(b).
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`AMD resides in this district and has committed acts of infringement in this district. AMD has
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`committed acts of infringement in this district by, among other things, selling and offering for sale in
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`this district (and elsewhere) infringing products made, used, developed, tested, and otherwise
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`practiced by AMD. Venue is further proper based on the facts alleged in the preceding paragraphs,
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`which Monterey incorporates by reference as if fully set forth herein.
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`THE PATENTS-IN-SUIT
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`10. Monterey incorporates by reference the preceding paragraphs as if fully set forth
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`herein.
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`3
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`A.
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`U.S. Patent No. 6,534,805
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`11.
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`The ’805 patent, titled “SRAM Cell Design,” was duly and properly issued by the
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`United States Patent and Trademark Office (“USPTO”) on March 18, 2003. On October 14, 2014,
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`the USPTO issued an Ex Parte Reexamination Certificate for the ’805 patent, which confirmed the
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`patentability of the ’805 patent. A true and correct copy of the ’805 patent and the Ex Parte
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`Reexamination Certificate for the ’805 patent is attached hereto as Exhibit A.
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`12. Monterey is the owner and assignee of the ’805 patent; owns all right, title, and interest
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`in the ’805 patent; and holds the right to sue and recover damages for infringement thereof, including
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`past infringement.
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`B.
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`U.S. Patent No. 6,629,226
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`13.
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`The ’226 patent, titled “FIFO Read Interface Protocol,” was duly and properly issued
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`by the USPTO on September 30, 2003. A true and correct copy of the ’226 patent is attached hereto
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`as Exhibit B.
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`14. Monterey is the owner and assignee of the ’226 patent; owns all right, title, and interest
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`in the ’226 patent; and holds the right to sue and recover damages for infringement thereof, including
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`past infringement.
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`C.
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`U.S. Patent No. 6,651,134
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`15.
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`The ’134 patent, titled “Memory Device with Fixed Length Non Interruptible Burst,”
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`was duly and properly issued by the USPTO on November 18, 2003. A true and correct copy of the
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`’134 patent is attached hereto as Exhibit C.
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`16. Monterey is the owner and assignee of the ’134 patent; owns all right, title, and interest
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`in the ’134 patent; and holds the right to sue and recover damages for infringement thereof, including
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`past infringement.
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`D.
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`U.S. Patent No. 6,765,407
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`17.
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`The ’407 patent, titled “Digital Configurable Macro Architecture,” was duly and
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`properly issued by the USPTO on July 20, 2004. A true and correct copy of the ’407 patent is attached
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`hereto as Exhibit D.
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`18. Monterey is the owner and assignee of the ’407 patent; owns all right, title, and interest
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`in the ’407 patent; and holds the right to sue and recover damages for infringement thereof, including
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`past infringement.
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`E.
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`U.S. Patent No. 6,961,807
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`19.
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`The ’807 patent, titled “Device, System and Method for an Integrated Circuit
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`Adaptable for Use in Computing Systems of Differing Memory Requirements,” was duly and
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`properly issued by the USPTO on November 1, 2005. A true and correct copy of the ’807 patent
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`is attached hereto as Exhibit E.
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`20. Monterey is the owner and assignee of the ’807 patent; owns all right, title, and
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`interest in the ’807 patent; and holds the right to sue and recover damages for infringement thereof,
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`including past infringement.
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`F.
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`U.S. Patent No. 8,373,455
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`21.
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`The ’455 patent, titled “Output Buffer Circuit,” was duly and properly issued by
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`the USPTO on February 12, 2013. A true and correct copy of the ’455 patent is attached hereto as
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`Exhibit F.
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`22. Monterey is the owner and assignee of the ’455 patent; owns all right, title, and
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`interest in the ’455 patent; and holds the right to sue and recover damages for infringement thereof,
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`including past infringement.
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`FACTUAL BACKGROUND
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`23. Monterey incorporates by reference the preceding paragraphs as if fully set forth
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`5
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`herein.
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`24.
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`The Patents-in-Suit stem from the research and design of innovative and proprietary
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`technology developed by leading high-technology companies, including Cypress Semiconductor
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`Corporation (“Cypress”). Cypress is an American multinational company and pioneer of cutting-
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`edge semiconductor technology. Founded in 1982, Cypress has made substantial investments in
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`researching, developing, and manufacturing high-quality semiconductor devices, integrated circuits,
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`and products containing the same.
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`25.
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`The Patents-in-Suit are directed to inventive technology relating to semiconductor
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`devices, integrated circuits, and/or products containing the same.
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`26.
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`Defendant AMD works closely with its customers, OEMs, foundry suppliers,
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`distributors, and/or other third parties to make, use, sell, offer to sell, and/or import semiconductor
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`devices, integrated circuits, and/or products containing the same. Among other things, AMD
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`optimizes its manufacturing process for its customers and optimizes its products for integration into
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`downstream products. AMD’s affirmative acts in furtherance of the manufacture, use, sale, offer to
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`sell, and importation of its products in and/or into the United States include, but are not limited to,
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`any one or combination of: (i) designing specifications for manufacture of its products; (ii)
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`collaborating on, encouraging, and/or funding the development of processes for the manufacture of
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`its products; (iii) soliciting and/or sourcing the manufacture of its products; (iv) licensing, developing,
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`and/or transferring technology and know-how to enable the manufacture of its products; (v) enabling
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`and encouraging the use, sale, or importation of its products in the United States; and (vi) advertising
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`its products and/or downstream products incorporating them in the United States.
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`27.
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`AMD also provides marketing and/or technical support services for its products from
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`its facilities in the United States. For example, AMD maintains a website that advertises its products,
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`including identifying the applications for which they can be used and providing specifications for its
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`products. See, e.g., www.amd.com/en. AMD’s publicly-available website also contains user
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`manuals, product documentation, and other materials related to its products. See, e.g.,
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`www.amd.com/en. For example, AMD’s website contains a knowledge base, software help center,
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`support
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`forum,
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`technical documents, and downloadable graphics drivers.
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` See, e.g.,
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`www.amd.com/en.
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`COUNT ONE
`INFRINGEMENT OF THE ’805 PATENT
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`28. Monterey incorporates by reference the preceding paragraphs as if fully set forth
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`herein.
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`29. Monterey is the assignee and lawful owner of all right, title, and interest in and to the
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`’805 patent.
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`30.
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`31.
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`The ’805 patent is valid and enforceable.
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`The ’805 patent is generally directed to static random access memory (“SRAM”) cell
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`design, particularly to optimizing SRAM cell design using a simpler geometric layout.
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`32.
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`As semiconductor structure size continued to shrink with time, one exemplary issue
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`with the prior art of the ’805 patent was increased difficulties in manufacturing. Specifically, the
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`then-existing memory cells contained complex geometric designs which required numerous
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`processing steps and larger cell sizes. Generally, more processing steps lead to increased
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`manufacturing costs and reduced profits.
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`33.
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`The ’805 patent teaches, among other things, an improved memory cell layout which
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`allows the features to be arranged in such a way as to minimize cell size. For example, the single
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`local interconnect layer of the ’805 patent allows for a thinner product and fewer processing steps.
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`34.
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`AMD products use SRAM with a six-transistor (“6T”) and/or eight-transistor (“8T”)
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`cell design. AMD’s 6T and 8T SRAM contain a single local interconnect layer. This has resulted
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`in, among other things, AMD’s ability to decrease the size of its SRAM area and to decrease the
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`number of manufacturing steps.
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`35.
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`AMD has directly infringed, and continues to directly infringe, one or more claims of
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`the ’805 patent under 35 U.S.C. § 271(a), either literally and/or under the doctrine of equivalents, by,
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`among other things, making, using, selling, offering to sell, and/or importing in or into the United
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`States without authorization products covered by one or more claims of the ’805 patent, including,
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`but not limited to, all AMD devices incorporating SRAM with a 6T and/or 8T cell design, such as
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`the A8-3800 semiconductor device and other products in the A-Series, Pro A-Series, Ryzen, Ryzen
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`Pro, Athlon, Epyc, FX, E-Series, Opteron, Phenom, Sempron, and the Turion product families; and
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`all other semiconductor devices, integrated circuits, and products with similar infringing technology
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`(“the Accused ’805 Products”).
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`36.
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`As one non-limiting example, AMD infringes claim 8 of the ’805 patent. For example,
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`the A8-3800 semiconductor device contains:
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`a.
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`a memory cell (e.g., SRAM cell of the A8-3800) comprising a plurality of
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`substantially oblong active regions (e.g., N-type and/or P-type diffusion areas of the A8-3800)
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`formed in a semiconductor substrate and arranged substantially in parallel with one another, and a
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`plurality of substantially oblong local interconnects (e.g., structures formed at the polysilicon layer
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`on top of the substrate of the A8-3800) above said substrate that extend only partially across the
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`memory cell and are arranged substantially in parallel with one another and substantially
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`perpendicular to said active regions; and
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`b.
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`a single local interconnect layer (e.g., metal 1 (“M1”) layer of the A8-3800)
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`comprising local interconnects (e.g., structures formed at the M1 layer of the A8-3800)
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`corresponding to bitlines (e.g., those formed at the metal 2 (“M2”) layer of the A8-3800) and a
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`global word-line (e.g., those formed at the metal 3 (“M3”) layer of the A8-3800).
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`37.
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`Claim 8 of the ’805 patent applies to each Accused ’805 Product at least because each
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`of those products contain the same or similar structures as the AMD A8-3800.
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`38.
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`AMD has induced infringement of, and continues to induce infringement of, one or
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`more claims of the ’805 patent under 35 U.S.C. § 271(b), either literally and/or under the doctrine of
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`equivalents, by, among other things, actively inducing others, including its customers, to make, use,
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`sell, offer to sell, and/or import in or into the United States without authorization the Accused ’805
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`Products, as well as products containing the same. AMD knowingly and intentionally instructs its
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`customers, OEMs, foundry suppliers, distributors, and/or third parties to infringe at least through user
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`manuals, product documentation, and other materials, such as those located on AMD’s website at
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`www.amd.com/en. Additional non-limiting examples include the materials found on AMD’s
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`websites
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`at
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`www.amd.com/en/processors/athlon-and-a-series
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`and
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`www.amd.com/en/products/specifications/processors/.
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`39.
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`AMD has contributed to the infringement of, and continues to contribute to the
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`infringement of, one or more claims of the ’805 patent under 35 U.S.C. § 271(c), either literally and/or
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`under the doctrine of equivalents, by, among other things, selling, offering to sell, and/or importing
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`in or into the United States the Accused ’805 Products, which constitute a material part of the
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`invention of the ’805 patent, knowing the Accused ’805 Products to be especially made or especially
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`adapted for use in an infringement of such patent, and not a staple article or commodity of commerce
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`suitable for substantial noninfringing use.
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`40. Monterey has sustained and is entitled to recover damages as a result of AMD’s
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`infringement.
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`41.
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`AMD’s infringement of the ’805 patent has been knowing, deliberate, and willful,
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`beginning at least as early as the date Monterey filed the complaint in this action and therefore at least
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`the date by which AMD knew of the ’805 patent and that its conduct constituted and resulted in
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`infringement of the ’805 patent. AMD nonetheless has committed—and continues to commit—acts
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`of direct and indirect infringement despite knowing that its actions constituted infringement of the
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`valid and enforceable ’805 patent, despite a risk of infringement that was known or so obvious that it
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`should have been known to AMD, and/or even though AMD otherwise knew or should have known
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`that its actions constituted an unjustifiably high risk of infringement of that valid and enforceable
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`patent. AMD’s conduct in light of these circumstances is egregious. AMD’s knowing, deliberate,
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`and willful infringement of the ’805 patent entitles Monterey to increased damages under 35 U.S.C.
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`§ 284 and to attorney fees and costs incurred in prosecuting this action under 35 U.S.C. § 285.
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`COUNT TWO
`INFRINGEMENT OF THE ’226 PATENT
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`42. Monterey incorporates by reference the preceding paragraphs as if fully set forth
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`herein.
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`43. Monterey is the assignee and lawful owner of all right, title, and interest in and to the
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`’226 patent.
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`44.
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`45.
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`The ’226 patent is valid and enforceable.
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`The ’226 patent is generally directed to a method and/or architecture for implementing
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`a multiqueue memory read interface, and more particularly, to a method and/or architecture for
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`implementing a multiqueue read interface protocol for eliminating synchronizing problems for
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`configuration dependent latencies where the protocol may be capable of handling variable size
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`packets.
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`46.
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`The ’226 patent explains that in prior multiqueue memories (e.g., first-in-first-out
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`(“FIFO”) memory), a signal, e.g., ADDRESS, was a queue address configured to determine a queue
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`number of the multiqueue memory. The signals, e.g., READ_CLOCK and READ_EN, could control
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`the timing of the presentation of the data signal, e.g., DATA. Because of particular architectures and
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`specifications of particular devices, the latency between enabling a queue address signal, e.g.,
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`ADDRESS, and presenting a data signal, e.g., DATA, could differ depending on the particular
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`configuration. Configuration information needed to be written into an external read device. The only
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`event reference available to the external read device was an end of packet or a start of packet, e.g.,
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`EOP or SOP. In such an environment, the read device was required to monitor this event to generate
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`the queue address signal, e.g., ADDRESS, in a sufficient number of cycles ahead of the read.
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`47.
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`These prior multiqueue memory systems had the disadvantage of requiring a fixed
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`packet size. This circuit could be required to generate the queue address, e.g., ADDRESS, a certain
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`number of cycles before the end of packet occurs. The particular number of cycles may be the same
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`as the minimum latency requirement. For certain configurations, there was a specific latency between
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`the queue address signal, e.g., ADDRESS, and presenting the signal, e.g., DATA. If the packet size
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`varied randomly, such as when the size of the packet was less than the number of cycles of latency,
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`a read of one or more unwanted packets occurred. Additionally, it may have been difficult for the
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`read device to synchronize the queue address signal, e.g., ADDRESS, with the data received from
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`the memory (e.g., FIFO). Therefore, the read device needed to be configured with enough logic to
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`respond to the different latencies. Such a configuration required extra overhead for the read device.
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`48.
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`The ’226 patent teaches, among other things, an interface coupled to a multiqueue
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`storage device and configured to interface the multiqueue storage device with one or more
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`handshaking signals. The multiqueue storage device and the interface may be configured to transfer
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`variable size data packets. Such a system provided numerous benefits, including but not limited to:
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`(i) eliminating synchronizing problems with configuration dependent latencies; (ii) being capable of
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`handling variable size packets; (iii) allowing back-to-back reads of variable size packets; and (iv)
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`exchanging address and data between an external read device and a multiqueue storage device.
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`49.
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`AMD products use a multiqueue storage device, such as an NVM Express (“NVME”)
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`compliant memory. For example, NVME compliant memory can be found in, among other products,
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`the AMD Pro SSG. AMD products use multiqueue storage devices that are compliant with the
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`NVME Base Specification standard and similar versions of the NVME standard that incorporate the
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`innovations of the ʼ226 patent’s multiqueue memory read interface. AMD’s multiqueue storage
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`device further interfaces with handshaking signals, and allows back-to-back reads of variable size
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`data packets.
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`50.
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`AMD has directly infringed, and continues to directly infringe, one or more claims of
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`the ’226 patent under 35 U.S.C. § 271(a), either literally and/or under the doctrine of equivalents, by,
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`among other things, making, using, selling, offering to sell, and/or importing in or into the United
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`States without authorization products covered by one or more claims of the ’226 patent, including,
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`but not limited to, products supporting NVME or with NVME compliant memory, such as the Radeon
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`Pro SSG semiconductor device and other products in the Radeon Pro, Epyc and Ryzen product
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`families; other AMD semiconductor devices, integrated circuits, and products built to utilize NVME
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`compliant memory; and all other semiconductor devices, integrated circuits, and products using a
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`similar multiqueue memory read interface (“the Accused ’226 Products”).
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`51.
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`As one non-limiting example, AMD infringes claim 18 of the ’226 patent. For
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`example, the Radeon Pro SSG semiconductor device contains: An interface coupled to a multiqueue
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`storage device (e.g., multiqueue memory of the Radeon Pro SSG) and configured to interface said
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`multiqueue storage device with one or more handshaking signals (e.g., data link packets and/or
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`command set of the Radeon Pro SSG), wherein said multiqueue storage device and said interface are
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`configured to allow back-to-back reads of variable size data packets (e.g., via sequential read requests
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`and/or burst read requests, and/or a Scatter Gather List of the Radeon Pro SSG).
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`52.
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`Claim 18 of the ’226 patent applies to each Accused ’226 Product at least because
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`each of those products contain infringing NVME compliant memory; and/or contain a multiqueue
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`storage device with similar infringing functionality.
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`53.
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`AMD has induced infringement of, and continues to induce infringement of, one or
`
`more claims of the ’226 patent under 35 U.S.C. § 271(b), either literally and/or under the doctrine of
`
`equivalents, by, among other things, actively inducing others, including its customers, to make, use,
`
`sell, offer to sell, and/or import (including import products made by a patented process) in or into the
`
`United States without authorization the Accused ’226 Products, as well as products containing the
`
`same. AMD knowingly and intentionally instructs its customers, OEMs, foundry suppliers,
`
`distributors, and/or other third parties to infringe at least through user manuals, product
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`documentation, and other materials, such as those located on AMD’s website at www.amd.com/en.
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`Additional non-limiting examples
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`include
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`the materials found on AMD’s websites at
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`www.amd.com/en/chipsets/str40 and www.amd.com/en/chipsets/x570.
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`54.
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`AMD has contributed to the infringement of, and continues to contribute to the
`
`infringement of, one or more claims of the ’226 patent under 35 U.S.C. § 271(c), either literally and/or
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`under the doctrine of equivalents, by, among other things, selling, offering to sell, and/or importing
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`in or into the United States the Accused ’226 Products, which constitute a material part of the
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`invention of the ’226 patent, knowing the Accused ’226 Products to be especially made or especially
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`adapted for use in an infringement of such patent, and not a staple article or commodity of commerce
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`suitable for substantial noninfringing use.
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`Case 1:19-cv-02149-UNA Document 1 Filed 11/15/19 Page 14 of 32 PageID #: 14
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`55. Monterey has sustained and is entitled to recover damages as a result of AMD’s
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`infringement.
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`56.
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`AMD’s infringement of the ’226 patent has been knowing, deliberate, and willful,
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`beginning at least as early as the date Monterey filed the complaint in this action and therefore at least
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`the date by which AMD knew of the ’226 patent and knew that its conduct constituted and resulted
`
`in infringement of the ’226 patent. AMD nonetheless has committed—and continues to commit—
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`acts of direct and indirect infringement despite knowing that its actions constituted infringement of
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`the valid and enforceable ’226 patent, despite a risk of infringement that was known or so obvious
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`that it should have been known to AMD, and/or even though AMD otherwise knew or should have
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`known that its actions constituted an unjustifiably high risk of infringement of that valid and
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`enforceable patent. AMD’s conduct in light of these circumstances is egregious. AMD’s knowing,
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`deliberate, and willful infringement of the ’226 patent entitles Monterey to increased damages under
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`35 U.S.C. § 284 and to attorney fees and costs incurred in prosecuting this action under 35 U.S.C. §
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`285.
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`herein.
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`COUNT THREE
`INFRINGEMENT OF THE ’134 PATENT
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`57. Monterey incorporates by reference the preceding paragraphs as if fully set forth
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`58. Monterey is the assignee and lawful owner of all right, title, and interest in and to the
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`’134 patent.
`
`59.
`
`60.
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`The ’134 patent is valid and enforceable.
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`The ’134 patent generally concerns memory devices, and is more specifically related
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`to non-interruptible burst read and write access features, as described in JEDEC standard JESD212
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`GDDR5 SGRAM and similar versions of the JEDEC GDDRx standards.
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`Case 1:19-cv-02149-UNA Document 1 Filed 11/15/19 Page 15 of 32 PageID #: 15
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`61.
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`The ʼ134 patent provides a faster and more efficient way for burst read and write
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`access over conventional DRAM devices existing when the patent was filed in early 2000. A
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`conventional DRAM may need an interrupt to perform data refreshes. Prior to the ʼ134 patent,
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`DRAM memory devices had a burst mode that had the possibility of needing to continually perform
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`interrupts to perform data refreshes.
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`62.
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`The ’134 patent teaches, among other things, a fixed burst memory that can have non-
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`interruptible bursts, hide required DRAM refreshes inside a known fixed burst length, free up the
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`address and control busses for multiple cycles, and operate at higher frequencies without needing
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`interrupts to perform refreshes of data.
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`63.
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`AMD products use memory devices that are compliant with the JESD212 GDDR5
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`SGRAM standard and similar versions of the JEDEC GDDRx standards that incorporate the
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`innovations of the ʼ134 patent’s non-interruptible fixed burst length.
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`64.
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`AMD has directly infringed, and continues to directly infringe, one or more claims of
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`the ’134 patent under 35 U.S.C. § 271(a), either literally and/or under the doctrine of equivalents, by,
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`among other things, making, using, selling, offering to sell, and/or importing in or into the United
`
`States without authorization products covered by one or more claims of the ’134 patent, including,
`
`but not limited to, products that comply with the JEDEC standards JESD212 GDDR5 SGRAM and
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`similar versions of the JEDEC GDDRx standards that use non-interruptible burst read or write
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`operations, such as the Radeon RX 580 graphics card and other products in the Radeon, Radeon Pro,
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`Embedded Radeon, Mobility Platforms, Instinct, FireStream, and the FirePro product families; the
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`Neo and Liverpool graphics processors; other AMD semiconductor devices, integrated circuits, and
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`products that are compliant with the JESD212 GDDR5 SGRAM standard or similar versions; and all
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`other semiconductor devices, integrated circuits, and products with similar infringing technology
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`Case 1:19-cv-02149-UNA Document 1 Filed 11/15/19 Page 16 of 32 PageID #: 16
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`(“the Accused ’134 Products”).
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`65.
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`As one non-limiting example, AMD infringes claim 1 of the ’134 patent since the
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`AMD Radeon RX 580 semiconductor device contains DDR3 SGRAM memory controllers that
`
`operate in conformance with JEDEC’s DDR3 SGRAM standard. For example, the AMD Radeon
`
`RX 580 contains a circuit comprising:
`
`a.
`
`a memory comprising a plurality of storage elements (e.g., banks of storage
`
`elements of the Radeon RX 580);
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`b.
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`each configured to read and write data in response to an internal address
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`signal (e.g., stored bits of memory bank addressed and defined by internal addresses of the Radeon
`
`RX 580);
`
`c.
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`a logic circuit configured to generate a predetermined number of said
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`internal address signals (e.g., generating addresses based on bank addresses, row addresses, and
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`column addresses of the Radeon RX 580) in response to an external address signal (e.g., read
`
`and/or write signals of the Radeon RX 580), a clock signal (e.g., clock signal of the Radeon RX
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`580), and one or more control signals (e.g., control signal of the Radeon RX 580);
`
`d.
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`wherein said generation of said predetermined number of internal address
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`signals is non-interruptible (e.g., burst reads or writes cannot be terminated or interrupted in the
`
`Radeon RX 580).
`
`66.
`
`Claim 1 of the ’134 patent applies to each Accused ’134 Product at least because each
`
`of those products either complies with the same JEDEC JESD212 GDDR5 SGRAM standard, or
`
`similar versions of the JEDEC standard, which result in infringing features (e.g., non-interruptible
`
`burst oriented read or write operations of the Accused ’134 Products) found in the JESD212 GDDR5
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`SGRAM standard.
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`Case 1:19-cv-02149-UNA Document 1 Filed 11/15/19 Page 17 of 32 PageID #: 17
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`67.
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`AMD has induced infringement of, and continues to induce infringement of, one or
`
`more claims of the ’134 patent under 35 U.S.C. § 271(b), either literally and/or under the doctrine of
`
`equivalents, by, among other things, actively inducing others, including its customers, to make, use,
`
`sell, offer to sell, and/or import in or into the United States without authorization the Accused ’134
`
`Products, as well as products containing the same. AMD knowingly and intentionally instructs its
`