`
`UNITED STATES INTERNATIONAL TRADE COMMISSION
`Washington, D.C.
`
`Before the Honorable Clark S. Cheney
`Chief Administrative Law Judge
`
`
`
`In the Matter of
`
`CERTAIN SEMICONDUCTOR
`DEVICES HAVING LAYERED DUMMY
`FILL, ELECTRONIC DEVICES, AND
`COMPONENTS THEREOF
`
`
`
`Inv. No. 337-TA-1342
`
`COMMISSION INVESTIGATIVE STAFF’S
`MARKMAN BRIEF
`
`
`
`March 29, 2023
`
`
`
`Margaret D. Macdonald, Director
`Jeffrey T. Hsu, Supervisory Attorney
`John K. Shin, Investigative Attorney
`
`OFFICE OF UNFAIR IMPORT INVESTIGATIONS
`U.S. International Trade Commission
`500 E Street, S.W., Suite 401
`Washington, D.C. 20436
`(202) 205-3117
`
`
`
`
`

`

`
`
` 
`
` 
`
` 
`
` 
`
`C. 
`
`D. 
`
`2. 
`
`TABLE OF CONTENTS
`INTRODUCTION............................................................................................................. 1 
`GENERAL CLAIM CONSTRUCTION PRINCIPLES ............................................... 1 
`BACKGROUND ............................................................................................................... 2 
`A. 
`Overview of the ‘760 Patent ................................................................................... 2 
`B. 
`The ’760 File History .............................................................................................. 5 
`C. 
`One of Ordinary Skill in the Art ............................................................................. 6 
`PROPER CONSTRUCTION OF THE DISPUTED CLAIM TERMS ....................... 7 
`A. 
`Independent Claim 1 of the ’760 Patent ................................................................. 7 
`B. 
`1st Disputed Claim Term: “dummy fill space”....................................................... 8 
`1. 
`Staff’s construction is correct based on the intrinsic evidence. .................. 8 
`2. 
`Complainant’s proposal is overly broad. .................................................... 9 
`2nd Disputed Claim Terms: “a first dummy fill space [for a first layer]”; and “a
`second dummy fill space [for a second layer]” ..................................................... 11 
`Staff’s construction correctly addresses the span of each “dummy fill
`1. 
`space.” ....................................................................................................... 11 
`Complainant offers no substantive construction yet argues for an
`arbitrary scope. .......................................................................................... 14 
`3rd Disputed Claim Term: “re-arranging a plurality of first dummy fill features
`and a plurality of second dummy fill features” ..................................................... 15 
`1. 
`“Re-arranging” has a commonly understood meaning of “moving.” ....... 16 
`2. 
`Complainant offers no substantive construction but argues for an
`unsupported, broad meaning for “re-arranging.” ...................................... 18 
`4th Disputed Claim Term: “minimizing the overlap” ........................................... 19 
`1. 
`The claim term “minimizing the overlap” is indefinite. ............................ 20 
`2. 
`Complainant’s newly proposed construction is still indefinite and should
`be rejected. ................................................................................................ 24 
`5th Disputed Claim Term: “total bulk capacitance is minimized” ....................... 25 
`1. 
`The claim term “total bulk capacitance is minimized” is indefinite. ........ 26 
`2. 
`If the claim term is not indefinite, then Staff’s alternative proposal should
`be adopted. ................................................................................................ 29 
`6th Disputed Claim Term: [The method described in claim 11, wherein] “the bulk
`inter-layer capacitance is a bulk capacitance created by overlaps between the first
`layer and the second layer” ................................................................................... 30 
`1. 
`Dependent Claim 13 is indefinite because it lacks antecedent basis. ....... 30 
`
`E. 
`
`F. 
`
`G. 
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`2. 
`
`Complainant’s proposed correction should be denied because there is
`reasonable debate as to two reasonable correction options. ..................... 31 
`CONCLUSION ............................................................................................................... 32 
`
`
` 
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`TABLE OF AUTHORITIES
`
`Cases 
`
`02 Micro Int. 7 Ltd. v. Beyond Innovation Tech. Co. Ltd., 521 F.3d 1351 (Fed. Cir. 2008)
`
`1, 14
`
`Abbott Labs. v. Sandoz, Inc., 544 F.3d 1341 (Fed. Cir. 2008)
`
`Berkheimer v. HP Inc., 881 F.3d 1360 (Fed. Cir. 2018)
`
`Certain Audio Players and Components Thereof (II),
`Inv. No. 337-TA-1330, Order No. 14 (U.S.I.T.C Feb. 15, 2023)
`
`Honeywell Int’l, Inc. v. Universal Avionics Sys. Corp., 493 F.3d 1358 (Fed. Cir. 2007)
`
`In re Packard, 751 F.3d 1307 (Fed. Cir. 2014)
`
`In re Zletz, 893 F.2d 319 (Fed. Cir. 1989)
`
`1
`
`passim
`
`31
`
`2
`
`31
`
`25
`
`Innova/Pure Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111 (Fed. Cir. 2004)
`
`2
`
`Interval Licensing LLC v. AOL, Inc., 766 F.3d 1364 (Fed. Cir. 2014)
`
`Media Rights Techs. v. Cap. One Fin., 800 F.3d 1366 (Fed. Cir. 2015)
`
`Nautilus, Inc. v. Biosig Instruments, Inc., 134 S. Ct. 2120 (2014)
`
`Noah Sys., Inc. v. Intuit, Inc., 675 F.3d 1302 (Fed. Cir. 2012)
`
`Novo Indus., L.P. v. Micro Molds Corp., 350 F.3d 1348 (Fed. Cir. 2003)
`
`Phillips v. AWH Corp., 415 F. 3d 1303 (Fed. Cir. 2005)
`
`
`
`23, 25, 26
`
`22
`
`passim
`
`23
`
`31
`
`1, 2, 16
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`INTRODUCTION
`
`
`
`Pursuant to Order No. 9 (December 23, 2023) setting the procedural schedule in this
`
`Investigation and Ground Rule 7.2, the Commission Investigative Staff (“Staff”) hereby submits
`
`its Markman Brief setting forth and explaining its proposed construction for each of the disputed
`
`claim terms in U.S. Patent No. 7,396,760 (“’760 Patent” or “Asserted Patent”). Complainant Bell
`
`Semiconductor, LLC (“Bell Semic”) and the remaining Respondents1 filed their initial Markman
`
`briefs on March 20, 2023.2
`
` GENERAL CLAIM CONSTRUCTION PRINCIPLES
`
`The purpose of claim construction is to explain disputed and material claim language in a
`
`way that will be useful to the decision maker. 02 Micro Int. 7 Ltd. v. Beyond Innovation Tech.
`
`Co., 521 F.3d 1351, 1362 (Fed. Cir. 2008); see also Abbott Labs. v. Sandoz, Inc., 544 F.3d 1341,
`
`1360 (Fed. Cir. 2008) (noting that claims are construed as an aid to the decision maker, by restating
`
`the claims in non-technical terms). Claims should be given their ordinary and customary meaning
`
`as understood by a person of ordinary skill in the art, viewing the claim terms in the context of the
`
`entire patent. Phillips v. AWH Corp., 415 F. 3d 1303, 1312-13 (Fed. Cir. 2005) (en banc). In some
`
`cases, the ordinary meaning of claim language is readily apparent and claim construction will
`
`involve “little more than the application of the widely accepted meaning of commonly understood
`
`words.” Id. at 1314. In other cases, claim terms have a specialized meaning and it is necessary to
`
`determine what a person of ordinary skill in the art would have understood the disputed claim
`
`language to mean by analyzing “the words of the claims themselves, the remainder of the
`
`
`1 The remaining Respondents are OmniVision Technologies, Inc., Skyworks Solutions Inc., and
`Arlo Technologies, Inc. (collectively “Respondents”).
`2 Complainant Bell Semic’s Opening Claim Construction Brief and Respondents’ Initial Claim
`Construction Brief are referred to herein as “COCCB” and “RICCB,” respectively.
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`specification, the prosecution history, and extrinsic evidence concerning relevant scientific
`
`principles, the meaning of technical terms, and the state of the art.” Id. (quoting Innova/Pure
`
`Water, Inc. v. Safari Water Filtration Sys., Inc., 381 F.3d 1111, 1116 (Fed. Cir. 2004)). The
`
`patentee may also act as a lexicographer. “When a patentee defines a claim term, the patentee’s
`
`definition governs, even if it is contrary to the conventional meaning of the term.” Honeywell
`
`Int’l, Inc. v. Universal Avionics Sys. Corp., 493 F.3d 1358, 1361 (Fed. Cir. 2007).
`
`Questions of claim indefiniteness may also be addressed during claim construction. A
`
`patent is invalid for indefiniteness only when “its claims, read in light of the specification
`
`delineating the patent, and the prosecution history, fail to inform, with reasonable certainty, those
`
`skilled in the art about the scope of the invention.” Nautilus, Inc. v. Biosig Instruments, Inc., 134
`
`S. Ct. 2120, 2124 (2014).
`
` BACKGROUND
`A.
`
`Overview of the ‘760 Patent
`
`The ’760 Patent is titled “Method and System for Reducing Inter-Layer Capacitance in
`
`Integrated Circuits.” (’760 Patent). It is a relatively short patent with six figures and four pages
`
`in the specification, including nineteen claims. The Abstract describes that “[t]he present invention
`
`is directed to a method and system of intelligent dummy filling placement to reduce inter-layer
`
`capacitance caused by overlaps of dummy filling area on successive layers.” (Id. at Abstract). In
`
`particular, the patent offers a solution to at least reduce overlap and thereby also reduce capacitance
`
`levels by simply re-arranging dummy fill features in “each consecutive pair of layers.” (See id. at
`
`Background of the Invention, 1:66-2:1, 2:10-13; and Summary of the Invention, 2:35-47).
`
`Certain areas of each layer of an integrated circuit (“IC”) design are used by active elements
`
`of the circuit logic, such as signal, power, and clock lines. (See ’760 Patent at 1:21-37; RICCB at
`
`Ex. 2 (Subramanian Decl.) at ¶¶ 25–27). These active elements provide both the interconnection
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`to create the logical function of the circuit and structural support for the layers above them. (Id.)
`
`The remaining unused area of a given layer may then be addressed by a circuit designer, and one
`
`may include dummy fills in those unused areas as a technique to fill in some of these voids to
`
`maintain planarity. (Id. at 43-61; Subramanian Decl. at ¶ 30). Dummy fill serves no circuitry
`
`function but provides structure (typically metal) to maintain consistent density and planarity in the
`
`unused areas of each layer. (’760 Patent at 1:27–49; Subramanian Decl. at ¶¶ 25–27). However,
`
`dummy fill can also create unwanted capacitance between layers where dummy fill overlap exists.
`
`(’760 Patent at 1:27-30, 1:62–66). This unwanted capacitance can cause timing issues in the circuit
`
`design, slowing circuit speeds and reducing chip performance. (Id. at 2:3–6).
`
`The alleged problem with prior art design methods for placing dummy fill was that dummy
`
`fill was placed on each layer without consideration for the adjacent layer’s design, thus “result[ing]
`
`in a large overlap over dummy fill areas on successive layers.” (’760 Patent at 1:66-2:1; see
`
`annotated Fig. 2 in RICCB at 5). The ’760 Patent describes methods for re-arranging the dummy
`
`fill to avoid various types of overlaps that will purportedly reduce capacitance levels in the IC.
`
`(Id. at 2:35–59, 4:17–56, 5:12–14; see Claims 1-19).
`
`Figure 3, shown below, is a flow diagram illustrating a method where “two consecutive
`
`layers are treated”3:
`
`
`3 In this brief, whenever emphasis and/or bracketed annotations appear within quoted material,
`the Staff has added these unless otherwise noted.
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`(’760 Patent, Fig. 3; see Claim 1; see also RICCB at 22-23). Figure 3 describes a method where
`
`a first step is to “[s]elect a first and a second metal layers [sic] for dummy fills process,” in step
`
`302. (Id.) Then there is a query in step 306 to see if “there [is] an overlap between the first and
`
`the second dummy fill space.” (Id.; see 3:50–54, 4:22–25). If overlap can be avoided (i.e., the
`
`outcome of step 308 is “Yes”), the specification describes that “dummy fill patterns on the first
`
`layer and the second layer may be re-arranged to minimize the overlaps in Step 310.” (Id. at
`
`4:30–32). This method continues in an iterative process for each of the two layers, where one asks
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`“Are all metal layers treated?” in step 312, until the “Finish…,” when all metal layers have been
`
`through this process, in the final step 314. (Id.)
`
`The ’760 Patent claims to solve the problem of unwanted capacitance by first comparing
`
`the dummy fill spaces on adjacent layers and determining where, if any, overlap of dummy fill
`
`spaces occurs. (Id. at Claims 1, 14). The initial arrangement of dummy fill in the unused area is
`
`then rearranged in a way that allegedly minimizes the overlap of either the dummy fill spaces
`
`(Claim 1) or the overlap of dummy fill features (Claim 14) by changing the placement of any
`
`overlapping dummy fill features to offset each other, while still meeting local pattern density
`
`requirements for fabrication. (See id. at 2:35-59). The invention claimed in the ’760 Patent thereby
`
`attempts to provide a simple method for reducing at least interlayer capacitance while maintaining
`
`manufacturing density requirements. (Id. at 1:43-61, 2:35-69).
`
`B.
`
`The ’760 File History
`
`During prosecution, the patent examiner issued a restriction requirement requiring the
`
`applicants to choose between pursuing the method claims or the system claims. (See RICCB, at
`
`Ex. 5 (2/9/07 Office Action) at 1–3). The applicants chose the method claims. (Id. at Ex. 6
`
`(4/23/07 Response) at 2).
`
`In the next office action, the examiner rejected the method claims as being anticipated by
`
`prior art U.S. Patent Publication No. 2002/0190382 (“Kouno”). (Id. at Ex. 7 (6/25/07 Office
`
`Action) at 2–3 (“Kouno et al. discloses a method of arranging dummy metal fills (6A,6B) in the
`
`formation of an IC including … arranging the second pattern of dummy fills so as not to overlap
`
`the first pattern thus eliminating the possibility of bulk capacitance.”). The basis for the examiner’s
`
`rejection is illustrated in this comparison between Figure 6 of Kouno and Figure 6 of the ’760
`
`Patent, both annotated to highlight the staggered dummy fill on different layers:
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`Kouno Figure 6 (annotated)
`
`’760 Patent Figure 6 (annotated)
`
`In response, the applicants attempted to distinguish the method claims from Kouno as follows:
`
`
`
`Kouno does not disclose determining if there is overlap between the dummy fills.
`The semiconductor of Kouno has been already constructed without overlap so there
`is no overlap to determine. Further, Kouno does not disclose rearranging dummy
`fills. The dummy fills in Kouno are arranged, but are at no point rearranged.
`Thus, Kouno cannot disclose rearranging dummy fills to minimize overlap.
`
`(Id. at Ex. 8 (8/27/07 Response) at 10–11 (emphasis added)).
`
`The examiner accepted the applicants’ argument, explaining: “The following is an
`
`examiner’s statement of reasons for allowance: Examiner agrees with applicant’s arguments with
`
`regard to the independent claims, filed on 27 August 2007.” (Id. at Ex. 9 (11/29/07 Office Action)
`
`at 2). And the Patent Office issued the ’760 Patent with claims 1-19 on July 8, 2008.
`
`C.
`
`One of Ordinary Skill in the Art
`
`The Staff submits that one of ordinary skill in the art would have a background in the field
`
`of electrical circuit design, and as related to the Asserted Patent, would have at least a Bachelor of
`
`Science degree in electrical or computer engineering or a related field and at least one year of
`
`practical experience, such as with integrated circuit design, architecture, and/or fabrication.
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`Alternatively, in lieu of practical experience, the skilled artisan would have at least a Master’s
`
`degree in any of these fields.
`
`The Staff views Complainant’s and Respondents’ proposals for the level of ordinary skill
`
`in the art as comparable with the Staff’s proposal, such that the minor differences between these
`
`proposals should not impact the claim construction process. (See COCCB at 1, citing Ex. 1 (Lloyd
`
`Linder Decl.) at ¶ 22); (RICCB at 9; Ex. 2 (Vivek Subramanian Decl.) at ¶ 22).
`
`
`
`PROPER CONSTRUCTION OF THE DISPUTED CLAIM TERMS
`A.
`
`Independent Claim 1 of the ’760 Patent
`
`Six claim terms are disputed in the ’760 Asserted Patent and asserted claims 1-6, 11-13.
`
`Independent claim 1 of the ’760 Patent is presented below, with four of the six disputed claim
`
`terms emphasized in bold and italics:
`
`’760 Patent, Claim 1:
`
`1. A method for placing dummy fill patterns in an integrated circuit fabrication
`process, comprising:
`obtaining layout information of the integrated circuit, the integrated circuit
`including a plurality of layers;
`obtaining a first dummy fill space for a first layer based on the layout
`information;
`obtaining a second dummy fill space for a second layer, the second layer being
`placed successively to the first layer;
`determining an overlap between the first dummy fill space and the second
`dummy fill space; and
`minimizing the overlap by re-arranging a plurality of first dummy fill features
`and a plurality of second dummy fill features,
`wherein the first dummy fill space includes non-signal carrying lines on the first
`layer and the second dummy fill space includes non-signal carrying lines on the
`second layer.
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`B.
`
`1st Disputed Claim Term: “dummy fill space”
`
`The parties offer the following proposed claim constructions for the “dummy fill space”
`
`term, which is recited in asserted claims 1-5 of the ’760 Patent, with only the word “unused”
`
`differing in the parties’ proposals:
`
`Term
`
`“dummy fill space”
`
`’760 Patent,
`asserted claims 1-5
`
`
`
`
`1.
`
`Staff’s Proposed
`Construction
`
`“unused area suitable
`to have dummy fill
`features inserted”
`
`Respondents’
`Proposed
`Construction
`“unused area
`suitable to have
`dummy fill features
`inserted”
`
`Complainant’s
`Proposed
`Construction
`“area suitable to
`have dummy fill
`features inserted”
`
`Staff’s construction is correct based on the intrinsic evidence.
`
`Staff and Respondents propose that “dummy fill space” be given its plain and ordinary
`
`meaning in the context of the claims and specification to mean “unused area [on a layer after the
`
`signal, power and clock segments have been routed] suitable to have dummy fill features inserted.”
`
`(See RICCB at 11-13). The Staff’s proposed construction is firmly rooted in the intrinsic evidence
`
`and is consistent with the description in the specification, including the word “unused.” Indeed,
`
`Staff’s proposed construction is almost a verbatim recitation from the following portions of the
`
`specification describing “dummy fill space”:
`
`The system may comprise a means for defining dummy fill features including small
`squares within the dummy fill space. The dummy fill spaces are suitable to have
`dummy fill features inserted.
`
`(’760 Patent at 2:26–31). And the specification further identifies that the active circuitry should
`
`be excluded from “dummy fill space”:
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`In a typical integrated chip layout, there are unused areas on a layer after the
`signal, power and clock segments have been routed. These unused areas can be
`large enough such that additional features (metals) should be added to satisfy
`minimum metal coverage requirements for manufacturing. The “dummy” fills may
`be added to the unused areas such that subsequent layers on the integrated circuit
`are substantially planar.
`
`(Id. at 1:34–42; see COCCB at 11-12 (citing the same disclosures)). Based on these two passages,
`
`the Staff proposes construing “dummy fill space” to mean “unused areas suitable to have dummy
`
`fill features inserted,” where the “unused areas” on a layer exclude where the signal, power and
`
`clock segments have been routed.
`
`2.
`
`Complainant’s proposal is overly broad.
`
`In comparison, Complainant’s proposal is overly broad because, on its face, it does not
`
`appear to exclude any area, including areas with active circuitry. Even though a designer (or
`
`software) could readily rearrange the circuitry so as to make even “used areas” eligible to be
`
`included within the boundaries of possible “dummy fill space,” the specification explicitly
`
`excludes active circuitry from “dummy fill space.” (’760 Patent at 1:34–42). Thus, because the
`
`Complainant’s proposal is overly broad, the Staff’s proposal should be adopted because it is more
`
`accurate in view of the intrinsic evidence.
`
`Moreover, Complainant only disputes that including “unused” would be too narrow and
`
`limited to a single embodiment by incorrectly arguing that “unused area” would also exclude the
`
`areas filled by the initial arrangement of dummy fill features. (See COCCB at 12 (“The areas
`
`devoid of signal lines or active circuit components that had already been ‘used’ for placement of
`
`some dummy fill could potentially receive more dummy fill and have the existing dummy fill
`
`rearranged.”). But Complainant mischaracterizes the Staff’s proposal, which does not exclude any
`
`of the discrete areas taken up by the initial arrangement of dummy fill features, as described by
`
`the following clarification: “dummy fill space” is “unused area [on a layer after the signal, power
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`and clock segments have been routed] suitable to have dummy fill features inserted.” Thus, Staff’s
`
`proposed construction can include areas filled by the initial arrangement of dummy fill features
`
`(as well as areas where any dummy fill features are subsequently moved).
`
`If not already clear, the last element of claim 1 explicitly requires dummy fill features to
`
`be included in each “dummy fill space,” where “non-signal carrying lines” include “dummy fill”:
`
`“wherein the first dummy fill space includes non-signal carrying lines on the first layer and the
`
`second dummy fill space includes non-signal carrying lines on the second layer.” (See ’760 Patent
`
`at Claim 1). This disclosure of “non-signal carrying lines,” which is another way to describe
`
`“dummy fill features,” is also evident from the specification’s statements that “the bulk
`
`capacitance introduced due to the overlap of non-signal carry lines may be reduced by changing
`
`the placement of non-signal carry lines.” (Id. at 1:24-30, 1:34–42).
`
`In sum, the Staff proposes to construe the term “dummy fill space” as “unused area suitable
`
`to have dummy fill features inserted.” The Staff and Respondents’ proposal is entirely consistent
`
`with the intrinsic record of the ’760 Patent as would have been understood by one of ordinary skill
`
`in the art at the time of the invention. Moreover, as discussed next, “dummy fill space” pertains
`
`to the available dummy fill space covering a given layer, and not just to an arbitrarily drawn box.4
`
`
`4 The Staff submits that the concepts of an IC layer, “dummy fill space” covering an IC layer, and
`the space occupied by a plurality of “dummy fill features” that are initially inserted and then
`rearranged in a “dummy fill space” are related as subsets to each other. In other words, any initial
`design of a given IC layer includes circuitry and dummy fill. The potential “dummy fill space”
`will include the areas where dummy fill features have been initially placed as well as the areas still
`capable of placing or moving dummy fill features, but it will exclude the areas already used by the
`signal, power, and clock segments.
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`C.
`
`2nd Disputed Claim Terms: “a first dummy fill space [for a first layer]”; and
`“a second dummy fill space [for a second layer]”
`
`The parties offer the following proposed claim constructions for the related terms “a
`
`[first/second] dummy fill space” for a [first/second] layer, which are in independent claim 1 of
`
`the ’760 Patent.
`
`Terms
`
`“a first dummy fill space
`[for a first layer]”; and
`
`
`
`
`“a second dummy fill
`space [for a second
`layer]”
`
`’760 Patent, asserted
`claims 1-5
`
`
`Staff’s Proposed
`Construction
`
`“an unused area
`covering a first
`layer suitable to
`have dummy fill
`features inserted”
`
`“an unused area
`covering a second
`layer suitable to
`have dummy fill
`features inserted”
`
`Respondents’
`Proposed
`Construction
`“an unused area
`covering a first
`layer suitable to
`have dummy fill
`features inserted”
`
`“an unused area
`covering a second
`layer suitable to
`have dummy fill
`features inserted”
`
`Complainant’s
`Proposed
`Construction
`plain and ordinary
`meaning – see also
`construction of
`“dummy fill space”
`above
`
`1.
`Staff’s construction correctly addresses the span of each “dummy fill
`space.”
`
`For the related terms “a [first/second] dummy fill space” for a [first/second] layer, the main
`
`
`
`dispute is the span of each of the first and second dummy fill spaces. Staff and Respondents
`
`propose “an unused area covering a [first/second] layer suitable to have dummy fill features
`
`inserted.” In addition to consistently incorporating the earlier proposed construction for “dummy
`
`fill space,” the Staff’s proposal also emphasizes the explicit requirement in the independent claim
`
`that each of the first/second dummy fill spaces be “for a [first/second] layer” of the integrated
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`circuit design, and thus, as a practical matter, “cover[s]” or extends across each layer. As is clear
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`from the intrinsic evidence, each of the first/second dummy fill spaces should be identified as a
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`broad subset of space covering its respective first/second layer after excluding the active circuitry.
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`The Complainant’s proposal, even though it states that the plain and ordinary meaning applies, is
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`to construe “dummy fill space” essentially as a small, arbitrarily drawn box. As explained below,
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`the specification does describe important characteristics for “dummy fill space,” which the Staff
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`believes informs the proper construction of the term.
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`Looking first at the claims, independent claim 1 recites, for example, the larger-scale
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`context of the preamble for “placing dummy fill patterns in an integrated circuit fabrication
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`process” and initial/first step of “obtaining layout information [for each layer] of the integrated
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`circuit, the integrated circuit including a plurality of layers.” (’760 Patent, Claim 1). Clearly,
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`these terms refer to obtaining the “layout information” of each layer of an IC, which defines the
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`layout of the active circuitry as well as the remaining, available dummy fill space across each of
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`the first and second layers. The second and third method steps at issue recite “obtaining a first
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`dummy fill space for a first layer based on the layout information [of the integrated circuit]” and
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`“obtaining a second dummy fill space for a second layer based on the layout information [of the
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`integrated circuit].” (Id.) Here, the action of “obtaining a [first/second] dummy fill space” refers
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`to getting or determining this known “dummy fill space” information from the layout information,
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`not arbitrarily selecting a random space.
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`The surrounding context of the claims refers to the structure of individual layers of the IC’s
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`design, which also supports this plain meaning for “dummy fill space.” By reciting “a first dummy
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`fill space for a first layer” and “a second dummy fill space for a second layer,” the claim indicates
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`that the method steps are performed on areas larger than just a small, arbitrarily drawn box within
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`a given layer. These references in the claims are consistent with the understanding that the method
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`steps are performed on the dummy fill spaces covering each of the first and second layers.
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`And as discussed earlier, the flow chart in Figure 3 is focused on the method steps being
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`applied to each layer of the IC design, specifically “wherein two consecutive layers are treated.”
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`(’760 Patent, Fig. 3; 3:11-13; see also Claim 1). In its brief, Complainant appears to concede that
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`the method in Figure 3 checks and compares the overlap in consecutive layers:
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`The ’760 Patent also provides a flow chart describing this operation in its Figure 3,
`where a successful determination that “the overlap [is] avoidable” conditions the
`next stage of “[r]earrang[ing] dummy fill features.” Accordingly, if an overlap is
`found to be unavoidable, the process skips the “re-arrange” stage and moves on to
`checking additional layers (where applicable).
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`(COCCB at 6).
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`The file history also supports construing this claim term to cover the available dummy fill
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`space covering each of the first and second layers. In an office action, the patent examiner rejected
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`the method claims as being anticipated by the Kouno publication. (See RICCB, at Ex. 7 (6/25/07
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`Office Action) at 2-3). In attempting to traverse the examiner’s anticipation rejection of all pending
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`claims by the Kouno reference under § 102, the applicants confirmed to the examiner that the
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`Claim 1 “recite[s] determining overlap of first and second layers of dummy fills….” as follows:
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`Applicant respectfully submits Claims 1-13 and 20-25 recite elements that have not
`been disclosed by Kouno. For example, Claims 1 and 20 generally recite
`determining overlap of first and second layers of dummy fills and rearranging the
`dummy fills to minimize overlap. The Patent office cites to Kouno for the above
`limitations (Figure 6, 6A, 6B, and related text). However, the cited sections of
`Kuono do not disclose determining overlap of first and second layers of dummy
`fills and rearranging the dummy fills to minimize overlap.
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`(RICCB, at Ex. 8 (8/27/07 Response) at 10–11). Clearly, the applicants were focused on the
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`dummy fill spaces covering each layer as they equated the fourth method step of “determining an
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`overlap between the first dummy fill space and the second dummy fill space” with the “dummy
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`fill space” term’s ordinary meaning, as provided to the examiner, of “determining overlap of first
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`and second layers of dummy fills,” which would include all possible space for placing or moving
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`dummy fill features in each of the first and second layers.
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`In the Staff’s view, the intrinsic evidence, including the prosecution history, of the ‘760
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`Patent dictates that the scope of the “dummy fill space[s]” be construed to cover each of the first
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`and second layers, as emphasized by the applicants’ own words.
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`2.
`Complainant offers no substantive construction yet argues for an
`arbitrary scope.
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`In essence, Complainant argues for a litigation-driven construction that would allow it to
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`pick and choose any arbitrary “box” or “window” or “tile” somewhere on each layer for its
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`infringement contentions. (See COCCB at 13-14; at Ex. 1 (Linder Declaration at ¶¶ 38 (“it is best
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`practice to focus, in a given layer, on the tiles of a circuit layout”) (Fig. 2 showing both “windows”
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`and “tile[s]”); 39 (“a dummy fill space within a layer, which does not need to cover the entire
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`layer”); 40 (“any given layer may include multiple dummy fill spaces that require comparison to
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`other layers”)). Because Complainant has not, and cannot, point to any intrinsic support for its
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`litigation-driven argument that each “dummy fill space” can be arbitrarily selected, its arguments
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`for its “plain and ordinary” proposal should be rejected in favor of the Staff’s proposed
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`construction. See O2 Micro, 521 F.3d at 1362 (“In this case, the ‘ordinary’ meaning of a term does
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`not resolve the parties’ dispute, and claim construction requires the court to determine what claim
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`scope is appropriate in the context of the patents-in-suit.”).
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`Although a skilled artisan would be familiar with EDA software and the tools used to
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`manage and