UNITED STATES INTERNATIONAL TRADE COMMISSION
`WASHINGTON, D.C.
`
`Before the Honorable David P. Shaw
`Administrative Law Judge
`
`In the Matter of
`
`
`
`CERTAIN STANDARD CELL LIBRARIES,
`PRODUCTS CONTAINING OR MADE USING
`THE SAME, INTEGRATED CIRCUITS MADE
`USING THE SAME, AND PRODUCTS
`CONTAINING SUCH INTEGRATED
`CIRCUITS
`
`Investigation No. 337-TA-906
`
`
`
`COMPLAINANT TELA INNOVATIONS, INC.’S
`IDENTIFICATION OF EXPERT WITNESSES
`
`Pursuant to the Procedural Schedule established in Order No. 9 and Ground Rule 4.a
`
`(Order No. 6), Complainant Tela Innovations, Inc. (“Tela”) respectfully submits this list of
`
`expert witnesses, including their curricula vitae and descriptions of their respective bodies of
`
`expertise. Depending on the specific circumstances, Tela may present these witnesses at the
`
`hearing, by deposition, by affidavit, or by witness statement. Tela reserves the right to
`
`supplement or amend this identification of expert witnesses as appropriate.
`
`A.
`
`Dr. Ezekiel Kruglick
`
`Dr. Ezekiel Kruglick is an expert in electrical engineering, including semiconductors and
`
`integrated circuit layout and design. Dr. Kruglick’s curriculum vitae is attached hereto as
`
`Exhibit A.
`
`B.
`
`Dr. Yu “Kevin” Cao
`
`Dr. Yu “Kevin” Cao is an expert in electrical engineering, including semiconductor and
`
`integrated circuit layout and design, simulation, and modeling. Dr. Cao’s curriculum vitae is
`
`attached hereto as Exhibit B.
`
`-1-
`
`

`
`
`
`C.
`
`Brian Napper
`
`Mr. Brian Napper is an expert in accounting, finance, and economics, including the
`
`valuation and management of intellectual property. Mr. Napper’s curriculum vitae is attached
`
`hereto as Exhibit C.
`
`In addition to the expert witnesses identified above, Tela reserves the right to offer
`
`opinion testimony from lay witnesses that it calls at the hearing in this Investigation as to matters
`
`within the perception of the lay witness. Tela further reserves the right to elicit testimony
`
`that may be deemed expert testimony from lay witnesses who have the requisite scientific,
`
`technical, or other specialized knowledge to provide that testimony and hereby designates those
`
`lay witnesses with regard to such testimony.
`
`-2-
`
`

`
`
`
`Date: April 4, 2013
`
`
`
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`/s/Alison McCarthy
`___________________________
`William D. Belanger
`Alison L. McCarthy
`Jaclyn M. Essinger
`Pepper Hamilton LLP
`19th Floor, High Street Tower
`125 High Street
`Boston, MA 02110-2736
`Tel: 617-204-5100
`Fax: 617-204-5150
`
`Goutam Patnaik
`David J. Shaw
`Michael H. Durbin
`Pepper Hamilton LLP
`Hamilton Square
`600 Fourteenth Street, N.W.
`Washington, DC 20005-2004
`Tel: 202-220-1247
`Fax: 202-220-1665
`
`Charles F. Koch
`Pepper Hamilton LLP
`555 Twin Dolphin Drive
`Suite 310
`Redwood City, CA 94065
`Tel: 650.620.9550
`Fax: 650.620.9594
`
`Counsel for Complainant
`Tela Innovations, Inc.
`
`-3-
`
`

`
`
`
`EXHIBIT A
`
`EXHIBIT A
`
`

`
`Dr. Ezekiel “Zeke” Kruglick
`13842 Deergrass Ct Poway, CA 92064
` zkruglick@gmail.com
`
`(858) 779 IDEA (4332)
`Experience
`•
`President of Ardent Research Inc., 2003-present
`Government and private company contracting and consulting, design, layout and fabrication of microdevices
`and computing architectures. Served 10 years as DARPA technical specialist in micro-technology office
`(MTO) with technology review and idea responsibilities. Industry reviews and technology development for
`multiple fields including integrated circuits, space propulsion, telecom, software, datacenters, materials science,
`and more. Expert on ITC investigation 337-TA-873.
`
` •
`
` OMM Inc., 1999-2003: Principal MEMS Designer
`Broad responsibilities including: Device physical conceptualization, chip design, layout, production metrology
`and process monitoring, development. Took projects from concept to manufacturing with excellent track record
`for both schedule and budget. Joined with 15 people, company reached 430 people during tenure.
`
` •
`
`
`UC Berkeley 1996 - 1999: PhD in EECS, specialty: Integrated Circuits and Systems
`(ICS)/MEMS, thesis topic: MEMS Relays
`
` •
`
` Maxim Integrated Products, 1995 - 1996: CMOS Designer
`Responsible for product planning, electronic and mechanical design, process management, chip layout, and
`testing of new inertial device product line based on integrating CMOS, MEMS, and xenon difluoride etching.
`First pass devices performed in accordance with predicted specifications.
`
` •
`
`
`
`
`Caltech Jet Propulsion Laboratory, 1994 - 1995
`Responsible for design, layout, fabrication, and testing of tunneling Golay cell array infrared detector for flight
`mission
`
`Education
`Ph.D., Electrical Engineering, University of California, Berkeley
`M.S., Electrical Engineering, University of California, Los Angeles
`B.S., Electrical Engineering, University of California, Los Angeles
`Patents, Awards, & Publications:
`35 papers published – work has been profiled in The Economist, OE Reports, EE Times -- Recipient
`of Congressional NASA Space Act Award
`Software Proficiencies
`Registered MS Project Black Belt, General computer and Microsoft proficient, Various analytic tools
`(MathCAD, Matlab); Various Design tools (ANSYS, Microcosm, L-Edit, Cadence, SPICE);
`Solidworks for 3D modeling, Python programming
`Personal
`
`Licensed Pilot – Single Engine Land
`Hobby Blacksmith, Carpenter, Glassworker
`Active Security Clearance TS / SCI / SAP
`
`
`
`
`
`
`
`SCUBA diver
`US Citizen
`
`All content copyright Ezekiel Kruglick 2006– distribution only with permission
`
`
`
`

`
`
`Doctor Ezekiel “Zeke” Kruglick received his B.S. and M.S. in electrical engineering from UCLA and
`his Ph.D. in electrical engineering from UC Berkeley. He has worked at the Jet Propulsion Laboratory,
`various universities, and several commercial companies including three start-ups that successfully
`developed new MEMS products. As a drop-in manager at his most recent start-up effort he took an
`idea from concept to product booking of over a million dollars per quarter in a single year.
`
`Dr. Kruglick and his professional activities have been featured in a number of publications, including
`The Economist, OE Reports, Scientific Computing World, and EE Times. He has numerous patents
`issued or pending, has published over 35 technical papers, and has received a number of awards in
`recognition of his work including a recent congressional NASA Space Act Award. He has written key
`or cover articles for several professional publications, including Solid State Technology, Lightwave
`Reports, and WDM Solutions. He is extensively quoted in “Fiber-Optic Systems for
`Telecommunications” and “RF MEMS: Theory, Design and Technology” and is a co-author of the
`“MEMS Handbook” second edition from CRC press.
`
`Doctor Kruglick served on the board of directors of Ntech Corp as both a private and public company;
`he was also on the board of directors of TiNi Alloy Company. He is currently president and board
`member at Ardent Research, a boutique consulting and strategic services company.
`
`
`
`All content copyright Ezekiel Kruglick 2006– distribution only with permission
`
`

`
`
`
`EXHIBIT B
`
`EXHIBIT B
`
`

`
`Yu (Kevin) Cao
`Associate Professor, Electrical Engineering
`Affiliated Professor, Computer Science and Engineering
`
`School of Electrical, Computer and Energy Engineering, Arizona State University
`P.O. Box 875706, Tempe, AZ 85287-5706
`Office: 480-965-1472; Cell: 480-567-5198; Fax: 480-965-0616
`E-mail: ycao@asu.edu; http://nimo.asu.edu/ycao
`
`
`
`
`Education
`
`1997 – 2002 University of California, Berkeley, CA, USA
`
`Ph.D. in Engineering – EECS (December 2002)
`Dissertation: Nanometer Circuit Performance Analysis: Device and Interconnect
`
`
`M.A. in Biophysics (December 1999)
`
`1991 – 1996 Peking University, Beijing, China
`
`B.S. in Physics (July 1996)
`
`Work Experience
`2013 – 2014 Visiting Associate Professor, Graduate School of Informatics, Kyoto University, Kyoto,
`Japan
` Associate Professor, School of Electrical, Computer and Energy Engineering, Arizona State
`University, Tempe, AZ
`2004 – 2009 Assistant Professor
`2003 – 2004 Post-Doctoral Researcher, University of California, Berkeley, CA
`Berkeley Wireless Research Center, Advisor: Professor Jan M. Rabaey
`1999 – 2002 Graduate Student Researcher, University of California, Berkeley, CA
`Device Group, Department of EECS, Advisor: Professor Chenming Hu
` Summer Research Intern, IBM Microelectronics Division, Hopewell Junction, NY
` Summer Research Intern, Hewlett-Packard Laboratories, Palo Alto, CA
`
`2001
`2000
`
`
`Teaching Experience
`
`EEE 333: HDL and Programmable Logic
`
`EEE 425: Digital Systems and Circuits
`
`EEE 525: VLSI Design
`
`EEE 598: Modeling and Design Solutions for Nano-CMOS Technology (Developed)
`
`Honors and Awards
`2013
`Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU
`2012
`Best Paper Award, IEEE Computer Society Annual Symposium on VLSI
`2012
`Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU
`2011
` Chunhui Award for Outstanding Oversea Chinese Scholars, China
`
`2009 –
`
`
`
`
`
`
`

`
`Y. Cao
`
`2
`
`Top 5% Teaching Award, Ira. A. Fulton Schools of Engineering, ASU
` ACM SIGDA Outstanding New Faculty Award
` Promotion and Tenure Faculty Exemplar, Arizona State University
` Distinguished Lecturer of the IEEE Circuits and Systems Society (CAS)
` Chunhui Award for Outstanding Oversea Chinese Scholars, China
` Best Paper Award, International Symposium on Low Power Electronics and Design
` IBM Faculty Award
` NSF Faculty Early Career Development (CAREER) Award
` IBM Faculty Award
` Best Paper Award, International Symposium on Quality Electronic Design
` Beatrice Winner Award, International Solid-State Circuits Conference
` Biophysics Graduate Program Fellowship, University of California, Berkeley
` Regents Fellowship, University of California, Santa Cruz
`
`2010
`2009
`2009
`2009
`2008
`2007
`2007
`2006
`2006
`2004
`2000
`1997
`1996
`
`Research Interests
`
`Predictive modeling of nanoelectronic devices
`
`Physical-level design and tools for variability and reliability
` Reconfigurable design of CMOS circuits and beyond
` Reliable integration of emerging technologies
`
`
`Teaching Interests
` Undergraduate: VLSI design and synthesis, solid-state devices, digital circuits and systems,
`analog integrated circuits, computer architecture
`VLSI design for nanoscale technology, device modeling, computer-aided design
`
`
` Graduate:
`
`Professional Service
` Chair, Simulation and Modeling Committee, IEEE Custom Integrated Circuits Conference (CICC),
`2014
` Co-chair, Circuit Aging/Simulation and Circuit Reliability Committee, IEEE International Reliability
`Physics Symposium (IRPS), 2014
` Co-organizer, Special Session on Neuron Inspired Computing using Nanotechnology, Asia and South
`Pacific Design Automation Conference (ASP-DAC), 2014
` Co-chair, Simulation and Modeling Committee, IEEE Custom Integrated Circuits Conference (CICC),
`2013
` Chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium (IRPS), 2013
` Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
`2012 – present
` Co-organizer, Tutorial on Overcoming CMOS Reliability Challenges: From Devices to Circuits and
`Systems, Design, Automation & Test in Europe (DATE), 2011
` Chair, Signal Integrity and Reliability Sub-Committee, Design Automation Conference, 2010
` Chair, ACM SIGDA Design for Manufacturability Technical Committee, 2010
` Associate Editor, Journal of Computational Electronics, Springer, 2010 – 2013
`Program Chair, 1st IEEE CASS Summer School on Physical Design of Reliable Systems, Brazil, 2010
`
`
`

`
`Y. Cao
`
`3
`
`
`
`
` Guest Editor, IEEE Design & Test of Computers, Special Issue on Compact Variability Modeling,
`2010
` Chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium (IRPS), 2010
` Vice Chair, ACM SIGDA Design for Manufacturability Technical Committee, 2009
`
`Editorial Board, ASP Journal of Low Power Electronics, 2009 – present
` Guest Editor, IEEE Design & Test of Computers, Special Issue on Design for Reliability, 2009
` Chair, VLSI Circuit and Architecture Track, IEEE Computer Society Annual Symposium on VLSI
`(ISVLSI), 2009
` Organizer, Tutorial on Circuit Reliability, Asia and South Pacific Design Automation Conference
`(ASP-DAC), 2009
` Co-chair, Circuit Reliability Committee, IEEE International Reliability Physics Symposium (IRPS),
`2009
` Co-organizer of IEEE/ACM Workshop on Compact Variability Modeling (CVM), 2008 – 2012
` Chair, Device Modeling and Simulation Subcommittee, IEEE International Conference on Computer-
`Aided Design (ICCAD), 2008
` Chair, Design Contest, ACM/IEEE International Symposium on Low Power Electronics Design
`(ISLPED), 2008 – 2009
` Member of the Compact Modeling Technical Committee, IEEE Electron Devices Society, 2007 –
`present
`Publicity Chair, IEEE Solid-State Circuits Society, Phoenix Chapter, 2006 – 2008
`Technical Program Committee member:
`-
`IEEE Custom Integrated Circuits Conference (CICC), 2012 – present
`- ACM/IEEE Design Automation Conference (DAC), 2007 – 2009
`-
`IEEE Workshop on Design for Reliability and Variability (DRV), 2009
`-
`IEEE Great Lakes Symposium on VLSI (GLSVLSI), 2006 – 2010
`- ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2005 – 2008
`-
`IEEE International Conference on Computer Design (ICCD), 2005 – 2007
`-
`IEEE International Conference on Microelectronic Test Structures (ICMTS), 2014
`-
`IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
`-
`IEEE International Electron Devices Meeting (IEDM), 2011 – 2012
`-
`IEEE International On-Line Testing Symposium (IOLTS), 2009 – 2011, 2013
`-
`IEEE International Reliability Physics Symposium (IRPS), 2009 – present
`- ACM/IEEE International Symposium on Low Power Electronics Design (ISLPED), 2005 – 2009,
`2013 – present
`-
`IEEE International Symposium on Quality Electronic Design (ISQED), 2008
`-
`IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009
`-
`International Workshop on Compact Modeling (IWCM), 2012 – present
`- ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2007 – 2011
`Session Chair, ASP-DAC 2014, CICC 2012/2013, DAC 2005/2007/2013, ICCAD 2005/2006, ICCD
`2005, IEDM 2012, IRPS 2013, ISLPED 2005/2007, ISQED 2006, SLIP 2010
`Proposal reviewer for:
`- National Science Foundation
`- Natural Sciences and Engineering Research Council (NSERC) of Canada
`- Research Grants Council (RGC) of Hong Kong
`- University of Arizona ADVANCE program
`- University of California MICRO program
` Reviewer for:
`
`
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`

`
`Y. Cao
`
`4
`
`-
`
`IEEE Computer Architecture Letters, IEEE Transactions on Automation Sciences and
`Engineering, IEEE Transactions on Computer-Aided Design, IEEE Transactions on Device and
`Materials Reliability, IEEE Transactions on Electron Devices, IEEE Journal of Solid-State
`Circuits, IEEE Transactions on VLSI Systems, IEEE Electron Device Letters, IEEE Transactions
`on Circuits and Systems, IEEE Circuits and Devices Magazine, IEEE Transactions on
`Nanotechnology
`- ACM Transactions on Design Automation of Electronic Systems, ACM Journal of Emerging
`Technologies in Computing Systems
`- AIP Journal of Applied Physics
`- ASP Journal of Low Power Electronics
`-
`IBM Journal of Research and Development
`-
`IEE Proceedings of Circuits, Devices and Systems, IET Microwaves, Antennas & Propagation,
`IET Electronics Letters
`- Elsevier Microelectronics Journal, Elsevier Microelectronics Reliability, Elsevier Solid State
`Electronics, Elsevier VLSI Integration
`- Morgan Kaufmann Publishers Inc.
`- Springer Journal of Computational Electronics, Springer Journal of Electronic Testing
`- Springer Science+Business Media, LLC
`
`
`University Service
`
`ECEE Faculty Search Committee, 2013
` Grand Challenge Scholar Program Faculty Advisory Committee, 2012 – present
`
`Solid-State Circuits Master (MSE) graduate advisor, 2005 – present
` Curriculum development of the Solid-State Circuits group at ASU, 2005 – present
`
`
`
`Consulting Experience
`
`Proplus Design Solutions Inc., San Jose, CA [Technical Advisory Board member, 2011 – present]
` Anova Solutions Inc., Santa Clara, CA
` APIC Corporation, Culver City, CA
` Rio Design Automation Inc., Santa Clara, CA
`
`Seiko EDA Technologies Inc., Japan
` Celestry Design Technologies Inc., San Jose, CA
`
`Grants and Contracts
` MaxLinear, Inc., “28nm Age Model Development,” 07/01/13 – 12/31/13 [Gift]
` Center for Embedded Systems, a National Science Foundation’s Industry/University Cooperative
`Research Center, “A Spiking Neuron-inspired Design Paradigm with Emerging Memory Devices,”
`co-PI with Sarma Vrudhula, 06/01/13 – 05/30/14
` National Science Foundation, “CSR: Small: Heterogeneous Memory Design: Exploiting Device
`Diversity for Superior System Performance,” co-PI with Chaitali Chakrabarti, 09/01/12 – 08/31/15
` Defense Advanced Research Projects Agency, “Techniques for Estimating Reliability in COTS ICs
`(TERCI),” co-PI with Michael Fritze, USC, 07/21/11 – 07/20/14
`Intel Corporation, University Research Office, seed funding to support research on reconfigurable
`analog design, 01/11 – 12/13 [Gift]
`
`Intel Corporation, University Research Office, Resilient Computing Program, 01/12 – 12/13 [Gift]
` National Science Foundation, “SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale
`Memory: From Predictive Device Modeling to Statistical Circuit Synthesis,” 08/15/10 – 07/31/13
`
`
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`

`
`Y. Cao
`
`5
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`
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`
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`
`
` National Science Foundation, “EAGER: Low-Power VLSI Applications of Neuromorphic Circuit
`Construction with Nanoelectronic Devices,” co-PI with Bertan Bakkaloglu, ASU, 09/01/09 – 08/31/10
`Focus Center Research Program (FCRP), IFC, “Scalable Technology Models for Alternative Devices
`and Interconnect,” 11/01/09 – 10/31/10
` Qualcomm, “Benchmarking Nanoscale Circuit Design with Predictive Technology Model,” 04/01/08
`– 03/31/09
` National Science Foundation, “Self-Assembled Inductors: A New Paradigm in Nanoelectronics
`Design,” co-PI with Hongbin Yu, Bertan Bakkaloglu, Hao Yan, ASU, 09/01/07 – 08/31/10
`Semiconductor Research Corporation, “Predictive Modeling and Simulation of Reliability
`Degradation in Nanoscale Circuits,” 07/01/07 – 06/31/10
` Qualcomm, “Benchmarking Nanoscale Circuit Design with Predictive Technology Model,” 04/01/07
`– 03/31/08
`Focus Center Research Program (FCRP), GSRC, “System Performance Prediction for Reliable
`Nanoscale Integration,” 09/01/06 – 8/31/09
`Focus Center Research Program (FCRP), MSD-C2S2, “Predictive Technology Modeling for End-of-
`the-Roadmap and Post-Silicon Technologies,” 09/01/06 – 8/31/09
` National Science Foundation, “CAREER: Bridging the Technology-EDA Gap through Strategic
`Tools for Robust Nanometer Design,” 08/15/06 – 07/31/11
`IBM Corporation, Faculty Award for research on nanoelectronic design [Gift], 2007.
`Semiconductor Research Corporation, “Benchmarking Nanoscale Circuit Reliability with Predictive
`Technology Models,” 09/01/05 – 12/31/06
`
`IBM Corporation, Faculty Award for research on reliable system design [Gift], 2006.
`
`Intel Corporation, funding to support research on variation modeling and analysis [Gift], 2006.
` Connection One, a National Science Foundation’s Industry/University Cooperative Research Center,
`“Ultra Low-Power Digital Logic Design for Nanometer Technology,” 07/01/06 – 09/30/06 [ASU
`internal competition]
` Microelectronics Advanced Research Corporation (MARCO), MSD-C2S2, “Predictive Technology
`Modeling for Robust Nanometer Design,” 04/16/05 – 12/31/06
`Semiconductor Research Corporation, “Robust Low Power Circuit Design with Predictive
`Technology Models,” co-PI with Lawrence Clark, ASU, 01/01-05 – 01/31/06
`
`Students
`Ph.D. Graduate Students
` Naveen Suda
` Ketul Sutaria
`
`Zihan Xu
` Rongjun Zhu
` Anupama Subramaniam (November 2012, Intel, Thesis “Efficient circuit analysis under multiple input
`switching”)
`Jyothi Velamala (November 2012, Intel, Thesis “Compact modeling and simulation for digital circuit
`aging”)
`Saurabh Sinha (November 2011, ARM, Thesis “Neuromorphic controller for low power systems:
`from devices to circuits”)
` Chi-Chao Wang (March 2011, Intel, Thesis “Predictive modeling for extremely scaled CMOS and
`post-silicon devices”)
` Yun Ye (April 2011, Proplus, Thesis “Modeling and simulation of variations in nano-CMOS design”)
`
`
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`

`
`Y. Cao
`
`6
`
` Min Chen (May 2010, Qualcomm, Thesis “Design for reliability: from silicon characterization, model
`calibration, to efficient simulation”)
` Wei Zhao (March 2009, Qualcomm Inc., Thesis “Predictive technology modeling for scaled CMOS
`design”)
` Wenping Wang (June 2008, Qualcomm, Thesis “Circuit aging in scaled CMOS design: modeling,
`simulation, and prediction”)
` Asha Balijepalli (co-advised with Prof. Trevor Thornton, December 2007, GLOBALFOUNDRIES,
`Thesis “Compact modeling and applications of a PD SOI MESFET”)
`Master Graduate Students
` Athul Ramkumar
`
`Pei An (November 2013, Supertex, Thesis “Reliable arithmetic circuit design inspired by SN P
`systems”)
` Venkatesa Sarma Ravi (February 2013, Samsung, Thesis “Statistical characterization and
`decomposition of SRAM cell variability and aging”)
` Cheng Xu (November 2012, Microchip, Thesis “Programmable analog device array (PANDA): a
`methodology for transistor-level analog emulation”)
` Rui Zheng (April 2011, Loongson, Thesis “Aging predictive models and simulation methods for
`analog and mixed-signal circuits”)
`
`Jia Ni (May 2010, Bloomberg, Thesis “Rigorous extraction of Vth variation in SRAM cell transistors”)
` Varsha Balakrishnan (November 2009, GLOBALFOUNDRIES, Thesis “Circuit aging simulation for
`digital and analog circuits”)
` Dinesh Ganesan (December 2007, Freescale, Thesis “Finite point gate model”)
` Ritu Singal (September 2007, Intel, Thesis “Compact modeling of non-rectangular gate effect”)
` Rakesh Vattikonda (July 2007, Qualcomm, Thesis “Predictive modeling of NBTI effect”)
`
`Tarun Sairam (July 2006, Oracle, Thesis “Low-power digital design with FinFET technology”)
`Visiting Scholars
` Yao Ma (09/12 – 08/13, Sichuan University, “Compact modeling of CMOS devices during swift
`heavy ion irradiation”)
`
`
`Selected Invited Talks and Presentations
`
`Samsung Technology Forum, “Designing Smarter SoCs for Reliability,” Milpitas, CA, September
`2013.
`IEEE Electron Device Society Mini-colloquium, “Hierarchical Exploration of Heterogeneous
`Memory Design,” Peking University, Beijing, China, July 2013.
` Design Automation Conference, Tutorial, “The Roadmap of Unreliability: A Digital Perspective,”
`Austin, TI, June 2013.
` MaxLinear, “The Roadmap of Device Unreliability,” San Diego, CA, April 2013.
`
`International Reliability Physics Symposium, Panelist, “Emerging Trends & Scaling in Reliability,”
`Monterey, CA, April 2013.
`IEEE SSCS Phoenix Chapter / Connection One Research Center, “Designing Smarter SoCs for
`Reliability,” Arizona State University, Tempe, AZ, March 2013.
` ARM, “Hierarchical Memory Modeling for Resilient Integration,” San Jose, CA, December 2012.
`
`International Conference on Solid-State and Integrated Circuit Technology, “Multi-level Reliability
`Simulation for IC design,” Xian, China, October 2012.
`IEEE Electron Device Society Mini-colloquium, “Circuit Reliability Modeling and Simulation for
`Complex SoCs,” Peking University, Beijing, China, October 2012.
`
`
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`Y. Cao
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`7
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`
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`
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`
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`
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`
`
` CMOS Emerging Technologies, “Design Exploration of Heterogeneous Memory Technologies,”
`Vancouver, Canada, July 2012.
` Workshop on Compact Modeling, Nanotech Conference & Expo 2012, “Hierarchical Memory
`Modeling for Reliable Integration,” Santa Clara, CA, June 2012.
`International Reliability Physics Symposium, Tutorial, “Circuit Reliability Modeling and Simulation
`for Complex SoCs,” Anaheim, CA, April 2012.
` Workshop on Compact Modeling, Nanotech Conference & Expo 2011, “A Universal Memory Model
`for Design Exploration,” Boston, MA, June 2011.
`219th Electrochemical Society Meeting, “Intrinsic Variability and Reliability in Nano-CMOS,”
`Montreal, Canada, May 2011.
`International Reliability Physics Symposium, Year in Review, “Circuit Reliability: Cross-layer
`Resilience Challenges and Solutions,” Monterey, CA, April 2011.
`IBM, Austin Distinguished Seminar Series, “Design at the End of the Silicon?” Austin, TX, April
`2011.
` Design, Automation and Test in Europe, Tutorial, “Modeling & Simulation of CMOS Circuit
`Reliability,” Grenoble, France, March 2011.
`International Electron Devices Meeting, “Intrinsic Variability in Nano-CMOS Design and Beyond,”
`San Francisco, CA, December 2010.
`(PANDA):
`Array
`Device
`ANalog
`Intel,
`“Programmable
`A Platform for Transistor-Level Analog Reconfigurability,” Santa Clara, CA, November 2010.
` Workshop on Simulation and Characterization of Statistical CMOS Variability and Reliability,
`International Conference on Simulation of Semiconductor Processes and Devices, “Statistical
`Reliability Modeling and Characterization in Scaled CMOS Design,” Bologna, Italy, September 2010.
`International Workshop on System Level Interconnect Prediction, Panelist, “New Models and
`Algorithms for Multi-core Interconnects,” Anaheim, CA, June 2010.
`TI, “Modeling and Simulation of Digital Circuit Reliability,” Dallas, TX, June 2010.
`First International Variability Characterization Workshop, “Predictive Variability Model,” Hsinchu,
`Taiwan, April 2010.
`(SRC) Technology Transfer e-Workshop, “In-Situ
`Semiconductor Research Corporation
`Characterization and Modeling of Circuit Reliability in Dynamic Operations,” March 2010.
`First IEEE CASS Summer School on Physical Design of Reliability Circuits, “Variability and
`Reliability in Advanced CMOS Design: Modeling and Resilient Design Solutions,” Porto Alegre,
`Brazil, January 2010.
` CMOS Emerging Technologies Workshop, “Compact Variability Modeling of Nanoscale CMOS
`Technology,” Vancouver, Canada, September 2009.
` Air Force Research Lab, Technology Seminar, “Reliability in Advanced CMOS Design: Modeling
`and Resilient Solutions,” Albuquerque, NM, August 2009.
` GLOBALFOUNDRIES, “Modeling and Design of Reliable Nanoelectronics,” Sunnyvale, CA, July
`2009.
`Intel, Pathfinding Forum, “Predictive Variability Modeling and Design Implications,” Santa Clara,
`CA, July 2009.
`IBM, “Compact Variability Modeling and Design Implications,” Yorktown Heights, NY, April 2009;
`Austin, TX, June 2009.
` Asia and South Pacific Design Automation Conference, Tutorial, “Circuit Reliability: Modeling,
`Simulation, and Resilient Design Solutions,” Yokohama, Japan, 2009.
`IEEE Workshop on Design for Reliability and Variability, “Modeling and Simulation Tools for
`Resilient Nanoelectronic Design,” Santa Clara, CA, October 2008.
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`Y. Cao
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`8
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`in
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`the
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`Intel, “Predictive Technology Modeling for Robust Nanoelectronic Design: CMOS and Beyond” and
`“Modeling and Diagnosis of Circuit Reliability in Scaled CMOS Design,” Hillsboro, OR, August
`2008.
`International Reliability Physics Symposium, Tutorial, “Reliability Modeling and Simulation for Sub-
`45nm Design,” Phoenix, AZ, April 2008.
` ARM, “Reliable Integration with Unreliable Nanoscale Devices: Predictive Modeling and Design
`Solutions,” Sunnyvale, CA, March 2008.
` University of Washington, Department of Electrical Engineering, Research Colloquium, “Predictive
`Technology Model for Nanoelectronic Design,” Seattle, WA, November 2007.
`International Conference on Computer-Aided Design, embedded tutorial, “MOSFET modeling for
`45nm and beyond,” November, 2007.
`Tsinghua University and Southeast University, “Predictive Technology Modeling
`Nanoelectronics Era,” China, May 2007.
`Intel, “Coping with Process Variations in Circuit Modeling and Simulation,” Santa Clara, CA,
`February, 2007.
`IBM, “Predictive Modeling of NBTI Effects for Reliable Nanoscale Design,” Austin, TX, February
`2007.
`Synopsys Engineering Seminar Series (SESS), “Predictive Technology Modeling for Robust Circuit
`Design with Nano-CMOS and Post-Silicon Technologies,” Sunnyvale, CA, December 2006.
` University of California, Los Angeles, “Bridging Nanometer to Gigascale: Predictive Technology
`Modeling for Robust IC Design,” November 2006.
`TI, “Predictive Modeling of Variability and Reliability in Nanoscale Design,” Dallas, TX, November
`2006.
` Qualcomm, “Benchmarking Nanoscale Circuit Design with Predictive Design Model,” San Diego,
`CA, October 2006.
`International Conference on Nano-Networks, “Predictive Technology Model for Nano-CMOS Design
`Exploration,” Lausanne, Switzerland, September 2006.
`Synopsys Engineering Seminar Series (SESS), “Coping with Process Uncertainties in Circuit
`Modeling and Simulation,” Sunnyvale, CA, September 2006.
`Semiconductor Research Corporation (SRC) Technology Transfer e-Workshop, “Benchmarking
`Nanoscale Circuit Reliability with Predictive Technology Models,” August 2006.
`Intel External Long-range Research Seminar (ELRS), “Predictive Technology Modeling for Reliable
`Nanoscale Integration,” San Jose, CA, August 2006.
`Tsinghua University and Peking University, “Bridging Nanometer to Gigascale: Predictive
`Technology Model for Robust Nanometer Integration,” Beijing, China, May 2006.
`LSI Logic, “Predictive Technology Model for Robust Nanoscale Integration,” Milpitas, CA, March
`2006.
`Intel, “Modeling and Simulation of Variability and Reliability Issues for Robust Nanometer Design,”
`Santa Clara, CA, March 2006.
`IBM T. J. Watson Research Center and Austin Research Laboratories, “Modeling and Simulation of
`Variability and Reliability Issues for Robust Nanometer Design,” Yorktown Heights, NY and Austin,
`TX, February 2006.
` Arizona State University, Center for Solid State Electronics Research (CSSER) Seminar, “Predictive
`Technology Model for Robust Nanoscale Integration,” Tempe, AZ, February 2006.
`Synopsys, “Benchmarking Sub-45nm Circuits Design with Predictive Technology Models,”
`Sunnyvale, CA, January 2006.
`IBM Austin Research Laboratories, “Variability Modeling and Characterization for Robust
`Nanometer Design,” Austin, TX, August 2005.
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`Y. Cao
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`9
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`Synopsys, “Bridging the Technology-EDA Gap: Variability Modeling and Characterization for
`Robust Nanometer Design,” Sunnyvale, CA, August 2005.
`Intel, “Bridging Nanometer to Gigascale: Process Variation Modeling for Reliable Design,” Santa
`Clara, CA, February 2005.
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`Professional Membership
`
`Senior Member, Institute of Electrical and Electrical Engineers (IEEE)
` Member, Association for Computing Machinery (ACM)
`
`Patent
`
`Lawrence Clark, Yu Cao, “Fast parallel test of SRAM arrays,” application submitted, 2011.
` Xia Li, Wei Zhao, Yu Cao, Shiqun Gu, Seung H. Kang, Matt Nowak, “Predictive modeling of
`interconnect modules for advanced on-chip interconnect technology,” applicatio