Chip Scale Package
`(CSP)
`
`Design, Materials, Processes, Reliability, and Applications
`
`- (cid:9)
`
`John H. Lau
`Express Packaging Systems, Inc.
`
`Shi-Wei Ricky Lee
`The Hong Kong University of Science &
`Technology
`
`I
`
`McGraw-Hill
`New York San Francisco Washington, D.C. Auckland Bogota
`Caracas Lisbon London Madrid Mexico City Milan
`Montreal New Delhi San Juan Singapore
`Sydney Tokyo Toronto
`
`

`

`Library of Congress Cataloging-in-Publication Data
`
`Lau, John H.
`Chip scale package, CSP design, materias, processes, and
`applications / John H. Lau, Shi-Wei Ricky Lee.
`cm.
`p. (cid:9)
`Includes index.
`ISBN 0-07-038304-9
`1. Integrated circuits(cid:151)Design and construction.
`2. Microelectronic packaging. I. Lee, Shi-Wei Ricky. II. Title.
`TK7874.L3167 1999
`621.3815(cid:151)dc2l
`
`98-53224
`CIP
`
`McGraw-Hill
`A Division of TheMcGnzw(cid:149)Hfflcotnpanies
`
`Copyright ' 1999 by The McGraw-Hill Companies, Inc. All rights
`reserved. Printed in the United States of America. Except as permitted
`under the United States Copyright Act of 1976, no part of this publica-
`tion may be reproduced or distributed in any form or by any means, or
`stored in a data base or retrieval system, without the prior written per-
`mission of the publisher.
`
`123456 7890 DOC/DOC 9 0432 109
`
`ISBN 0-07-038304-9
`
`The sponsoring editor for this book was Stephen S. Chapman, the editing
`supervisor was Penny Linskey, and the production supervisor was Sherri
`Souffrance. It was set in Century Schoolbook by Victoria Khavkina of
`McGraw-Hill’s Professional Book Group composition unit.
`
`6. (cid:9)
`
`Printed and bound by R. R. Donnelley & Sons Company.
`
`- (cid:9)
`
`- (cid:9)
`
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`
`(cid:9)
`(cid:9)
`

`

`4 (cid:9)
`
`Chapter One
`
`1.2.1 Assembly process
`Figure 1.2 shows a very simplified assembly process for wire-bonding
`chips and solder-bumped flip chips on organic substrates. More de-
`tailed design, materials, process, reliability, and applications for wire-
`bonding and flip-chip technologies can be found in Ref. [1-34]. It
`should be noted that there are two ways to do the screening test for
`solder-bumped flip-chip technology. One is to test before wafer bump-
`ing. In this case, the probe marks (damages) will be on the pad, which
`could affect the integrity of the under-bump metallurgy and have po-
`
`Wire Bonding Chip On Organic Solder Bumped Flip Chip On Organic
`Substrate (cid:9)
`Substrate
`
`I Wafer I (cid:9)
`
`Wafer
`
`I
`
`I 1 MHz Screen Test (cid:9)
`
`4. (cid:9)
`4. (cid:9)
`
`I Dicing (cid:9)
`
`I Die attach
`
`I (cid:9)
`
`Cure
`
`I (cid:9)
`
`I Wire Bonding
`
`I (cid:9)
`
`I Marking (cid:9)
`
`1. (cid:9)
`4. a (cid:9)
`I Encapsultion I (cid:9)
`4. (cid:9)
`4. (cid:9)
`r Cleaning I (cid:9)
`4. (cid:9)
`
`System test
`
`1MHz Screen ’lest
`
`I Wafer bumping
`
`1
`1.
`
`Dicing
`
`I
`
`Pick & place + Flux
`
`4.
`I Reflow I
`
`1 Underfill Encapsulation
`
`.1
`
`Marking
`
`_________
`I Cleaning I
`4.
`1
`4.
`
`System test
`
`I (cid:9)
`Figure 1.2 Assembly process for wire-bonding and flip-chip technologies.
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`vire-bonding
`s. More de-
`)flS for wire-
`f. [1-341. It
`rung test for
`wafer bump-
`e pad, which
`md have po-
`
`p On Organic
`
`[est
`
`_____
`Flux
`
`]
`
`ulation (cid:9)
`
`j
`
`!I1 (cid:9)
`
`Solder-Bumped Flip Chip and Wire-Bonding Chip on CSP Substrate (cid:9)
`
`5
`
`tential effects on long-term reliability. The other is to test after wafer
`bumping. In this case, the test will contaminate the probe needles and
`result in shorts. Also, solder bumps may be damaged. However, better
`yield can be obtained because there will be better electrical contact be-
`tween the probe needles and the solder bumps. For a mature wafer-
`bumping process, the bump yield is usually very high (>99 percent).
`From a cost point of view, the most important difference between
`wire bonding and solder-bumped flip chip is that the wire-bonding
`technology needs gold wire and the solder-bumped flip-chip technolo-
`gy needs wafer bumping. The second most important difference be-
`tween these two technologies is the effect on IC chip yields of the 1-
`MHz screening test and at-speed/burn-in system tests. Finally, the
`major equipment needed for these interconnect methods differs.
`
`1.2.2 (cid:9) Major equipment
`The major equipment needed by wire-bonding chips and solder-
`bumped flip chips on a CSP organic substrate is shown in Table 1.2. It
`should be noted that equipment required by both technologies is not
`shown. Also, all the equipment is assumed to be utilized 300 days (24
`hours a day) a year, and the capacity is assumed to be 12 million
`chips per year.
`It can be seen from Table 1.2 that expensive pick and place and
`fluxing machines are necessary for flip-chip technology. Even though
`the wire bonder is cheaper, however, because its throughput is much
`lower (it depends on the number of pads on a chip) than that of the
`pick and place machine (which performs gang bonding on a chip),
`more wire bonders are needed. Consequently, the cost of major equip-
`ment for flip chip ($2,700,000) is lower than that for wire bonding
`($4,790,000). Also, the manufacturing floor space for flip chip should
`be smaller.
`
`1.2.3 (cid:9) Materials/labor/operation
`As mentioned earlier, the largest cost differences between wire bond-
`ing and flip chip are those for materials and IC chip yields. The
`labor/operation costs for these two assembly processes are assumed to
`be the same.
`
`1.2.3.1 The wafer. The physically possible number of undamaged
`chips N stepped from a wafer (Fig. 1.2) may be given by
`
`[4_(1+O)V]2
`4A
`
`

`

`Solder-Bumped Flip Chip and Wire-Bonding Chip on CSP Substrate
`
`19
`
`1.3 How to Select Underfill Materials
`
`One of the major reasons why solder-bumped flip chip on low-cost or-
`ganic CSP substrates works is because of the underfihl epoxy encapsu-
`lant [1-6, 10-291. It reduces the effect of the global thermal expansion
`mismatch between the silicon chip and the organic substrate, i.e., it
`reduces the stresses and strains in the flip-chip solder bumps (since
`the chip and the substrate are tightly held by the underfihl) and redis-
`tributes over the entire chip area the stresses and strains that would
`otherwise be increasingly concentrated near the corner solder bumps
`of the chip. Other advantages of underfihl encapsulant are that it pro-
`tects the chip from moisture, ionic contaminants, radiation, and hos-
`tile operating environments such as thermal [3, 5, 181, mechanical pull
`[31, shear [3, 22, 26-281, and twist [3, 221, and shock/vibration [24].
`In this chapter, eleven different underfihl encapsulants with differ-
`ent filler size and content and different epoxies are studied. Their cur-
`ing conditions, such as time and temperature, are measured by a dif-
`ferential scanning calorimeter (DSC) unit. Their material properties,
`such as the TCE (thermal coefficient of expansion), Tg (glass transi-
`tion temperature), dynamic storage modulus, tangent delta, and mois-
`ture content, are measured using thermal mechanical analysis (TMA),
`dynamic mechanical analysis (DMA), and thermal gravimetric analy-
`sis (TGA). Their flow rate and mechanical (shear) strength in a solder-
`bumped flip chip on board are measured. Their effects on the electri-
`cal performance (voltage) of a functional flip-chip device are
`determined experimentally. For each test configuration, the sample
`size is three and the values reported herein are the average.
`
`1.3.1 Underfill materials and applications
`There are eleven different encapsulant materials under considera-
`tion, namely, Underfihls A, B, C, Dl, D2, D3 (three different lots), E, F,
`G, H, and I (Table 1.4). All of the underfihl encapsulants are premixed
`at the supplier sites, packed in plastic syringes (5 to 10 mL), and then
`frozen packed at (cid:151)40(cid:176)C to prevent curing. In shipping, these underfihl
`materials require special handling to maintain the low temperature
`continuously. Upon receiving the package, one needs to unpack the
`package, take out the syringes quickly, and store them in a freezer at
`an uninterrupted temperature of (cid:151)40(cid:176)C. Under these conditions,
`most of the underfihl encapsulants would have approximately one
`year storage life.
`The filler content and size for Underfihls A, B, C, Dl, D2, D3, E, F,
`G, H, and I are shown in Table 1.4. For all these underfills, the filler
`is silica. The resin of Underfihls A, B, C, Dl, D2, and D3 is bisphenol-
`type epoxy; that of Underfihl H is a mixture of bisphenol epoxy and a
`
`(cid:9)
`