1J5006970362B1
`
`(12) Unlted States Patent
`(10) Patent N0.:
`US 6,970,362 B1
`
`Chakravorty
`(45) Date of Patent:
`Nov. 29, 2005
`
`(54) ELECTRONIC ASSEMBLIES AND SYSTEMS
`COMPRISING INTERPOSER WITH
`EMBEDDED CAPACITORS
`
`75
`
`)
`
`(
`
`(73)
`
`-
`.
`IélAShgrSe K' Chakravorty’ san Jose’
`Inventor’
`(
`)
`.
`.
`ASSIgHCCZ Intel corporatlom sama Clam CA
`(US)
`
`5,745,335 A
`5,777,345 A
`5,786,630 A
`5,796,587 A
`5,818,699 A
`5,840,382 A
`5,870,274 A
`5,870,289 A
`5,889,652 A
`5,920,120 A
`
`
`
`4/1998 Watt ........................... 361/313
`7/1998 Loder et al.
`......
`257/777
`7/1998 Bhansali et al.
`..
`257/697
`.
`8/1998 Lauffer et al.
`361/763
`10/1998 Fukuoka ...........
`361/760
`
`11/1998 Nishide et al.
`428/209
`
`2/1999 Lucas ...............
`361/311
`
`2/1999 Tokuda et al.
`361/779
`.
`
`3/1999 Turturro ........
`361/705
`................ 257/719
`7/1999 Webb etal.
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 459 days.
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`0359513
`3/1990
`
`EP
`
`(21) Appl. No.: 09/628,705
`
`(22)
`
`Filed:
`
`Jul. 31, 2000
`
`(51)
`
`Int. Cl.7 ........................... H05K 7/02; H05K 7/06;
`H05K 7/08; H05K 7/10
`...................... 361/782; 361/764; 361/765;
`361/3063
`
`(52) US. Cl.
`
`(58) Field Of Search ................................ 361/760—764,
`361/306.1, 306.2, 306.3; 174/259—261; 257/700—704,
`257/723—724; 29/25-42
`
`(56)
`
`_
`References Clted
`
`(Continued)
`OTHER PUBLICATIONS
`
`Amey, D., et al., “Advances in MCM Ceramics”, Solid State
`Technology, 143—146, (1997).
`
`.
`(Confirmed)
`
`Primary Examiner—Kamand Cuneo
`Assistant Examiner—Tuan Dinh
`(74) Attorney, Agent, or Firm—Schwegman, Lundberg,
`Woessner & Kluth, PA.
`
`U.S. PATENT DOCUMENTS
`
`(57)
`
`ABSTRACT
`
`4,567,542 A
`4,926,241 A
`5,027,253 A
`5,060,116 A
`5,177,594 A
`5,177,670 A
`5,271,150 A
`5,281,151 A
`5,321,583 A
`5,354,955 A
`5,377,139 A
`5,469,324 A
`5,488,542 A
`5,639,989 A
`5,691,568 A
`5,714,801 A
`5,736,448 A
`
`............ 361/321
`1/1986 Shimada et al.
`5/1990 Carey ................... 357/75
`
`........... 361/321
`6/1991 Lauffer et al.
`..... 361/474
`10/1991 Grobman et al.
`
`.............. 257/678
`1/1993 Chance et al.
`1/1993 Shinohara et al.
`.......... 361/388
`12/1993 Inasaka
`1/1994 Arima etal.
`................. 439/68
`6/1994 McMahon ........... 361/770
`
`10/1994 Gregor et al.
`..
`..... 174/250
`................. 365/154
`12/1994 Lage et al.
`
`.
`.. 361/301.2
`11/1995 Henderson et al.
`1/1996 Ito ............................. 361/793
`6/1997 Higgins, III
`174/35 Ms
`
`11/1997 Chou et al. ............. 257/691
`
`2/1998 Yano et al. .......... 257/691
`.................. 438/393
`4/1998 Saia et al.
`
`To reduce switching noise, the power supply terminals of an
`integrated circuit die are coupled to the respective terminals
`of at least one capacitor embedded in an interposer that lies
`between the die and a substrate. In an embodiment, the
`interposer is a multilayer ceramic structure that couples
`power and signal conductors on the die to corresponding
`conductors on the substrate. The capacitor is formed of at
`least one high permittivity layer and in an embodiment
`comprises several high permittivity layers interleaved with
`conductive layers. Alternatively, the capacitor can comprise
`at least one embedded discrete capacitor. Also described are
`an electronic system, a data processing system, and various
`methods of manufacture.
`
`24 Claims, 8 Drawing Sheets
`
`PRWIARY SUBSTRATE
`
`Vcc
`
`53
`
`Vss
`
`IVM 1007
`
`IPR of U.S. Pat. No. 7,566,960
`
`

`

`US 6,970,362 B1
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,929,510 A
`5,939,782 A
`5,949,654 A
`5,991,161 A
`6,061,228 A
`6,072,690 A
`6,075,427 A
`6,088,915 A
`6,097,609 A
`6,097,611 A
`6,104,599 A
`6,183,669 B1
`6,218,729 B1
`6,252,761 B1
`6,407,929 B1 *
`6,446,317 B1 *
`6,452,776 B1
`6,532,143 B2 *
`2004/0238942 A1
`
`7/1999 Geller et al.
`................ 257/635
`8/1999 Malladi ............ 257/698
`
`9/1999 Fukuoka .............. 361/760
`
`..... 361/760
`11/1999 Samaras et al.
`
`........... 361/306.2
`5/2000 Palmer et al.
`.. 361/321.2
`6/2000 Farooq et al.
`..
`6/2000 Tai et al. ............. 333/219
`
`7/2000 Turturro ..
`...... 29/840
`
`8/2000 Kabadi ................ 361/760
`
`..... 361/760
`8/2000 Samaras et al.
`
`........
`.. 361/306.3
`8/2000 Ahiko et al.
`........... 252/5181
`2/2001 Kubota et al.
`4/2001 Zavrel, Jr. et al.
`.......... 257/698
`6/2001 Branchevsky ............ 361/321.2
`6/2002 Hale et al.
`.................. 361/763
`9/2002 Figueroa et al.
`29/25.42
`
`9/2002 Chakravorty ........... 361/303
`......... 361/301.4
`3/2003 Figueroa et al.
`12/2004 Chakravorty et al.
`FOREIGN PATENT DOCUMENTS
`
`EP
`JP
`JP
`JP
`WO
`WO
`WO
`WO
`
`0656658
`07—142867
`08—172274
`10—163447
`WO—97/50123
`WO—98/39784
`WO—00/21133
`WO—01/00573
`
`6/1995
`6/1995
`7/1996
`6/1998
`12/1997
`9/1998
`4/2000
`1/2001
`
`OTHER PUBLICATIONS
`
`Baniecki, J ., et al., “Dielectric Relaxation of Ba0.7 Sr0.3
`TiO3 Thin Films from 1 mHz to 20 GHz”,Appl. Phys. Letter
`72 (4) , 1998 American Institute of Physics, 198-500, (Jan.
`1998).
`Chan, Y., et al., “Fabrication and Characterization of
`Multilayer Capacitors Buried in a Low Temperature Co-
`Fired Ceramic Substrate”, Active and Passive Elec. Comp.
`vol. 20, 215-224, (1998).
`Choi, K.L., et al., “Characterization of Embedded Passives
`Using Macromodels in LTCC Technology”, IEEE Transac-
`tions on Components, Packaging, and Manufacturing
`Technology, vol. 21, 258-268, (Aug. 1998).
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`
`Inductors, Capacitors and Resonators Using LTCC Technol-
`ogy for Mobile Communication Systems”, 1 998 IEEE MTT-
`S Digest, 1285-1288, (1998).
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`Board Thickness, and Part Spacing: A Screening Doe”,
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`(Sep. 1999).
`Mistler, R.E., “Tape Casting: Past, Present, Potential”, The
`American Ceramic Society Bulletin, 82-86, (Oct. 1998).
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`MMIC Utilizing SrTiO3 Capacitors for 1.95 GHz Wide-
`Band CDMA Cellular Phones”, 1 998 IEEE MTT-S Digest,
`447-450, (1998).
`Rector, Jr., J., et al., “Integrated and Integral Passive
`Components: A Technology Roadmap”, 1997 Electronic
`Components and Technology Conference, 713-723, (1997).
`Scrantom, S., et al., “Manufacture of Embedded Integrated
`Passive Components
`into Low Temperature Co-Fired
`Ceramic Systems”,
`I 998 International Symposium on
`Microelectronics, 459-466, (1998).
`Sugai, K., et al., “Multilayer Alumina Substrates for ECU”,
`Z 998 IEEE/CPMT Berlin Int’l Electronics Manufacturing
`Technology Symposium, 109-112, (1998).
`Tok, AL, et al., “Tape Casting of Composite Ceramic
`Substrates Using Hollow Micro-Speherical Powders”,
`Processing and Fabrication of Advanced Materials VII,
`Proceedings of a Symposium organized by: The Minerals,
`Metals & Materials Society (TMS), Warrendale, PA, USA,
`451-461, (Oct. 1998).
`Ueda, T., et al., “GaAs MMIC Chip-sets for Mobile Com-
`munication Systems With On-Chip Ferroelectric Capaci-
`tors”, Integrated Ferroelectrics, vol. 7, 45-60, (1995).
`Williamson,
`III, W., et al., “High Frequency Dielectric
`Properties of PLZT Thin Films”, Integrated Ferroelectrics,
`vol. 17, 197-203, (1997).
`Yamasaki, K., et al., “Solder Column Interposer Grid
`Array—Improved CBGA Reliability”, 1-9.
`Yao, K., et al., “Improved Preparation Procedure and Proper-
`ties for a Multilayer Piezoelectric Thick-Film Actuator”,
`Sensors and ActuatorsA 71, 139-143, (1998).
`
`* cited by examiner
`
`

`

`US. Patent
`
`Nov. 29, 2005
`
`Sheet 1 0f 8
`
`US 6,970,362 B1
`
`
`
`I ELECTRONIC ASSEMBLY I
`WITH EMBEDDED
`CAPACITORS
`
`4
`
`1
`
`\
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`MEMORY
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`US. Patent
`
`Nov. 29
`
`9
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`US. Patent
`
`Nov. 29, 2005
`
`Sheet 7 0f 8
`
`US 6,970,362 B1
`
`70
`
`
`
`
`
`
`FORM WITHIN A MULTILAYER CERAMIC STRUCTURE AT LEAST ONE
`CAPACITOR HAVING FIRST AND SECOND TERMINALS, THE
`CAPACITOR COMPRISING (I) AT LEAST ONE HIGH PERMITTIVITY
`LAYER SANDWICHED BETWEEN CONDUCTIVE LAYERS, OR
`ALTERNATIVELY (2) A DISCRETE CAPACITOR
`
`
`
`
`
`
`FORM IN THE STRUCTURE FIRST AND SECOND POWER SUPPLY
`NODES
`
`
`
`
`
`
`
`FORM A FIRST PLURALITY OF LANDS ON A FIRST SURFACE OF THE
`STRUCTURE,
`INCLUDING A FIRST LAND COUPLED TO THE FIRST
`TERMINAL(S) AND TO THE FIRST POWER SUPPLY NODE, AND A
`SECOND LAND COUPLED TO THE SECOND TERMINALIS) AND TO THE
`SECOND POWER SUPPLY NODE, WHEREIN THE FIRST AND SECOND
`LANDS ARE POSITIONEO TO BE COUPLED TO FIRST AND SECOND
`POWER SUPPLY NODES OF A DIE
`
`
`
`FORM A SECOND PLURALITY OF LANDS ON A SECOND SURFACE OF
`THE STRUCTURE,
`INCLUDING A THIRD LAND COUPLED TO THE FIRST
`
`
`TERMINALIS) AND TO THE FIRST POWER SUPPLY NODE, AND A
`FOURTH LAND COUPLED TO THE SECOND TERMINALIS) AND TO THE
`SECOND POWER SUPPLY NODE, WHEREIN THE THIRD AND FOURTH
`
`
`LANDS ARE POSITIONEO TO BE COUPLED TO FIRST AND SECOND
`POWER SUPPLY NODES OF A SUBSTRATE
`
`
`703
`
`705
`
`TOT
`
`709
`
`END
`
`711
`
`[42,27
`
`

`

`US. Patent
`
`Nov. 29, 2005
`
`Sheet 8 0f 8
`
`US 6,970,362 B1
`
`80A
`
`PROVIDE A DIE HAVINC FIRST AND SECOND PONEP
`SUPPLY NODES
`
`803
`‘
`
`,
`
`PROVIDEASUBSTRAIE HAVINC IHIPD AND EODRIH
`POWER SUPPLY NODES
`
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`
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`3
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`807
`
`PROVIDE AN INTERPOSER TO COUPLE THE DIE TO THE
`SUBSTRATE, THE INTERPOSER COMPRISING:
`AT LEAST ONE CAPACITOR HAVING FIRST AND
`SECOND TERMINALS, THE CAPACITOR COMPRISING
`(I) AT LEAST ONE HIGH PERMITIVITY LAYER
`SANDWICHED BETWEEN CONDUCTIVE LAYERS, OR
`ALTERNATIVELY (2) A DISCRETE CAPACITOR,
`A FIRST PLURALITY OF LANDS ON A FIRST SURFACE
`THEREOF,
`INCLUDING A FIRST LAND COUPLED TO
`THE FIRST TERMINAL AND A SECOND LAND
`COUPLED TO THE SECOND TERMINAL,
`A SECOND PLURALITY OF LANDS ON A SECOND
`SURFACE THEREOF,
`INCLUDING A THIRD LAND
`COUPLED TO THE FIRST TERMINAL AND A FOURTH
`LAND COUPLED TO THE SECOND TERMINAL
`
`I
`,
`
`I
`I
`
`COUPLE IHE FIRST AND SECOND LANDS TO IHE FIRST
`AND SECOND POWER SUPPLY NODES, RESPECIIVELV
`
`'
`,
`
`809
`
`CODPEE THE THIRD AND FOURTH LANDS TO DIE THIRD
`AND FOURTH POWER SUPPLY NODES, RESPECTIVELY
`
`8“
`
`END
`
`813
`
`OM
`
`

`

`US 6,970,362 B1
`
`1
`ELECTRONIC ASSEMBLIES AND SYSTEMS
`COMPRISING INTERPOSER WITH
`EMBEDDED CAPACITORS
`
`RELATED APPLICATION
`
`The present application is related to the following appli-
`cation which is assigned to the same assignee as the present
`application and which was filed on even date herewith:
`Ser. No. 09/631,037, entitled “Electronic Assembly Com-
`prising Substrate with Embedded Capacitors”, now U.S. Pat.
`No. 6,611,419.
`
`TECHNICAL FIELD
`
`The application relates generally to electronics packaging.
`More particularly, the application relates to an electronic
`assembly that includes an interposer having one or more
`embedded capacitors to reduce switching noise in a high-
`speed integrated circuit, and to manufacturing methods
`related thereto.
`
`BACKGROUND INFORMATION
`
`Integrated circuits (ICs) are typically assembled into
`packages by physically and electrically coupling them to a
`substrate made of organic or ceramic material. One or more
`IC packages can be physically and electrically coupled to a
`printed circuit board (PCB) or card to form an “electronic
`assembly”. The “electronic assembly” can be part of an
`“electronic system”. An “electronic system” is broadly
`defined herein as any product comprising an “electronic
`assembly”. Examples of electronic systems include comput-
`ers (e.g., desktop, laptop, hand-held, server, etc.), wireless
`communications devices (e.g., cellular phones, cordless
`phones, pagers, etc.), computer-related peripherals (e.g.,
`printers, scanners, monitors, etc.), entertainment devices
`(e.g.,
`televisions, radios, stereos,
`tape and compact disc
`players, video cassette recorders, MP3 (Motion Picture
`Experts Group, Audio Layer 3) players, etc.), and the like.
`In the field of electronic systems there is an incessant
`competitive pressure among manufacturers to drive the
`performance of their equipment up while driving down
`production costs. This is particularly true regarding the
`packaging of ICs on substrates, where each new generation
`of packaging must provide increased performance while
`generally being smaller or more compact in size.
`An IC substrate may comprise a number of insulated
`metal layers selectively patterned to provide metal intercon-
`nect lines (referred to herein as “traces”), and one or more
`electronic components mounted on one or more surfaces of
`the substrate. The electronic component or components are
`functionally connected to other elements of an electronic
`system through a hierarchy of conductive paths that includes
`the substrate traces. The substrate traces typically carry
`signals that are transmitted between the electronic compo-
`nents, such as ICs, of the system. Some ICs have a relatively
`large number of input/output (I/O) terminals, as well as a
`large number of power and ground terminals. The large
`number of I/O, power, and ground terminals requires that the
`substrate contain a relatively large number of traces. Some
`substrates require multiple layers of traces to accommodate
`all of the system interconnections.
`Traces located within different layers are typically con-
`nected electrically by vias (also called “plated through-
`holes”) formed in the board. Avia can be made by making
`a hole through some or all layers of a substrate and then
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`plating the interior hole surface or filling the hole with an
`electrically conductive material, such as copper or tungsten.
`One of the conventional methods for mounting an IC on
`a substrate is called “controlled collapse chip connect” (C4).
`In fabricating a C4 package,
`the electrically conductive
`terminations or lands (generally referred to as “electrical
`contacts”) of an IC component are soldered directly to
`corresponding lands on the surface of the substrate using
`refiowable solder bumps or balls. The C4 process is widely
`used because of its robustness and simplicity.
`As the internal circuitry of ICs, such as processors,
`operates at higher and higher clock frequencies, and as ICs
`operate at higher and higher power levels, switching noise
`can increase to unacceptable levels.
`For the reasons stated above, and for other reasons stated
`below which will become apparent to those skilled in the art
`upon reading and understanding the present specification,
`there is a significant need in the art for a method and
`apparatus for packaging an IC on a substrate that minimizes
`problems, such as switching noise, associated with high
`clock frequencies and high power delivery.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of an electronic system incor-
`porating at least one electronic assembly with embedded
`capacitors in accordance with an embodiment of the inven-
`tion;
`FIG. 2 shows a cross-sectional representation of a mul-
`tilayer interposer in accordance with an embodiment of the
`invention;
`FIG. 3 shows a cross-sectional representation of a mul-
`tilayer interposer with embedded capacitors in which the
`vias that couple capacitive layers of like potential are
`arranged throughout the interior of the interposer in accor-
`dance with an embodiment of the invention;
`FIG. 4 shows a cross-sectional representation of a mul-
`tilayer interposer with an embedded discrete capacitor in
`accordance with an alternate embodiment of the invention;
`FIG. 5 shows a cross-sectional representation of a mul-
`tilayer interposer with two embedded discrete capacitors in
`accordance with an alternate embodiment of the invention;
`FIG. 6 shows a graphical representation of capacitance
`versus area for various dielectric materials that can be used
`
`in an interposer with an embedded capacitor in accordance
`with an embodiment of the invention;
`FIG. 7 is a flow diagram of a method of fabricating an
`interposer comprising an embedded capacitor, in accordance
`with an embodiment of the invention; and
`FIG. 8 is a flow diagram of a method of fabricating an
`electronic assembly having an interposer comprising an
`embedded capacitor, in accordance with an embodiment of
`the invention.
`
`DETAILED DESCRIPTION
`
`In the following detailed description of embodiments of
`the invention, reference is made to the accompanying draw-
`ings that form a part hereof, and in which is shown by way
`of illustration specific preferred embodiments in which the
`inventive subject matter may be practiced. These embodi-
`ments are described in sufficient detail
`to enable those
`
`skilled in the art to practice the inventive subject matter, and
`it is to be understood that other embodiments may be utilized
`and that logical, mechanical and electrical changes may be
`made without departing from the spirit and scope of the
`present
`inventive subject matter. The following detailed
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`US 6,970,362 B1
`
`3
`description is, therefore, not to be taken in a limiting sense,
`and the scope of embodiments of the inventive subject
`matter is defined only by the appended claims.
`The inventive subject matter provides a solution to power
`delivery problems that are associated with prior art packag-
`ing of integrated circuits that operate at high clock speeds
`and high power levels by embedding one or more decou-
`pling capacitors in a multilayer structure. Various embodi-
`ments are illustrated and described herein. In an embodi-
`
`the form of an
`structure takes
`the multilayer
`ment,
`“interposer” between an IC die and a substrate to which the
`die would ordinarily have been directly mounted. The
`embedded capacitors can be discrete capacitors, or they can
`be one or more layers of capacitive material.
`FIG. 1 is a block diagram of an electronic system 1
`incorporating at least one electronic assembly 4 with embed-
`ded capacitors in accordance with an embodiment of the
`invention. Electronic system 1 is merely one example of an
`electronic system in which the inventive subject matter can
`be used. In this example, electronic system 1 comprises a
`data processing system that includes a system bus 2 to
`couple the various components of the system. System bus 2
`provides communications links among the various compo-
`nents of the electronics system 1 and can be implemented as
`a single bus, as a combination of busses, or in any other
`suitable manner.
`
`Electronic assembly 4 is coupled to system bus 2. Elec-
`tronic assembly 4 can include any circuit or combination of
`circuits. In an embodiment, electronic assembly 4 includes
`a processor 6 which can be of any type. As used herein,
`“processor” means any type of computational circuit, such
`as but not limited to a microprocessor, a microcontroller, a
`complex instruction set computing (CISC) microprocessor,
`a reduced instruction set computing (RISC) microprocessor,
`a very long instruction word (VLIW) microprocessor, a
`graphics processor, a digital signal processor (DSP), or any
`other type of processor or processing circuit.
`Other types of circuits that could be included in electronic
`assembly 4 are a custom circuit, an application-specific
`integrated circuit (ASIC), or the like, such as, for example,
`one or more circuits (such as communications circuit 7) for
`use in wireless devices like cellular telephones, pagers,
`portable computers, two-way radios, and similar electronic
`systems. The IC can perform any other type of function.
`Electronic system 1 can also include an external memory
`10, which in turn can include one or more memory elements
`suitable to the particular application, such as a main memory
`12 in the form of random access memory (RAM), one or
`more hard drives 14, and/or one or more drives that handle
`removable media 16 such as floppy diskettes, compact disks
`(CDs), digital video disk (DVD), and the like.
`Electronic system 1 can also include a display device 8,
`a loudspeaker 9, and a keyboard and/or controller 20, which
`can include a mouse,
`trackball, game controller, voice-
`recognition device, or any other device that permits a system
`user to input information into and/or receive information
`from electronic system 1.
`FIG. 2 shows a cross-sectional representation of a mul-
`tilayer interposer 50 in accordance with an embodiment of
`the invention. Interposer 50 is interposed between IC die 40
`and primary substrate 60. IC die 40 can be of any type, such
`as a microprocessor or microcontroller, memory circuit,
`application specific integrated circuit (ASIC), digital signal
`processor (DSP), a radio frequency circuit, an amplifier, a
`power converter, a filter, a clocking circuit, and the like.
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`Primary substrate 60 can be of any suitable type and can be
`made of any suitable material, e.g. an organic material, a
`polyimide, silicon, glass, quartz, ceramic, and the like.
`Interposer 50 contains at least one embedded capacitor
`55, comprising, in the embodiment shown, alternating pairs
`of capacitive plates 52 and 54 with high permittivity (Dk)
`layers 53 between them. The expression “high permittivity
`layer” as used herein means a layer of high permittivity
`material such as a high permittivity ceramic ply such as
`titanate particles; a high permittivity dielectric film such as
`a titanate film that is deposited, for example, by Sol-Gel or
`metal-organic chemical vapor deposition (MOCVD) tech-
`niques; or a layer of any other type of high permittivity
`material.
`
`The Vcc and Vss electrodes of capacitor 55 of interposer
`50, represented by reference numerals 52 and 54, respec-
`tively, can be coupled by metallized power vias 48 and 49,
`respectively, to the corresponding bumps 43 and 45, respec-
`tively, at
`the central or core region of the die and to
`corresponding bumps 63 and 65, respectively, on the pri-
`mary substrate 60. If it is assumed, for the embodiment
`illustrated, that the via pitch is approximately 150 microns,
`a large number of such power vias (in excess of 2,000) can
`be accommodated, coupling capacitor 55 directly to the Vcc
`and Vss power nodes or bumps of IC die 40. This ensures a
`very low value for the loop inductance and enhances the
`current carrying capability of the overall IC packaging
`structure.
`
`It will be understood that the land/bump pitch of the top
`of interposer 50 needs to match the bump pitch of die 40, and
`that the land/bump pitch of the bottom of interposer 50 needs
`to match the pad pitch of primary substrate 60. While in the
`embodiment shown in FIG. 2 the pitch is the same on the top
`and bottom of interposer 50, the pitch on the bottom of
`interposer 50 and on the primary substrate 60 could be
`relaxed to larger dimensions. That
`is,
`in an alternative
`embodiment the interposer 50 could be used to transform the
`pitch from a relatively tight die bump pitch to a relatively
`loose substrate pad pitch.
`Signal bumps, such as signal bumps 41 and 47, are
`typically routed at the periphery of the die in an arrangement
`that is, for example, four or more rows deep (only one row
`being shown on each side of die 40 for the sake of simplic-
`ity). For peripheral signal bumps, interposer 50 may use
`through-vias (e.g. signal vias 46 and 51) which route signals
`from these signal bumps on the die to the opposite surface
`of interposer 50. Interposer 50 can eventually be coupled to
`the primary substrate 60, thus ensuring complete connectiv-
`ity of the Vcc, Vss, and signal levels between the IC die 40
`and the primary substrate 60.
`The inventive subject matter is equally applicable to
`embodiments where signal traces occur other than at the
`periphery, and to embodiments where Vcc and Vss traces are
`provided anywhere on the die. Essentially, all signal I/O
`levels from signal I/O bumps on the IC die 40 can be coupled
`through interposer 50 to its opposite surface using through-
`vias like vias 46 and 51 shown in FIG. 2. Likewise, Vcc and
`Vss levels from corresponding bumps on the IC die 40 can
`be coupled through interposer 50 to its opposite surface
`using through-vias like 48 and 49, respectively.
`Interposer 50 has a plurality of contacts or lands 44 on one
`surface that match corresponding solder balls or bumps 42,
`in terms of their pitch and placement, on a surface of IC die
`40. In addition, interposer 50 has a plurality of contacts or
`lands 56 on another surface that match corresponding solder
`balls or bumps 58 on a surface of primary substrate 60. Die
`40 and primary substrate 60 can be of any type. Although the
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`US 6,970,362 B1
`
`5
`embodiment of interposer 50 illustrated in FIG. 2 is
`described as having the same high density configuration of
`lands and vias as the IC die 40 and primary substrate 60,
`other embodiments could have a configuration of lands and
`vias of a different density. The through-vias can couple lands
`(e.g. lands 44 and 56) on opposite sides of the interposer 50
`that have the same pitch, or the through-vias can be fanned
`out in order to relaX the pitch of the lands on the lower
`surface of interposer 50.
`the lands 44 of
`When the IC package is assembled,
`interposer 50 are coupled to solder bumps 42 on IC die 40,
`and the lands 56 of interposer 50 are coupled to solder
`bumps 58 on primary substrate 60.
`At least one Vcc terminal 43 on die 40 is coupled to a via
`48 of interposer 50 that couples Vcc potential to layers 52 of
`capacitor 55 and to Vcc terminal 63 of primary substrate 60.
`Also, at least one Vss terminal 45 on die 40 is coupled to a
`via 49 of interposer 50 that couples Vss potential to layers
`54 of capacitor 55 and to Vss terminal 65 of primary
`substrate 60. In addition, at least one signal terminal 41 on
`die 40 is coupled to a through-via 46 that couples an IC
`signal level to a corresponding signal terminal 61 on primary
`substrate 60. An additional signal terminal 47 on die 40 is
`coupled to through-via 51 that couples an additional IC
`signal level to signal terminal 67 on primary substrate 60.
`One important purpose of the interposer is to provide
`relatively high capacitance relatively close to the die in order
`to reduce the effect of reactive inductive coupling when the
`IC is operating, particularly at high clock speeds.
`FIG. 3 shows a cross-sectional representation of a mul-
`tilayer interposer 310 with embedded capacitors in which
`the vias that couple capacitive layers of like potential are
`arranged throughout the interior of the interposer in accor-
`dance with an embodiment of the invention. Interposer 310
`can be coupled between IC die 300 and primary substrate
`320. Interposer 310 can be coupled to IC die 300 by suitable
`connectors such as solder balls 301 on a matrix having the
`same pitch and location as corresponding conductive leads
`on IC die 300. Solder balls 301 can be affixed to lands 302
`
`and 305 of interposer 310. Lands 302 are intended to be
`coupled to a Vcc potential, while lands 305 are intended to
`be coupled to a Vss potential. Lands 302 are coupled to
`capacitive plates 306, whereas lands 305 are coupled to
`capacitive plates 307.
`Also coupled to capacitive plates 306 are lands 312 on
`another surface of interposer 310. Certain ones of solder
`balls 311 couple lands 312 to corresponding conductive
`traces or areas of primary substrate 320. In addition, lands
`315 are coupled to capacitive plates 307 and to others of
`solder balls 311 that can be affixed to corresponding con-
`ductive traces or areas of primary substrate 320.
`In this embodiment, the various capacitive plates 306 are
`coupled to lands 302 and 312, and they are further coupled
`to each other, by conductive vias such as via 303. Likewise,
`the various capacitive plates 307 are coupled to lands 305
`and 315, and they are further coupled to each other, by
`conductive vias such as via 309. In this embodiment, vias
`that connect capacitive plates of the same potential are
`dispersed throughout any suitable part of the interior region
`of interposer ceramic substrate 310.
`The interposer 310 comprises an embedded capacitor
`stack, the plates of which can be fabricated by using multiple
`layers or plys of ceramic film having a high pemmittivity
`(Dk) (i.e. having a dielectric constant greater than that of
`silicon dioxide). The Vcc and Vss connections are coupled
`to the plate electrodes of the embedded capacitor stack by
`connecting the respective lands to the plate electrode using
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`metallized vias through the employment of conventional
`ceramic substrate technology.
`Alternatively, the capacitor could also be fabricated by
`using a single layer or multiple layers of thin films which are
`deposited by techniques such as Sol-Gel, MOCVD, sputter-
`ing, or the like.
`As described above, the Vcc and Vss bumps on the die
`can be connected to the electrodes of the capacitors by using
`metallized vias. The signal bumps (not illustrated in FIG. 3
`but typically located at the peripheral regions of die 300) are
`routed to the opposing face of interposer 310 by using
`through-vias (although not shown in FIG. 3 they can be of
`the type illustrated in FIG. 2).
`FIG. 4 shows a cross-sectional representation of a mul-
`tilayer interposer 410 with an embedded discrete capacitor
`430 in accordance with an alternate embodiment of the
`
`invention. Interposer 410 can be coupled between IC die 400
`and primary substrate 420. Interposer 410 comprises an
`embedded discrete capacitor 430 having one terminal 426
`intended to be coupled to Vcc potential and another terminal
`428 intended to be coupled to Vss potential.
`Lands 402 of interposer 410 are intended to be at Vcc
`potential and can be coupled via certain ones of solder balls
`401 to corresponding conductive areas (not shown) on IC
`die 400. Likewise,
`lands 403 are intended to be at Vss
`potential and can be coupled via other solder balls 401 to
`corresponding areas (not shown) on IC die 400.
`Lands 402 are coupled to one terminal 426 of embedded
`capacitor 430 by a route that includes vias 404, conductive
`layer 406, and via 412. Lands 402 are coupled to lands 408
`by a similar routing that includes vias 414.
`Lands 403 are coupled to another terminal 428 of embed-
`ded capacitor 430 by a route that includes vias 405, con-
`ductive layer 407, and via 413. Lands 403 are coupled to
`lands 409 by a similar routing that includes vias 415.
`Lands 408 and 409 can be coupled to corresponding
`conductive leads or areas (not shown) on a surface of
`substrate 420 via solder bumps 411.
`Various signal routing (not illustrated for the sake of
`simplicity, but comprising signal areas of IC die 400, certain
`solder balls 401, appropriate lands on interposer 410, and
`signal planes and vias within interposer 410) can also be
`provided within interposer 410, as will be understood by
`those of ordinary skill.
`Embedded capacitor 430 can be of any suitable type. In an
`embodiment, it is a ceramic chip capacitor that is fabricated
`using conventional ceramic chip capacitor
`technology.
`While a single capacitor 430 is illustrated, for the sake of
`simplicity of illustration and description, multiple capacitors
`could be used in the embodiment illustrated in FIG. 4.
`
`FIG. 5 shows a cross-sectional representation of a mul-
`tilayer interposer 510 with two embedded discrete capacitors
`530 and 540 in accordance with an alternate embodiment of
`
`the invention. Interposer 510 can be coupled between IC die
`500 and primary substrate 520.
`Embedded discrete capac