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`MORGAN T. JOHNSON
`6107 SW Fountain Grove Terrace, Beaverton, Oregon 97007 | 503-227-1338 (H) |
`503-358-5658 (Cell) | thorgne@gmail.com
`
`PROFESSIONAL EXPERIENCE
` 2002 – Present
`
`Advanced Inquiry Systems Inc. – Hillsboro, Oregon
`AISI is a venture funded, high tech startup based on Morgan Johnson patented
`technologies covering full wafer, single touch down testing and burn-in of chips.
`AISI has attracted over $30M in investments from, among others, INTEL Capital, Applied
`Materials, KLA Tencor, and Olympic Venture Partners.
`Full wafer interposer contactors called Wafer Translators have recently met key
`milestones and are moving to production with focus on NAND, NOR and DRAM full
`wafer, single touchdown test. Additionally, interposer technologies for contacting flip-chip
`wafers (CPUs, GPUs and SoCs are examples) are progressing and will be shipping by
`Q2, 2014
`AISI has about 35 issued patents. Morgan Johnson is, on all but one, a named inventor.
`Additionally, AISI has royalty free, permanent licenses to several additional patents by Mr.
`Johnson
`Over 20 new Johnson patent filings extend the technology to Wafer Level Chip Scale
`Packaging and include a break through wafer probe technology that yields true package
`part test results from unsingulated die on the wafer. AISI formed a JDA with Intel for the
`development of semiconductor test methods and equipment. Intel Capital is an investor
`in four rounds of venture capital financing.
`These full wafer interposers reside and connect between the die on the wafer and the
`Contactor connected to the wafer tester. These interposers contact up to 13,000 die on a
`wafer simultaneously. They can have up to 110,000 contacts, all touching the wafer die
`and the contactor while connected to the tester. These contactors are trademarked
`Translated WaferTM
`
`
`Morgan Johnson enjoys a faculty appointment as Adjunct Professor in the Electrical
`Engineering School at Portland State University, Portland Oregon. Mr. Johnson has been
`a guest lecturer at the Jet Propulsion Laboratory (JPL) in Pasadena, California.
`
`SOME OF MORGAN JOHNSON’S MORE RECENT AISI PATENTS:
`8,476,630 July 2013 Methods of adding pads and one or more interconnect layers to the passivated
`topside of a wafer including connections to at least a portion of the integrated circuit pads thereon
`8,461,024 June 2013 Methods and apparatus for thinning, testing and singulating a semiconductor wafer
`8,405,414 Mar 2013 Wafer testing systems and associated methods of use and manufacture
`8,362,797 Jan. 2013 Maintaining a wafer/wafer translator pair in an attached state free of a gasket
`disposed therebetween
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`MORGAN T. JOHNSON, PAGE 1 OF 9
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`8,088,634 Jan. 2013 Methods of adding pads and one or more interconnect layers to the passivated
`topside of a wafer including connections to at least a portion of the integrated circuit pads thereon
`8,076,216 Dec, 2011 Methods and apparatus for thinning, testing and singulating a semiconductor wafer
`7,960,986 June 2011 Methods and apparatus for multi-modal wafer testing
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` 2000 – 2001
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`Morgan Johnson Technology – Portland, Oregon
`Informal Partnership with SanDisk, worked with head test engineers and managers,
`developed a full wafer interposer contactor for use in wafer-level-burn-in and test for
`NAND memory wafers. This technology formed the basis for AISI.
`
` 1997 – 1999
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`Prototype Solutions (Phase II) – Beaverton, Oregon
`Developed a technology put forth in a 1994 DARPA proposal. One-hour turn laser
`personalized ceramic substrates were achieved. Laser scribing of isolated wires directly
`in thick-film gold over filled vias on a multilayer co-fired ceramic substrate was developed.
`NOTE: This work yielded US Patent 6,878,901 LASER
`MICROMACHINING AND ELECTRICAL STRUCTURES FORMED
`THEREBY – INVENTOR Morgan Johnson – April 2005
`o HEWLETT PACKARD Printer Division (at their request)
` DELIVERABLE I: Design for an interposer containing numereous
`FPGAs that could emulate a custom ASIC and an interface to a
`second board that contains all chips to make up a printer controller
`except those on the interposer – the assemply to be able to run at
`virtually full system speed to support firmware and software
`development.
` DELIVERABLE II: A three board stack:
` Top board containing all components except the ASIC
`emulation elements and with 3,200 pressure connect interface
`pads to the:
` Middle Interposer board containing four laser programmable,
`auto routable interconnect layers, 10,000 through hole vias
`and 300,000 two layer blind vias to connect the FPGAs on the
`Bottom board to each other and to the components on the Top
`board. This interposer has 3,200 pads point up to the top
`board and 3,200 pads point down to the Botom board
` Bottom board packages 8 FPGAs with 3,200 interface pads
`NOTE: The auto routing worked perfectly and the laser programmed both
`sides of the middle interposer with great success and perfect yield on the
`second try.
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`XILINX – Programmable Device Division:
`NOTE: Working with Bob Conn, a senior technical staff member, Johnson
`developed a series of designs for high die count; bare die interposer packages over
`a period of two years. Johnson made numerous trips to Xilinx headquarters from
`Portland, Oregon
`Bob wanted to bring die close enough together to obviate the need for controlled
`impedance signal paths. This required the longest signal to be below ¼ wave
`length or about 3.7 inches. Die to die signal capacitance had to be below 2 pico
`farads.
`These goals were achieved in the Phase III design. The Phase III design fit into a
`4.1 inch cube but could still export 85 watts per die. Die to die distance was at a
`three dimensional minimum.
`The fabrication of the Cube required only standard ceramic methods and design
`rules
`Thermal management was via embedded heat pipes - somewhat exotic then but in
`every notebook PC today.
`Bob Conn wanted a compute cube that could operate at Super Computer
`Benchmark performance but cost only a few thousand dollars. High I/O band width,
`a feature of all super computers, was addressed by the design and appeared to be
`adequate to sustain high benchmark performance.
` Additionally we discussed the fact that the cube could act as a 2,048 pin, non-
`blocking cross bar switch for voice and data switching centers where it would
`replace several 72 inch high fully populated racks and use 1/1000 the power and
`operate at 20 times the data rate.
` DELIVERABLE Phase 0: A series of design speculations for consideration
` DELIVERABLE Phase I: An 8 FPGA chip interposer with the ability to stack
`with at least three additional 8 FPGA chip interposers to form a 24 FPGA die
`package. The stack provided a thermal path per-die that could remove up to
`60 watts. Average signal path length was 6.8 inches
` DELIVERABLE Phase II: An 8 FPGA chip interposer with the ability to
`stack with at least five additional 8 FPGA chip interposers to form a 48
`FPGA die package. The stack provided a thermal path per-die that could
`remove up to 65 watts. Average signal path length was 5.2 inches
` DELIVERABLE Phase III: A 12 FPGA chip interposer with the ability to
`stack with at least even additional 12 FPGA chip interposers to form a 96
`FPGA die package. The stack provided a thermal path per-die that could
`remove up to 85 watts. Worst case signal path length was 3.2 inches –
`Phase III hardware fits into a 4 inch cube
`o DARPA Contract – Prototype Solutions competed for and won a large DARPA
`contract aimed at producing quick turn, multi die interposers that could be stacked
`and interconnected to form a variety of electronics assemblies. The contract was
`for $1.5M (back when that was real money)
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`o THE NAVAL SURFACE WEAPONS LAB provided project oversight, benchmark
`result approval, progress reporting and arbitration of contract and technical issues.
`o Certification of 100% completion of all contract goals and deliverables was given
`by the NSWL to Prototype Solutions
` 1. DARPA DELIVERABLE & Innovation: Laser programmed, removable
`multi-layer thin-film wiring - Must connect a minimum of 2,048 pins with
`random net lists (accomplished). Routing must be 100% with any net list
`(accomplished). It must take less than one hour, be completely automatic to
`route and laser program any net list (final, typical time was 20 min.).
`NOTE: the above technologies yielded US Patent 5,937,515 entitled
`CONFIGURABLE CIRCUIT FABRICATION METHOD – Inventor
`Morgan Johnson - August 1999
` 2. DARPA DELIVERABLE & Innovation: Inexpensive 100% open and short
`tester - Must be accomplished in one hour. Tester did 100% test & reporting
`in 2 minutes for substrates up to 2,048 pins. Tester cost $3,200. The tester
`was the first known fully automatic opens and shorts tester that did not use
`capacitive “golden standard” routs to infer opens or shorts but instead sent
`signals to and from an array of FPGAs that were connected to the wiring
`plate being tested. In a 2,048 pin laser programmed wiring plate 1 line
`would broadcast and 2,047 pins would listen. The entire netlist of the plate
`could be derived and compare with the desired net list with error reporting
`and short location and open location coordinates being delivered.
` 3. DARPA DELIVERABLE & Innovation: Two layer autorouters – The
`autorouter ran on an ordinary PC and was capable of routing 1,024 nets with
`100% completion 100% of the time. The code routed all nets in less than 1
`second. It remains the fastest autorouters of record and never required a
`second pass with altered rules or eased constraints
` 4. DARPA DELIVERABLE & Innovation: Laser trigger map capable of
`extracting laser firing points from the completed autorouters result and
`feeding the laser firing coordinates to the laser system. This was completely
`integrated with the laser positioning system which brought each laser trigger
`point into place when the laser was fired.
` 5. DARPA DELIVERABLE & Innovation: Laser system for under $100,000
`- (actual cost $92,000). System routinely programmed copper and gold thin-
`film metallization on break-link
`interposer wiring plates with organic
`dielectrics. These 68mm square substrates had two or three metal layers
`with BCB or polyimide dielectrics.
` 6. DARPA DELIVERABLE & Innovation: 8 Ceramic plates and a wiring
`plate pressure connected – Stack contained over 80,000 pressures
`connected lapped gold pads. DARPA contract required the stack to be
`assembled and disassembled 200 times without degradation of function or
`signals. Proof cycles took one entire 18 hour day and passed 100 continuity
`tests after each disassembly and reassembly cycle.
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` 7. DARPA DELIVERABLE & Innovation: 3D-i, a patented, solder ball
`based stacking board-to-board connectors - Co-invented, patented and
`developed with Dave Ekstrom, a unique low cost board to board connector
`that enables interposer board stacking with high connection numbers
`between several interposer boards. Test structure design used over 34,000
`solder solid core solder balls, which were reflowed in one operation. 3D-I
`patent has issued. The patent includes invention and methods of producing
`multi chip interposers that are themselves interconnected to package large
`numbers of die in a single package assembly
`NOTE: The above technologies and experiments yielded US Patent
`6,443,990 entitled MULTIPLE BOARD PACKAG EMPLOYING
`SOLDER BALLS AND FABRICATION METHOD AND APPRATUS–
`Inventor Morgan Johnson – March 2000
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`o SYNOPSYS – Logic Automation Division:
` 1. DELIVERABLE & Innovation: Laser programmed, removable interposer
`and associated chip package to allow quick turn installation of chips into
`their in-circuit co-simulation system
` 2. DELIVERABLE & Innovation: Hardware Simulation chip emulation
`module and add-in board for add-in to PCs and work stations and ad-in
`board for previous hardware simulation boxes
` 3. DELIVERABLE & Innovation: High bandwidth flat cable system for
`connection of the FPGA Modules to the standard Hardware Modeler
`standard product, The cable system had a laser programmable Paddle
`board with a snap-in laser programmable interposer to re-identify the chips
`for interface to the test and simulation instruments
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` 1994 – 1996
`
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`Prototype Solutions (Phase I) – Beaverton, Oregon
`Co-founded and served as Chief Technology Officer to develop and bring to market laser
`programmed, removable wiring to market as chip prototyping.
`o Contract with DRC (Design Research Corporation) for a U.S. Navy Project
`requiring the following deliverables:
` DRC DELIVERABLE 1: Design and build a moderate cost, near IR laser
`system to customize multi-die packaging including Multi Chip Module (MCM)
`stacking
`interposer wiring,
` passives specific
`interposers containing
`capacitors, resistors, inductors and certain laser adjustable versions of each,
`and pure wiring interposers called “wiring plates”. Optionally, certain on-chip
`metal, multi-layer interconnect could be customized System laser spot
`delivery accuracy of +/- 1/10th micron “on-the-fly” was achieved and 3rd party
`verified. The laser system had a green wave length kit installed as well.
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` DRC DELIVERABLE 2: Ceramic, modular, interchangeable avionics
`function-specific
`interposer
`stacking
`components. Function-specific
`interposers included: A. Multiple signal processing chips and capacitors, B.
`Multiple FPGA die with FIFO memory and capacitors, C. Vertical spacer
`interposers to create stacking clearance and provide vertical signal paths –
`no passive or active devices, D. Generalized pad arrays for mounting
`unanticipated chips – two versions with BGA & flip-chip on one and wire
`bondable pads on a second. E. Pin Grid Array (PGA) base interposer, F.
`Ball Grid Away (BGA) base inter poser and G. Laser programmable
`Universal Wiring Plate. Modules contain two banks of 1,024 contacts
`(2,048) facing up and an equal number facing down for a total of 4,096
`accessible pads per module. These can be pass troughs or act
`independently. A stack, with C. vertical spacer probes can get quickly to
`over 88,000 pads per stack.
` DRC DELIVERABLE 2: Organic, modular, interchangeable avionics
`function-specific interposer stacking components as above with the addition
`of single piece vertical spacer interposers not practical or even possible with
`ceramic technology and flex cable attached debug inter poser for connection
`to external logic analyzer or oscilloscope.. Total pad count per stack is
`somewhat less
` DRC DELIVERABLE 3. Anisotropic, sheet stock stacking system
`incorporating alignment, pressure plate and module alignment structures.
`Several anisotropic sheet stocks were tried with mixed results but two
`materials from Shinitsu Japan were effective. Shinitsu inform us we had
`made the largest number of connections, by far than any application they
`were aware of.
` DRC DELIVERABLE 4. Spring probe stacking system including two piece
`spring probe capture blocks of 1024 pins each with up to 12 blocks used per
`assembly connecting aligning 10,240 spring probes to 20,480 pads We
`imported 1 mm pitch double ended spring probes and Everett Charles we
`were the first application to use them in such numbers.
`Innovation: Stacking, pressure connected, ceramic and organic substrates
`- with memory, FPGA and DSP packaged and bare die. This stack was
`topped with a laser programmed wiring plate to interconnect all die with one-
`day turn, no tooling, no soldering and no substrate modification. (All goals
`were met with exception of DSP die which could not be obtained).
`Note: The DRC Navy laser system was donated to Oregon Health Science
`University and remains in service in cell science studies
` 1989 – 1993
`Morgan Johnson Technology – Portland, Oregon
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`
`o Formalized Partnership: Mentor Graphics – formed with MJTech to develop
`removable laser programmed wiring for use in conjunction with FPGAs to build low
`cost, quick-turn chip emulators.
`o Formalized Partnership: TriQuint Semiconductor
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`
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` Project One formed with MJTech by the CEO of TriQuint, Al Patz to develop
`one-day turn laser programmed custom GaAs ASIC chips. TriQuint supplied
`desk and lab space on their site, phone service, cad programs and a
`workstation with clerical service and GaAs chip fabrication.. I designed and
`taped out two laser programmed GaAs semi-custom logic array devices. Both
`were fabricated successfully.
` Project Two Under the same agreement as above I designed several broad
`based comprehensive laser programming test structures for both near IR (1064
`nm) and green laser wave length (532 nm). These test patterns were
`fabricated in BCB dielectric with gold conductors and gold filled via structures.
`The structures were successfully fabricated.
` Project Three Under an additional agreement I undertook the design of a
`series of both mask programmed and laser programmed multi-chip interposers
`that act as inter die, intra die and system level interface interconnect and multi
`die packages. These structures were laid out in four fabrication design rule
`sets and fabrication technologies.
`1) Semiconductor thin film
`2) Flex circuit two layer fineline including reel to reel TAB
`3) Ceramic thin film
`4) Ceramic thick film with DuPont FODEL filled via technology
`
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` 1988 – 1989
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`Morgan Johnson Technology – Palo Alto, California
`o Continued a version of single mask programmed arrays. In one project for Adaptec
`networking chip set development turned a gate array design 8 times in 8 days prior
`to a critical industry conference and show proving how fast development and in-
`system debug could be accomplished.
`Innovation: laser programmed removable wiring interposers - for quick-turn MCMs and
`PCBs.
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` 1983 – 1987
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`LaserPath Corporation – Sunnyvale, California
`Founder and Chief Technology Officer. A venture funded high tech startup based on my
`inventions and patents. Investors included Eugene Kliener of Kliener, Perkins, Caulfield,
`Byre, General Electric Venture Capital, Crosspoint Ventures, and James D. Wolfenson.
`Laser Programmed, “Same Day” and five business day deliveries of custom chips when
`universal current practice was 12 weeks committed and about 16 to 24 weeks actual.
`o JDA - FORMAL PARTNERSHIP: General Electric Corporation adopted the
`Laserpath Quick Turn chip process as their corporate standard for internal
`development of electronics world wide and issued a press release to that effect.
`o FORMAL PARTNERSHIP: General Electric Semiconductor contracted as our
`foundry and manufactured our wafers that were the Gate Arrays we laser
`customized.
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`o
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`o
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`Innovation: Laser programmable semicustom gate arrays – done at the wafer
`level, with same functionality as masked programmed chips, same gate and logic
`structure, same I/O cell options, same chip package options. This was the first
`commercial application of laser based random logic creation. Formed Partnership
`with General Electric – GE agreed to act as foundry for LaserPath wafers in return
`for rights to use the technology company-wide for any project needing custom chip.
`Innovation: Single Mask Programming of Custom Chips – Metal 1, Via, Metal 2
`and Pad Mask were replaced in customization with a single “Break-Mask”. Allowed
`an entire wafer to be customized with one mask. Photo masks were being
`delivered in three weeks when the project was undertaken – we were able to
`reduce photo mask delivery to 8 hours without a time premium.
`o Three Patents:
`issued (one Canadian) covering
`laser and single mask
`programmed chips, MCMs and PCBs.
`o LaserPath had twice the design wins in its first year as any previous custom chip
`supplier. 200 custom chip designs were each delivered in 5 business days – only
`one was late (1/2 of one percent) versus typical industry practice of 25 to 30% late.
`Customers included Intel, IBM, Compaq, Hughes, Honeywell, and Rockwell, 11
`groups inside AT&T, Bell Labs, General Electric, Adaptec, Xerox and RCA.
`
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` 1980 – 1982
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`Hewlett Packard – Corvallis, Oregon
`Joint Project, HP-41C Handhelds. HP’s 41C product line could not be easily used “in-
`the-field” by surveyors, contractors, field researchers and other professionals requiring
`printing and weather protection.
`o
`Innovation: Conversion Kit and Case – Converted separate parts into unified,
`robust portable system with printer and storage for accessories and supplies.
`Shown in HP’s booth at the Consumer Electronics Show in Las Vegas. Officially
`endorsed by HP Corvallis for use with any elements of the 41C product line. Sold
`by HP’s largest distributor, Government Marketing Services from 1980 – 1984.
`Manufactured and assembled by MJDesign.
`
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` 1980 – 1981
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`Cray Computer – Boulder Colorado
`Funded research to develop Laser Programmed MCMs for Cray II Scientific Super
`Computer System.
`o
`Innovation: Laser programmed PCBs – that could be customized on-site, as
`needed using existing laser trim systems – Cray anticipated 1,400 designs per
`machine on common unprogrammed format.
`Innovation: Laser Programmable MCM structures - 2 mil lines/spaces, plated 2
`mil post vias on Al heat sink carrier, wire bonded bare die ECL, one Gig clock –
`developed jointly with PakTel, San Diego, CA.
`Innovation: Laser Programmed ECL On-Chip Wiring – initial development of laser
`link blowing patterns to program ECL logic, route signals and deliver power and
`ground. First look at on-chip metal link blowing with ESI Model 80 Laser Memory
`Repair System.
`
`o
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`o
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` 1977 – 1979
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`Morgan Johnson Design – Denver, Colorado
`High Tech Consulting.
`o Designed science education products with focus on energy use issues.
`o
`Innovation: Invented laser programmed interconnect – June, 1978 – applications
`at PCB, hybrid, MCM, single chip package and on-chip metallization levels.
`Innovation: 3D-laser programmable circuit structures – with 2D-laser access.
`Designs had the capability to route signal, ground and voltage creating virtual coax
`wiring.
`
`o
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`PATENTS
`I have about 40 issued patents, about 20 patents pending, some foreign patents issued
`and pending and over 60 patents in draft as of March 2013.
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`EDUCATION
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`B.S. Graphics, University of Oregon, Eugene, OR, 1960-63 & 65.
`Industrial Design, Art Center College of Design, Pasadena, CA, 1964.
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`MORGAN T. JOHNSON, PAGE 9 OF 9
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