`Trials@uspto.gov
`Tel: 571-272-7822
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`Paper 14
`Entered: February 12, 2013
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`v.
`
`XILINX, INC.
`Patent Owner
`_______________
`
`Case IPR2012-00020
`Patent 8,058,897
`_______________
`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and
`JUSTIN T. ARBES, Administrative Patent Judges.
`
`MEDLEY, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`Intellectual Ventures Management, LLC (IVM) filed a petition to institute an
`
`inter partes review of U.S. Patent 8,058,897 (the “’897 patent”) on the basis that
`
`claims 1-9 and 12-14 are unpatentable. 35 U.S.C. § 311 et seq. (Paper 5). Patent
`
`Owner Xilinx, Inc. filed a preliminary response to the petition. (Paper 10). For the
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`

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`Case IPR2012-00020
`Patent 8,058,897
`
`reasons that follow, the Board, acting on behalf of the Director, has determined to
`
`institute an inter partes review under the terms set forth herein.
`
`BACKGROUND
`
`IVM challenges claims 1-9 and 12-14 under 35 U.S.C. § 103(a). (Paper 5).
`
`The Petition is GRANTED as to claims 1-9 and 12-14 on the grounds explained
`
`herein.
`
`The ’897 Patent (Ex. 1001)
`
`The ’897 patent, entitled “Configuration of a Multi-Die Integrated Circuit,”
`
`issued on November 15, 2011 based on Application 12/825,286, filed
`
`June 28, 2010.
`
`The ’897 patent generally relates to the configuration of an integrated circuit
`
`(IC) that includes multiple dies, such as a master die and a slave die. The ’897
`
`patent describes that a master die of an integrated circuit (IC) receives
`
`configuration data for both the master and slave dies. The master and slave
`
`segment of the configuration data can be determined and the slave segment of the
`
`configuration data can be distributed to the slave die of the IC. (Ex. 1001, Col.
`
`2:5-15). The ’897 patent also describes sending configuration data from the master
`
`die of a first IC to a second IC. (Ex. 1001, Col. 7:45-60).
`
`Exemplary Claims
`
`Of the claims challenged, claims 1 and 8 are the only independent claims.
`
`Claims 2-7 depend directly from claim 1 and claims 9 and 12-14 depend directly
`
`from claim 8. Claims 1 and 8 are reproduced here:
`
`1.
`
`A method of configuring an integrated circuit (IC), the method
`comprising:
`
`
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`2
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`Case IPR2012-00020
`Patent 8,058,897
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`
`
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`receiving configuration data within a master die of a first IC,
`wherein the first IC comprises the master die and a slave die;
`
`
`determining a master segment and a slave segment of the
`configuration data, wherein the master segment specifies a master die
`circuit design to be implemented within the master die and the slave
`segment specifies a slave die circuit design to be implemented within
`the slave die;
`
`
`distributing the slave segment of the configuration data to the slave
`die of the first IC,
`
`
`determining, within the master die, whether configuration data
`comprises a segment of configuration data for a second IC; and
`
`
`responsive to determining that the configuration data comprises a
`segment of configuration data for the second IC, sending the segment
`of the configuration data to the second IC.
`
`An integrated circuit (IC) comprising:
`
`8.
`
`
`an interposer comprising a configuration bus;
`
` a
`
` a
`
` first die on a surface of the interposer;
`
` second die on the surface of the interposer,
`
`
`wherein the first die and the second die are coupled by the
`configuration bus,
`
`wherein the first die is configured, responsive to receiving
`configuration data, to determine a first segment and a second segment
`of the configuration data and distribute the second segment of the
`
`3
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`Case IPR2012-00020
`Patent 8,058,897
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`configuration data to the second die through the configuration bus,
`
`wherein the first die comprises a configuration data output coupled
`to an output of the IC, and responsive to determining that the
`configuration data comprises a segment of configuration data for the
`additional IC, the first die is configured to send the segment of
`configuration data for the additional IC through the first die
`configuration data output.
`
`
`
`IVM relies on the following prior art:
`
`The Prior Art
`
`U.S. Patent 7,397,272 , Jul. 8, 2008 (“Wennekamp”) (Ex.
`1009);
`
`U.S. Patent 7,827,336, Nov. 2, 2010 (“Miller”) (Ex. 1010);
`
`U.S. Patent 7,671,624, Mar. 2, 2010 (“Walstrum”) (Ex. 1011);
`
`U.S. Patent 7,702,893, Apr. 20, 2010 (“Rally”) (Ex. 1012); and
`
`U.S. Patent 6,730,540, May 4, 2004 (“Siniaguine”) (Ex. 1013).
`
`
`
`The Asserted Grounds
`
`
`
`IVM challenges the patentability of ’897 patent claims 1-9 and 12-14 on the
`
`following grounds:
`
`1)
`
`Claims 1-7 are unpatentable under 35 U.S.C. § 103(a) as obvious over
`
`Wennekamp;
`
`2)
`
`Claims 1 and 8 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over Wennekamp in view of Miller;
`
`3)
`
`Claims 1 and 8 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over Wennekamp in view of Walstrum;
`
`4
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`Case IPR2012-00020
`Patent 8,058,897
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`4)
`
`Claims 12-14 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over Wennekamp in view of either Miller or Walstrum;
`
`5)
`
`Claims 1-3 and 5-7 are unpatentable under 35 U.S.C. § 103(a) as
`
`obvious over Rally;
`
`6)
`
`Claims 1 and 8 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over Rally in view of Miller;
`
`7)
`
`Claims 1 and 8 are unpatentable under 35 U.S.C. § 103(a) as obvious
`
`over Rally in view of Walstrum;
`
`8)
`
`Claims 13 and 14 are unpatentable under 35 U.S.C. § 103(a) as
`
`obvious over Rally in view of either Miller or Walstrum; and
`
`9)
`
`Claim 9 is unpatentable under 35 U.S.C. § 103(a) as obvious over
`
`Wennekamp or Rally in view of either Miller or Walstrum further in
`
`view of Siniaguine.
`
`ANALYSIS
`
`Claim Interpretation
`
`Consistent with the statute and the legislative history of the America Invents
`
`Act (AIA), the Board interprets claims using “the broadest reasonable construction
`
`in light of the specification of the patent in which it appears. 37 C.F.R. § 100(b);
`
`see also Office Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48766 (Aug. 14,
`
`2012). There is a “heavy presumption” that a claim term carries its ordinary and
`
`customary meaning. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366
`
`(Fed. Cir. 2002). However, claims “must be read in view of the specification. . . .
`
`[T]he specification is always highly relevant to the claim construction analysis.
`
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`Patent 8,058,897
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`Usually, it is dispositive; it is the single best guide to the meaning of a disputed
`
`term.” See Phillips v. AWH Corp., 415 F.3d, 1303, 1317 (Fed. Circ. 2005) (en
`
`banc).
`
`The follow claim construction applies.
`
`“First IC comprises the master die and a slave die” (claim 1) or
`
`“[a]n integrated circuit (IC) comprising … a first die on a surface of the
`
`interposer” and “a second die on the surface of the interposer” (claim 8).
`
`Although IVM does not propose an explicit definition for the above term per
`
`the “claim interpretation” section of its Petition (Paper 5 at 1), we understand IVM
`
`and Xilinx to agree that both claim 1 and claim 8, with the recitation of an IC that
`
`includes more than one die, means a “multi-die IC.” (See, e.g., Paper 5 at 6; Ex.
`
`1002; Paper 10 at 4). The agreed upon meaning is consistent with the claim
`
`language itself in light of the ’897 specification. For example, claim 1 recites an
`
`IC comprising a master die and a slave die; claim 8 recites an IC comprising a first
`
`die on the surface of an interposer and a second die on the surface of an interposer.
`
` Thus, since the IC includes more than one die, there are multi-die per IC, e.g., a
`
`multi-die IC. The ’897 specification itself describes the invention in the context of
`
`a multi-die IC and is consistent with the agreed upon interpretation. (Ex. 1001
`
`title, Col. 3:23-25 “[a]n IC that is formed of two or more dies can be referred to as
`
`a ‘multi-die IC.’”).
`
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`Neither party proposes a definition for the term “die.” The ’897 patent does
`
`not define the term “die.” Accordingly, we find that a die is “a single piece of
`
`silicon that contains one or more circuits and is or will be packaged as a unit.”1
`
`Contrary to the assertions made by IVM and by their declarant
`
`Mr. Johnson (see, e.g., Ex. 1002, ¶ 25), we do not agree that an integrated circuit
`
`(IC) is necessarily a die. An integrated circuit is a broader concept and does not
`
`necessarily include the attributes of a die as that term is defined.
`
`Accordingly, claim 1 and claim 8 require a multi-die IC, where a die is a
`
`single piece of silicon that contains one or more circuits packaged as a unit.
`
`All other terms in claims 1-9 and 12-14 are given their ordinary and
`
`customary meaning.
`
`Ground 1 - Claims 1-7 (obviousness over Wennekamp (Ex. 1009))
`
`The standard for instituting an inter partes review is set forth in 35 U.S.C.
`
`§ 314(a):
`
`THRESHOLD – The Director may not authorize an inter partes
`review to be instituted unless the Director determines that the
`information presented in the petition filed under section 311 and any
`response filed under section 313 shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of
`the claims challenged in the petition.
`Wennekamp describes a system for configuring a plurality of programmable
`
`devices that may include an external memory, a master programmable device, and
`
`
`1 The Authoritative Dictionary of IEEE Standards Terms, Seventh Edition (2000).
`Ex. 3002. A copy of the dictionary term has been uploaded into the PRPS system.
`
`
`
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`Case IPR2012-00020
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`at least one slave programmable device. (Abstract).
`
`Although Wennekamp does not describe the programmable devices in the
`
`context of dies on an integrated circuit, e.g., a “multi-die IC,” Wennekamp
`
`describes that the invention is applicable to a variety of systems having
`
`programmable or configurable devices, such as programmable logic devices or
`
`integrated circuits having some programmable resources. (Col. 3:15-18). Like the
`
`’897 patent, Wennekamp recognizes the field programmable gate array (FPGA)
`
`device as a type of programmable logic device. (Col. 1:15-18 and Ex. 1001, Col.
`
`1:15-18).
`
`Wennekamp describes that a master programmable device, for example 320
`
`of Figure 3, can receive configuration data from external memory 310. (Col. 5:4-
`
`14). Figure 3 further shows a slave device 330 connected to master device 320.
`
`The external memory contains a master segment and a slave segment of the
`
`configuration data. (Col. 5:12-14, memory 310 “store[s] configuration data, or a
`
`configuration bitstream for configuring the plurality of programmable devices 320
`
`and 330”). Wennekamp also describes that the memory may provide a
`
`configuration bitstream in parallel to the master programmable device in response
`
`to addresses and that the master programmable device can provide at least a portion
`
`of the configuration bitstream in parallel to the slave programmable device.
`
`(Col. 2:26-31and 5:16-17). The slave device can then, for example, provide
`
`configuration data to another slave device from the original data provided to the
`
`master device.
`
`Wennekamp further describes a parallel daisy chain configuration (Col.
`
`
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`8
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`Case IPR2012-00020
`Patent 8,058,897
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`5:22-23) that allows for a master device to communicate with other slave devices
`
`without first sending configuration data through another device. With respect to
`
`Figure 4, Wennekamp describes that instructions can be nested in a bitstream to
`
`enable multiple devices to ignore the bitstream data and to target a particular
`
`device in the chain. (Col. 6:31-34). Wennekamp discloses that “by properly
`
`arranging the bitstream, a user may enforce the order in which devices in the chain
`
`are configured.” (Col. 6:40-41).
`
`Xilinx argues that the Petition does not present any prior art that teaches or
`
`suggests a multi-die IC and therefore the “proposed obviousness rejection” is
`
`incomplete, citing MPEP § 2143.03. (Paper 10 at 4:4-5 and 5). The argument is
`
`misplaced. This proceeding is an inter partes one under the procedures set forth
`
`under 37 C.F.R. § 42.100, et. seq., and is not a reexamination proceeding or a
`
`continued prosecution of the involved patent by the USPTO. Therefore, it is
`
`inaccurate to refer to the grounds for unpatentability as a “proposed obviousness
`
`rejection” to be made by the Board.
`
`Moreover, Xilinx has not taken into consideration the level of ordinary skill
`
`in the art as proffered by IVM, i.e., the knowledge of a person of ordinary skill in
`
`the art at the time of the ’897 invention.2 Based on the record before us, IVM has
`
`demonstrated sufficiently that there is a reasonable likelihood that it will prevail
`
`
`2
` The legal determination of obviousness is made on the basis of underlying factual
`inquiries including (1) the scope and content of the prior art; (2) the differences
`between the claimed invention and the prior art; (3) the level of ordinary skill in
`the art; and (4) any objective evidence of unobviousness. Graham v. John Deere
`Co., 383 U.S. 1, 17 (1966).
`
`
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`with respect to the challenge of claim 1 as unpatentable based on Wennekamp.
`
`In support of its Petition, IVM relies on the declaration of Morgan Johnson
`
`(“Johnson”) (Ex. 1002). At the time of his declaration, Johnson was chief scientist
`
`at Advanced Inquiry Systems, Inc. (AISI), a company founded by him in 2001.
`
`Mr. Johnson has a Bachelor of Science degree in Graphics and more than 29 years
`
`of experience in the semiconductor industry. (Ex. 1002, ¶¶ 6-7). Based on the
`
`record before us, a person of ordinary skill in the art would have a BS degree in
`
`Electrical Engineering or equivalent training as well as 3-5 years of experience in
`
`the field of circuit design. (Ex. 1002, ¶ 4). We find that Mr. Johnson has sufficient
`
`qualifications to testify as to the knowledge of a person of ordinary skill in the art.
`
`
`
`In its Petition, IVM takes into account the scope and content of the prior art,
`
`e.g., Wennekamp. (See, e.g., Paper 5 at 5-10 and Ex. 1002, ¶¶ 24-28). The
`
`difference between the claimed invention and Wennekamp is that Wennekamp
`
`does not explicitly describe its invention in the context of dies on ICs, e.g., “multi-
`
`die ICs.” IVM apparently recognizes this. (Paper 5 at 7:1-5; Ex. 1014).
`
`However, Johnson testifies that multi-die ICs had been in extensive use
`
`since long prior to the filing of the ’897 patent and that by the time of the filing of
`
`the ’897 patent the technology of a single package IC containing as few as two dies
`
`was well known.3 (Ex. 1002, ¶¶ 20 and 21). Based on the record before us, multi-
`
`
`
` 3
`
` IVM directs attention to Oh, et al., “The Evolution of CPU Packaging
`Technology and Future Challenges” (EMAP 2006) at Secs. 2.5 and 3. (Paper 5 at
`7). This evidence factually supports the assertions made by Johnson that multi-die
`ICs were known at the time of the invention (see, e.g., section 2.5 describing a
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`die ICs were well known in the art at the time of the ’897 invention.
`
`Johnson further testifies that at the time of the ’897 invention, the placement
`
`of the various devices described in Wennekamp, in the form of dies, on the same or
`
`different ICs would have been a matter of routine implementation and well within
`
`the abilities of one of ordinary skill in the art. (Ex. 1002, ¶ 27). Johnson directs
`
`attention to Wennekamp itself in support of the conclusions Johnson makes, as to
`
`the placement and arrangement of the various devices. (Ex. 1002, ¶ 27). In
`
`addition, IVM argues that providing programmable devices such as those of
`
`Wennekamp in the form of multiple dies in a single IC would minimize routing
`
`path lengths. (Paper 5 at 8). Based on the record before us, Petitioner has made a
`
`threshold showing that it would have been within the knowledge and skill set of a
`
`person of ordinary skill in the art to arrange the Wennekamp programmable
`
`devices as dies on the same or a different IC. One with ordinary skill in the art has
`
`ordinary creativity and is not an automaton. KSR Int'l Co. v. Teleflex Inc., 550 U.S
`
`398, 421 (2007).
`
`For the above reasons, we are not persuaded that the Petition does not
`
`present any teaching or suggestion of a multi-die IC. Xilinx makes no other
`
`arguments with respect to this ground. The Petition additionally sets forth how
`
`Wennekamp teaches the other limitations of claim 1. (Paper 5 at 5-10). Xilinx has
`
`not shown otherwise.
`
`IVM also has demonstrated sufficiently that there is a reasonable likelihood
`
`
`multi-chip package (MCP) containing more than one die (made of silicon) on the
`package (IC) and Figure 7.).
`
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`Case IPR2012-00020
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`that it will prevail with respect to the challenge of claims 2-7, claims, which
`
`depend directly on claim 1, as unpatentable under 35 U.S.C. § 103(a) based on
`
`Wennekamp. For example, claim 4, which depends directly on claim 1, recites
`
`“sending the segment of configuration data for the second IC directly from the
`
`master die of the first IC to the configuration data output of the master die without
`
`first sending the segment of configuration data for the second IC to any other die of
`
`the IC.”
`
`IVM directs attention to Wennekamp as describing a parallel daisy chain
`
`configuration (Ex. 1009, Col. 5:22-23) that allows for a master device to
`
`communicate with other slave devices without first sending configuration data
`
`through another device. Wennekamp also describes, with respect to Figure 4, that
`
`instructions can be nested in a bitstream to enable multiple devices to ignore the
`
`bitstream data and to target a particular device in the chain. (Ex. 1009, Col. 6:31-
`
`34). Wennekamp further describes that “by properly arranging the bitstream, a
`
`user may enforce the order in which devices in the chain are configured.” (Ex.
`
`1009, Col. 6:40-41).
`
`Xilinx makes no specific arguments regarding any one of claims 2-7 as to
`
`this ground of unpatentability.
`
`For the reasons stated above, IVM has demonstrated sufficiently that there is
`
`a reasonable likelihood that it will prevail on its assertion that claims 1-7 are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp.
`
`
`
`
`
`Ground 2 - Claims 1 and 8 (obviousness over
`Wennekamp in combination with Miller)
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`Case IPR2012-00020
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`
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`IVM argues that Wennekamp teaches or suggests each and every feature of
`
`independent claim 1. Miller is relied on by IVM “should further support be
`
`needed” to show mounting and connecting multi-die ICs through an interposer.
`
`(Paper 5 at 15). Specifically, IVM relies upon Miller for its description of two
`
`integrated circuit dies interconnected and packaged together to form a multi-chip
`
`module or “multi-die IC.” The first die is primary, the second die is secondary and
`
`the two dies are connected through an interposer. (Ex. 1010; Abstract). With
`
`respect to all other claim terms, IVM applies the Wennekamp reference to those
`
`claim terms in similar fashion with respect to that of Wennekamp alone (Ground
`
`1). Xilinx does not provide any arguments with respect to Ground 2.
`
`Based on the record before us, IVM has demonstrated sufficiently that there
`
`is a reasonable likelihood that it will prevail on its assertion that claims 1 and 8 are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp in view of
`
`Miller.
`
`Ground 3 - Claims 1 and 8 (obviousness over
`Wennekamp in combination with Walstrum)
`
`This ground for challenging claims 1 and 8 is unnecessary as cumulative in
`
`light of the determination that there is a reasonable likelihood that claims 1 and 8
`
`are unpatentable over Wennekamp in view of Miller (and for claim 1 unpatentable
`
`over Wennekamp). Accordingly, the Petition is denied as to this ground.
`
`Ground 4 – Claims 12-14 (obviousness over
`Wennekamp and either Miller or Walstrum)
`
`Based on the record before us, IVM has demonstrated sufficiently that there
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`Case IPR2012-00020
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`is a reasonable likelihood that it will prevail on its assertion that claims 12-14 are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp in view of
`
`Miller. For example, claim 12, which depends on claim 8, recites “wherein the
`
`first die is configured to send the segment of configuration data for the additional
`
`IC through the first die configuration port without first sending the segment of
`
`configuration data for the additional IC to any other die of the IC.” IVM directs
`
`attention to Wennekamp as describing a parallel daisy chain configuration (Ex.
`
`1009 at Col. 5:22-23) that allows for a master device to communicate with other
`
`slave devices without first sending configuration data through another device.
`
`Wennekamp also describes, with respect to Figure 4, that instructions can be nested
`
`in a bitstream to enable multiple devices to ignore the bitstream data and to target a
`
`particular device in the chain. (Ex. 1009 at Col. 4:31-34). Wennekamp further
`
`describes that “by properly arranging the bitstream, a user may enforce the order in
`
`which devices in the chain are configured.” (Ex. 1009 at Col. 6:40-41).
`
`We understand IVM to argue alternatively that claims 12-14 are
`
`unpatentable based on Wennekamp in view of Walstrum. This basis for
`
`challenging claims 12-14 is unnecessary as cumulative in light of the determination
`
`that there is a reasonable likelihood that claims 12-14 are unpatentable over
`
`Wennekamp in view of Miller. Accordingly, the Petition is denied as to this
`
`portion of Ground 4.
`
`We have considered Xilinx’s argument that Ground 4 is defective for not
`
`providing a statement of the precise relief requested. Specifically, Xilinx argues
`
`that the Petition lumps together many different references using either/or type of
`
`
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`language resulting in an imprecise statement of the relief requested. In support of
`
`the argument, Xilinx only directs attention to the title of Ground 4, for example,
`
`that was used in the Petition. (Paper 10 at 6). However, IVM has substantively
`
`provided an underlying explanation of how the Wennekamp and Miller patents are
`
`applied to claims 12-14. (Paper 5 at 26-27). Xilinx has failed to demonstrate
`
`otherwise. We understand the titles that IVM selected are for edification and
`
`organization purposes and not necessarily representative of the precise nature of
`
`the relief it seeks. Xilinx’s request to ignore Ground 4 based on, for example, the
`
`titles IVM used would put form over substance, which we find to be unreasonable.
`
`
`
`Based on the record before us, IVM has demonstrated sufficiently that there
`
`is a reasonable likelihood that it will prevail on its assertion that claims 12-14 are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp in view of
`
`Miller.
`
`
`
`Grounds 5-8 (unpatentability of claims 1-3, 5-8, 13-14 based on Rally)
`and Ground 9 (claim 9 based on Rally)
`
`We have reviewed IVM’s grounds of unpatentability based on Rally either
`
`alone or in combination with other references. We have determined that those
`
`grounds for challenging claims 1-3, 5-9, 13, and 14 based on Rally are cumulative
`
`to the grounds proposed for challenging the same claims based on Wennekamp.
`
`Accordingly, the Petition is denied as to the grounds based on Rally.
`
`
`
`
`
`
`
`Ground 9 (claim 9 based on Wennekamp, Miller and Siniaguine)
`
`15
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`Case IPR2012-00020
`Patent 8,058,897
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`Based on the record before us, IVM has demonstrated sufficiently that there
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`is a reasonable likelihood that it will prevail on its assertion that claim 9 is
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`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp in view of
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`Miller and Siniaguine. For example, claim 9, which depends on claim 8, recites
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`“wherein the interposer further comprises configurable and active circuitry,
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`wherein the active circuitry is coupled to the configuration bus and implements a
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`circuit design responsive to receiving configuration data through the configuration
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`bus.” In other words, the interposer “can include active circuitry that is
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`configurable in substantially the same way that circuitry within each of dies 105
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`and 110 is configurable.” (Ex. 1001 at Col. 7:13-16). IVM directs attention to
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`Siniaguine’s description of Figure 5 that shows “active areas 350A [that] may be
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`formed in substrate 350 [which is part of interposer 320] for transistors or other
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`elements of ‘clock headers’ 160.” (Paper 5 at 53; Ex. 1013 at Col. 5:18-20). IVM
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`avers that it would have been obvious at the time of the invention to implement this
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`type of known transistor technology to function as claimed, e.g., to receive
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`configurable data similar to the dies receiving configurable data, just as it would be
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`any transistor-based circuit. IVM’s position is reasonable and Xilinx has not
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`demonstrated otherwise. Xilinx argues that Ground 9 is defective for not providing
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`a statement of the precise relief requested. The argument is the same as the one
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`made above with respect to Ground 4 (see, e.g., Paper 10 at 6). The argument is
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`not persuasive as already explained.
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`Case IPR2012-00020
`Patent 8,058,897
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`For reasons already discussed, we do not proceed to trial on the grounds of
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`unpatentability where Walstrum or Rally is involved.
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` Based on the record before us, IVM has demonstrated sufficiently that there
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`is a reasonable likelihood that it will prevail on its assertion that claim 9 is
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`unpatentable under 35 U.S.C. § 103(a) as obvious over Wennekamp in view of
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`Miller and Siniaguine.
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`SUMMARY
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`IVM has demonstrated a reasonable likelihood of prevailing on its challenge
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`of claims 1-9 and 12-14 of the ’897 patent. The Petition is granted as to the
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`following grounds: (i) claims 1-7 as obvious under 35 U.S.C. § 103(a) over
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`Wennekamp; (ii) claims 1, 8 and 12-14 as obvious under 35 U.S.C. § 103(a) over
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`Wennekamp and Miller; and (iii) claim 9 as obvious under 35 U.S.C. § 103(a) over
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`Wennekamp, Miller and Siniaguine. The Petition is denied as to all other grounds.
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`It is
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`ORDER
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`ORDERED that the Petition is GRANTED as to claims 1-9 and 12-14 of the
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`’897 patent based on grounds (i) - (iii) immediately above;
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`Case IPR2012-00020
`Patent 8,058,897
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`FURTHER ORDERED that the Petition is DENIED as to all other grounds
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`set forth in the Petition;
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`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(a), a trial for inter
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`partes review of the ’897 patent is hereby instituted, commencing on the entry date
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`of this Order, and pursuant to 35 U.S.C. § 314(c) and 37 C.F.R. § 42.4, notice is
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`hereby given of the institution of a trial;
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`FURTHER ORDERED that the trial is limited to grounds (i)-(iii)
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`immediately above and no other grounds are authorized; and
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`FURTHER ORDERED that an initial conference call with the Board is
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`scheduled for 1:00 PM ET on March 14, 2013. The parties are directed to the
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`Office Trial Practice Guide, 77 Fed. Reg. 48756, 48765-66 (Aug. 14, 2012) for
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`guidance in preparing for the initial conference call, and should come prepared to
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`discuss any proposed changes to the Scheduling order entered herewith and any
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`motions the parties anticipate filing during the trial.
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`cc:
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`Petitioner:
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`Lori A. Gordon
`Robert G. Sterne
`Sterne, Kessler, Goldstein & Fox, PLLC
`Email: lgordon@skgf.com
`Email: rsterne@skgf.com
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`Patent Owner:
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`Case IPR2012-00020
`Patent 8,058,897
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`
`David M. O’Dell
`Thomas B. King
`Haynes and Boone, LLP
`Email: david.odell@haynesboone.com
`Email: Thomas.king@haynesboone.com
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