Paper 11
`Entered: February 12, 2013
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`Trials@uspto.gov
`Tel: 571-272-7822
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
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`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
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`v.
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`Patent of XILINX, INC.
`Patent Owner
`_______________
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`Case IPR2012-00023
`Patent 7,994,609
`_______________
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`
`
`Before SALLY C. MEDLEY, KARL D. EASTHOM, and JUSTIN T.
`ARBES, Administrative Patent Judges.
`
`EASTHOM, Administrative Patent Judge.
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`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
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`

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`Case IPR2012-00023
`Patent 7,994,609
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`Petitioner, Intellectual Ventures Management, LLC (“IVM”), filed a petition
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`to institute an inter partes review of claims 1-19 of U.S. Patent 7,994,609 owned
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`by Xilinx, Inc. (Paper 3.) See 35 U.S.C. § 311. For the reasons that follow, the
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`Board, acting on behalf of the Director, hereby institutes an inter partes review of
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`the ‘609 patent. See 35 U.S.C. § 314.
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`I. INTRODUCTION
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`The ‘609 patent describes a shielded capacitor in an integrated circuit (IC)
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`having a core capacitor portion which includes multiple layers of conductive
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`elements. Shields, including a shield capacitor portion and a reference shield,
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`surround the core capacitor portion. The shield capacitor portion has multiple
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`conductive elements in different metal layers. According to claim 1, the shield
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`capacitor portion forms part of a capacitor node and lies partially between the
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`reference shield and the core capacitor portion. The shields reduce electronic
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`noise. (See Ex. 1001, col. 2, l. 40 to col. 3, l. 3; col. 5, ll. 1-4; col. 6, ll. 24-31;
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`Abstract.)
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`IVM annotates Figures 2A and 2B from the ‘609 patent to identify some of
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`the disclosed elements recited in claim 1:
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`(Paper 3 at 4-5.)
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`IVM’s annotated figures supra show the centrally located core capacitor
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`including a first (T1, T2) and second (B1, B2) plurality of elements, the numbered
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`conductive layers, two capacitor nodes, and shields. With respect to claim 1
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`(which follows) and similar claim 13, layer T corresponds to a second part of a
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`first capacitor node, layers B and B’ correspond partially to a shield capacitor
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`portion and a second part of a second capacitor node, and the VDD shield
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`corresponds to a reference shield.
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`Representative claim 1 follows with bracketed information added to help
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`illustrate an example (i.e., without limitation) structure depicted in the annotated
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`figures supra representing claim elements:
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`1. A capacitor in an integrated circuit (“IC”) comprising:
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`a core capacitor portion having a first plurality of conductive elements [see
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`T1,T2] electrically connected to and forming a first part of a first node of the
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`capacitor formed in a first conductive layer of the IC and a second plurality
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`of conductive elements [see B1, B2] electrically connected to and forming a
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`first part of a second node of the capacitor formed in the first conductive
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`layer, the first plurality of conductive elements alternating with the second
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`plurality of conductive elements in the first conductive layer, and a third
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`plurality of conductive elements [see T] electrically connected to and
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`forming a second part of the first node formed in a second conductive layer
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`adjacent to the first conductive layer, at least portions of some of the second
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`plurality of conductive elements overlying and vertically coupling to at least
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`portions of some of the third plurality of conductive elements;
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`a shield capacitor portion [see B, B’] having a fourth plurality of
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`conductive elements formed in at least the first conductive layer of the IC,
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`the second conductive layer of the IC, a third conductive layer of the IC, and
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`a fourth conductive layer of the IC, the first conductive layer and the second
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`conductive layer each being between the third conductive layer and the
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`fourth conductive layer, the shield capacitor portion being electrically
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`connected to and forming a second part of the second node of the capacitor
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`and surrounding the first plurality of conductive elements and the third
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`plurality of conductive elements; and
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`a reference shield [see VDD Shield] electrically connected to a reference
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`node of the IC other than the second node of the capacitor, the shield
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`capacitor portion being disposed between the reference shield and the core
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`capacitor portion.
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`IVM asserts the following six obviousness grounds of rejection under 35
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`U.S.C. § 103:
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`Ground 1. Claims 1, 3, 5, 6, and 10-12 based on Paul, U.S. 6,737,698 (May
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`18, 2004).
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`Ground 2. Claims 2 and 13-17 based on Paul and Anthony, U.S. 7,439,570
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`(Oct. 21, 2008).
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`Ground 3. Claim 4 based on Paul and Hsueh, U.S. 7,286,071 (Oct. 23,
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`2007).
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`Ground 4. Claims 7-9 based on Paul and Brennan, U.S. 6,903,918 (June 7,
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`2005).
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`Ground 5. Claims 18 and 19 based on Anthony and Marotta, U.S. 7,238,981
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`(July 3, 2007).
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`Ground 6. Claims 1 and 13 based on Anthony and Bi, U.S. Pub.
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`2008/0128857 (June 5, 2008).
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`II. DECISION ON PETITION
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`A. Claim Construction
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`The Board interprets a claim in an inter partes review using the “broadest
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`reasonable construction in light of the specification of the patent in which it
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`appears.” 37 C.F.R. § 42.100(b). See also Office Patent Trial Practice Guide, 77
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`Fed. Reg. 48756, 48766 (Aug. 14, 2012) (Claim Construction). There is a “heavy
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`presumption” that a claim term carries its ordinary and customary meaning. CCS
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`Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). But
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`claims “must be read in view of the specification. . . . [T]he specification is always
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`highly relevant to the claim construction analysis. Usually, it is dispositive; it is
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`the single best guide to the meaning of a disputed term.” See Phillips v. AWH
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`Corp., 415 F.3d, 1303, 1317 (Fed. Circ. 2005) (en banc).
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`The following claim construction applies.
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`Shield. In the context of the ‘609 patent and as supported by Paul, a “shield”
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`as recited in the claims includes at least one conductive layer (whether including
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`separate strips or not) which is outside one or more capacitor core layers but which
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`may or may not form a capacitor node. (Compare Ex. 1001 at Fig. 3A (‘609
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`patent’s grounded shield VDD and node shields B, B’); col. 5, ll. 1-7; col. 6, ll. 15-
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`16 with Ex. 1006 at Fig. 6 (Paul’s node shields 608, 610); Fig. 13 (Paul’s grounded
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`shields 1308, 1310); Abstract.)
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`All other terms are given their ordinary and customary meaning that those
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`terms would have to a person of ordinary skill in the art in light of the ‘609 patent
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`specification.
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`B. Grounds 1-6
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`The standard for instituting an inter partes review is set forth in 35 U.S.C. §
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`314(a):
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`THRESHOLD – The Director may not authorize an inter partes
`review to be instituted unless the Director determines that the
`information presented in the petition filed under section 311 and any
`response filed under section 313 shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of
`the claims challenged in the petition.
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`Pursuant to the defined threshold under 35 U.S.C. § 314(a), the Board
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`institutes an inter partes review based on Grounds 1-6 for the reasons outlined
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`below.
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`Ground 1
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`Relying on the declaration of Morgan T. Johnson (“Johnson Declaration”)
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`(Ex. 1002), IVM edits and annotates figures from Paul (Ex. 1006) to show how
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`features from different figures in the reference could be combined to satisfy claims
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`1, 3, 5, 6, and 10-12. (See Paper 3 at 6-23.)
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`With respect to claim 1 and some of the dependent claims, IVM cites to
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`Paul’s disclosure that “‘one or more shields are disposed around layers of
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`conductive strips to shield the capacitor.’” (See Paper 3 at 12 (quoting Ex.1006 at
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`abstract, emphasis by IVM).) IVM also points to Paul’s use of “‘side shield[s].’”
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`(See Paper 3 at 10 (quoting Ex. 1006 at col. 4, l. 29).) IVM also relies on Paul’s
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`purpose for using one or more such shields – to “‘confine the electric fields . . .
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`within the limits of the shields.’” (See Paper 3 at 9 (quoting Ex. 1006 at col 3, ll.
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`34-36; accord Ex. 1006 abstract).) IVM also relies on Paul’s statement that
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`“‘various combinations of [the explicitly disclosed] configurations are also
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`possible.’” (See Paper 3 at 7 (quoting Ex. 1006 at col. 3, ll. 66-67).)
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`Based on Paul’s teachings and the Johnson Declaration, IVM produces the
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`following edited and annotated versions of Paul’s Figures 8 and 13:
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`(Paper 3 at 11, 12.) As the captions in the reproduced figures indicate, the Johnson
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`Declaration provides the above edited and annotated versions of Paul’s figures to
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`support the obviousness rejection of claims under Ground 1.
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`In essence, Johnson testifies that, given Paul’s disclosure and routine
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`knowledge, skilled artisans would have tended to produce symmetrically shielded
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`capacitors with multiple shields such as the capacitor in edited and annotated
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`Figure 13 from Paul as shown above. Johnson opines that a person of ordinary
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`skill would have utilized multiple shields to obtain the predictable results of
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`confining electrical fields to minimize the effects of electrical discontinuities and
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`fluctuations in dielectric-to-conductor spacing, and to maximize electrical
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`performance including bandwidth. (See Ex. 1002 at ¶ 37 and Fig. A3; Paper 3 at
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`11-14 (summarizing the Johnson Declaration and Paul).)
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`In response, Xilinx states that Paul teaches away from combining the two
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`different embodiments exemplified in Figures 8 and 13. Xilinx argues that when
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`Paul teaches applying a reference shield to a reference voltage such as a ground, as
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`Paul does in Figure 13, that Paul teaches applying it to “‘a reference voltage (e.g.,
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`ground) rather than to nodes A or B.’” (Paper 9 at 6 (quoting Ex. 1006 at col. 4, ll.
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`60-64, emphasis and bracketed information by Xilinx).) Xilinx reasons, citing a
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`dictionary definition, that Paul’s use of the word “rather” in relation to Figure 13
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`amounts to teaching away from combining two embodiments – for example,
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`because “‘rather than . . . indicate[s] negation as a contrary choice.’” (See Paper 9
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`at 7, n. 3 (quoting dictionary, cite omitted).)
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`In the context of Paul, the word “rather” does not discourage a skilled artisan
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`from combining two embodiments – or from using extra shield layers connected to
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`ground or otherwise to provide more shielding. As IVM shows, Paul teaches using
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`more than one shield layer and explicitly teaches combining different
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`embodiments. Also, even if the noted passage in Paul describes a preference for
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`connecting the “top and bottom shields” to ground (Ex. 1006, col. 4, ll. 61-63), that
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`passage does not preclude or teach away from other shield nodes which may or
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`may not be connected to conductive capacitor nodes – e.g., the shielding nodes (A,
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`B) which Paul’s Figures 4-12 depict.
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`As discussed at the outset, in the context of the ‘609 patent and in Paul, a
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`shield simply includes a conductive or metal layer (of strips or otherwise) which is
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`outside one or more capacitor core metal layers but which may or may not form a
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`capacitor node. As noted above, the Johnson Declaration indicates that multiple
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`shield layers would enhance the capacitor’s electrical performance. Paul
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`corroborates Johnson’s analysis and explains that “[t]he shields confine the electric
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`fields between the limits of the shields.” (Ex. 1006, abstract.) In other words, Paul
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`is concerned with confining the fields and ensuring that stray fields do not impact
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`the integrated circuit, and the record indicates that combining embodiments as
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`IVM proposes enhances rather than defeats that purpose. As such, IVM’s
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`showings establish a reasonable likelihood of success.
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`IVM similarly produces claim charts and annotated circuits and relies on the
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`Johnson Declaration to support rejections for claims 3, 5, 6, 10, 11, and 12. (See
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`Paper 3 at 14-23.) Xilinx does not respond to IVM’s showings. IVM’s showings
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`for these dependent claims detail the claim limitations and establish a reasonable
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`likelihood of success.
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`As an example, claim 12 requires a second reference shield. To satisfy
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`claim 12, IVM proposes further modifying annotated Figure A.4 supra such that
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`the second reference shield lies above the reference shield recited in claim 1. (See
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`Paper 3 at 21-23 (relying on Figure C of the Johnson Declaration – an annotated
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`and edited version of Figure 13 of Paul).) IVM relies on the Johnson Declaration
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`which states that certain capacitor designs cause capacitive value fluctuations
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`caused by small discontinuities in the shielding, thereby motivating a skilled circuit
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`designer to simulate capacitor structures in a software system which would indicate
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`in some cases the requirement for a “third node” approach as shown in Figure C of
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`the Johnson Declaration. (See Paper 3 at 22; Ex. 1002 at ¶ 45.)
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`In other words, similar to the analysis of claim 1, IVM essentially reasons
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`that discontinuities or other electrical field concerns may require additional shields
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`to ensure electric fields are confined – thereby suggesting a reason for adding
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`another shield layer to the modified version of Paul depicted supra. Paul supports
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`IVM’s rationale, disclosing that “one or more shields are disposed around layers of
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`conductive strips to shield the capacitor.” (Ex. 1006, Abstract.) Based on the
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`foregoing discussion, IVM’s petition establishes a reasonable likelihood of success
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`for Ground 1 and claims 1, 3, 5, 6, and 10-12.
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`Grounds 2-4
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`Grounds 2-4 pertain to rejections of dependent claims 2, 4, 7-9, and 13-17.
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`IVM produces claim charts and modified circuit diagrams to map claim elements
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`onto the combinations of Paul and Anthony, Hsueh, or Brennan and show that the
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`prior art combinations satisfy the dependent claims. (Paper 3 at 23-44.) Xilinx
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`responds by relying on arguments presented for Ground 1 – i.e., asserting the
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`above-discussed alleged deficiencies in Paul. (See Paper 9 at 7.)
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`IVM’s petition establishes a reasonable likelihood of success as to Grounds
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`2-4. As an example, per Ground 2, IVM asserts that Paul discloses everything
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`recited in claim 2 except “the fourth layer is a poly layer of the IC or that a second
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`node shield is formed in the poly layer.” (Paper 3 at 24.) IVM relies on Anthony
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`(Ex. 1007) and the Johnson Declaration to support modifying Paul’s bottom metal
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`shield layer 810 and forming it as part of a bottom polysilicon layer pursuant to
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`Anthony’s teaching that a polysilicon layer can be used as a shield plate. (See
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`Paper 3 at 24 (quoting Ex. 1007 at col. 4, ll. 49-52).) IVM also reasons that such a
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`metal and poly shield structure further isolates the capacitor and reduces parasitic
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`capacitance. (See id. at 25 (citing Ex. 1002 at ¶ 50; Ex. 1007 at col. 5, ll. 2-3).)1
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`IVM makes similar showings for the remaining claims under Grounds 2-4.
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`IVM’s petition establishes a reasonable likelihood of success as to Grounds 2-4
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`and claims 2, 4, 7-9, and 13-17.
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`Ground 5
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`IVM, in further reliance on the Johnson Declaration, provides annotated
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`diagrams and maps the recited claim 18 and 19 elements onto the combination of
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`Anthony and Marotta to support its asserted ground of unpatentability based on
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`obviousness. (See Paper 3 at 44-51.) Xilinx asserts that IVM fails to show that the
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`combination “has a second plate of a capacitor formed in a substrate as required
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`by claim 18.” (Paper 9 at 8 (emphasis by Xilinx).) Xilinx points out that the ‘609
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`patent discloses as an example, an “overlying conductive layer as a first plate and a
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`1 Anthony states that “[a]s many metal layers as available may be used in this way
`to minimize parasitic capacitance.” (Ex. 1007 at col. 5, ll. 2-3.)
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`doped region of a substrate as a second plate.” (Paper 9 at 9.)
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`IVM relies on the bottom shield plate 46 of Anthony’s Figure 4 to satisfy the
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`disputed second plate. (Paper 3 at 46.) Xilinx challenges this characterization of
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`Anthony and asserts that Anthony does not refer to that bottom plate 46 as a
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`capacitor second plate, but rather, discloses another capacitor second plate in the
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`capacitor 30. (Paper 9 at 11.)
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`Xilinx’s challenge does not overcome IVM’s showing. As Xilinx
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`acknowledges, a capacitor structure simply requires “a first plate and a second
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`plate with a dielectric interposing the plates.” (See Paper 9 at 8.) IVM’s annotated
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`Figure 4 shows a bottom or second shield plate 46 and first plate 34 that has a
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`dielectric interposing the two plates and satisfies the claimed capacitor structure,
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`regardless of what Anthony calls the structure. (See Paper 3 at 46 (annotated Fig.
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`4).)
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`As indicated, IVM details how the prior art combination satisfies the
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`disputed limitation and the other limitations recited in claims 18 and claim 19. As
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`such, IVM’s petition establishes a reasonable likelihood of success as to Ground 5.
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`Ground 6
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`IVM supports a showing of obviousness of claims 1 and 13 by mapping
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`claim elements to the combination of Anthony and Bi. (Paper 3 at 52-58.)
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`According to IVM, Anthony shows all the claim elements except for the core
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`capacitor portion having first and second conductive layers as recited in the claims.
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`Relying on the Johnson Declaration, Bi, and descriptions in the Background
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`section of the ‘609 Patent describing prior art integrated capacitors (see Ex. 1001 at
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`col. 1, ll. 49-55), IVM sets forth supporting rationale for employing Bi’s first and
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`second layers in the core of Anthony’s shielded capacitor – for example, to
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`increase the capacitance. (Paper 3 at 52-53.)
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`Xilinx does not challenge Ground 6. IVM’s petition establishes a reasonable
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`likelihood of success as to Ground 6.
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`Summary
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`Taking into account Xilinx’s preliminary response, IVM’s petition
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`sufficiently demonstrates a reasonable likelihood that claims 1-19 are unpatentable
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`based on Grounds 1-6. See 37 C.F.R. § 42.108.
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`III. ORDER
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`In consideration of the foregoing, it is hereby
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`ORDERED that the Petition is granted as to Grounds 1-6 and claims 1-19 of
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`the ʼ609 patent;
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`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(a), inter partes
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`review of the ʼ609 patent is hereby instituted with trial commencing on the entry
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`date of this Order, and pursuant to 35 U.S.C. § 314(c) and 37 C.F.R. § 42.4, notice
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`is hereby given of the institution of the trial;
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`FURTHER ORDERED that the trial is limited to the grounds identified
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`above and no other grounds are authorized; and
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`FURTHER ORDERED that an initial conference call with the Board is
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`scheduled for 1:00 PM ET on March 14, 2013. The parties are directed to the
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`Office Trial Practice Guide, 77 Fed. Reg. 48756, 48765-66 (Aug. 14, 2012) for
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`guidance in preparing for the initial conference call, and should be prepared to
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`discuss any proposed changes to the Scheduling Order entered herewith and any
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`motions the parties anticipate filing during the trial.
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`Case IPR2012-00023
`Patent 7,994,609
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`For Petitioner:
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`Lori Gordon
`Robert Sterne
`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
`lgordon@skgf.com
`RSTERNE@skgf.com
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`For Patent Owner:
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`David M. O’Dell
`Thomas B. King
`HAYNES AND BOONE, LLP
`david.odell@haynesboone.com
`thomas.king@haynesboone.com
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