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`571-272-7822 Entered: February 19, 2014
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`SYNOPSYS, INC.
`Petitioner
`
`v.
`
`MENTOR GRAPHICS CORPORATION
`Patent Owner
`____________________
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`
`___________________
`
`
`
`Before HOWARD B. BLANKENSHIP, SALLY C. MEDLEY, and
`JENNIFER S. BISK, Administrative Patent Judges.
`
`
`BISK, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
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`
`
`Trials@uspto.gov
`571-272-7822 Entered: February 19, 2014
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`SYNOPSYS, INC.
`Petitioner
`
`v.
`
`MENTOR GRAPHICS CORPORATION
`Patent Owner
`____________________
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`
`___________________
`
`
`
`Before HOWARD B. BLANKENSHIP, SALLY C. MEDLEY, and
`JENNIFER S. BISK, Administrative Patent Judges.
`
`
`BISK, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`
`
`
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`
`
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`Case IPR2012-00042
`Patent 6,240,376 B1
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`I. INTRODUCTION
`
`A. Background
`
`Petitioner, Synopsys, Inc. (“Synopsys”), filed a petition on
`
`September 26, 2012, for inter partes review of claims 1-15 and 20-33 of
`
`U.S. Patent No. 6,240,376 B1 (“the ’376 Patent”) pursuant to 35 U.S.C. §§
`
`311-319. Paper 1 (“Pet.”). Patent Owner, Mentor Graphics Corporation
`
`(“Mentor Graphics”), filed a preliminary response on December 28, 2012.
`
`Paper 15 (“Prelim. Resp.”). On February 22, 2013, the Board denied the
`
`petition as to claims 10, 12-15, 20-27, and 30-33, and instituted trial for
`
`claims 1-9, 11, 28, and 29, on one ground of unpatentability, anticipation by
`
`U.S. Patent No. 6,132,109 (“Gregory”) (Ex. 1007). Paper 16 (“Decision to
`
`Institute”).
`
`After institution of trial, Mentor Graphics filed a patent owner
`
`response. Paper 28 (“PO Resp.”). Mentor Graphics also filed a substitute
`
`motion to amend claims by submitting proposed new claims 34-43 for
`
`claims 1, 5, 28, 2, 3, 6, 8, 9, 11, and 29, respectively. Paper 31 (“Mot. to
`
`Amend”). Synopsys filed a reply to the patent owner response (Paper 36;
`
`“Reply”), and also an opposition to Mentor Graphics’s motion to amend
`
`(Paper 35; “Opp.”). Mentor Graphics then filed a reply in support of its
`
`motion to amend. Paper 39 (“Reply Mot. to Amend”).
`
`In preparation for oral hearing, both parties filed and fully briefed
`
`motions to exclude. Paper 42 (“Mentor Graphics’s Motion to Exclude”);
`
`Paper 44 (“Synopsys’s Motion to Exclude”). Oral hearing was held
`
`November 14, 2013. Paper 59 (“Transcript”).
`
`The Board has jurisdiction under 35 U.S.C. § 6(c). This final written
`
`decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
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`Patent 6,240,376 B1
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`Synopsys has shown that claims 5, 8, and 9 are unpatentable.
`
`Synopsys, however, has not met its burden to show by a preponderance of
`
`the evidence that claims 1-4, 6, 7, 11, 28, and 29 are unpatentable.
`
`Mentor Graphics’s motion to amend claims is denied.
`
`B. The ’376 Patent
`
`The ’376 patent generally relates to the fields of simulation and
`
`prototyping of integrated circuits. Ex. 1001, col. 1, ll. 10-11. In particular,
`
`the patent describes “debugging synthesizable code at the register transfer
`
`level during gate-level simulation.” Id. at ll. 11-13.
`
`As described in the Background of the Invention, integrated circuit
`
`design begins with a description of the behavior desired in a hardware
`
`description language (“HDL”) such as Very High Speed Integrated Circuit
`
`Description Language (“VHDL”). Id. at ll. 14-25. A subset of HDL source
`
`code is referred to as Register Transfer Level (“RTL”) source code. Id. at
`
`ll. 28-30. This RTL source code can be simulated using software, which
`
`typically offers robust debugging functionality for analyzing and verifying
`
`the design, including navigating the design hierarchy, viewing the RTL
`
`source code, setting breakpoints on a statement of RTL source code to stop
`
`the simulation, and viewing and tracing variables and signal values. Id. at
`
`ll. 44-54. However, although flexible, software RTL simulators are slow
`
`compared with hardware emulation. Id. at ll. 55-63. Thus, it often is
`
`desirable to use gate-level simulation to verify complex designs. Id.
`
`The RTL description of a circuit can be used by synthesis tools to
`
`generate a “gate-level netlist,” which, in turn, can be converted to a format
`
`suitable for programming a hardware emulator. Id. at ll. 35-42. A gate-level
`
`netlist represents the circuit to be simulated and ultimately is comprised of
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`combinatorial or sequential logic gates (e.g. AND, NAND, and NOR gates,
`
`or flip-flops and latches) and a description of their interconnections using
`
`signals (signals are also referred to as nets). Id. at col. 4, ll. 5-17. As
`
`discussed, gate-level simulation is useful for validation of a circuit design.
`
`Id. at col. 1, ll. 55-67. However, one disadvantage of gate-level simulation
`
`is that much of the high-level information from the RTL source code is lost
`
`during synthesis, resulting in debugging functionality that is limited severely
`
`in comparison with that available in software RTL simulation. Id. at col. 2,
`
`ll. 1-23.
`
`The ’376 patent describes a method of synthesizing RTL source code
`
`such that the resulting gate-level simulation can support the traditional
`
`debugging tools of setting breakpoints, mapping signal values to particular
`
`source code lines, and stepping through the source code to trace variable
`
`values. Id. at ll. 1-30. The Summary of the Invention describes facilitating
`
`debugging during gate-level simulation by: (1) generating “instrumentation
`
`logic indicative of the execution status of at least one synthesizable
`
`statement within the RTL source code”; (2) generating a gate-level netlist
`
`from the RTL source code; and (3) during simulation, evaluating the
`
`instrumentation logic of the gate-level netlist to enable RTL debugging. Id.
`
`at ll. 26-39.
`
`The ’376 patent describes two main embodiments for implementing
`
`this method. The first embodiment modifies the gate-level netlist to provide
`
`instrumentation signals “implementing the instrumentation logic and
`
`corresponding to synthesizable statements within the RTL source code.” Id.
`
`at ll. 40-43. This modification of the gate-level netlist can be done either by
`
`modifying the RTL source code directly or by generating the modified gate-
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`level netlist during synthesis. Id. at ll. 43-46. The second embodiment (“the
`
`cross-reference embodiment”) describes storing the instrumentation signals
`
`in a cross-reference database instead of modifying the gate-level netlist. Id.
`
`at ll. 47-52.
`
`Figure 2 of the ’376 patent, reproduced below, illustrates “one
`
`embodiment of the instrumentation process in which instrumentation is
`
`integrated with the synthesis process.” Id. at col. 5, ll. 9-11.
`
`
`
`Figure 2, above, shows that RTL source code 210 is provided to synthesis
`
`process 220, which includes instrumentation step 234 followed by synthesis
`
`step 240. Id. at ll. 11-16. In the first embodiment, in which the gate level
`
`netlist is modified to include instrumentation signals, the resulting gate-level
`
`design 250 “contains additional logic to create the additional instrumentation
`
`output signals referenced in instrumentation data 238.” Id. at ll. 17-30.
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`Instrumentation data 238 is implemented as gates that can then be simulated.
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`Id. at col. 6, ll. 32-37.
`
`In the cross-reference embodiment, “the RTL source code is analyzed
`
`to generate a cross-reference database as instrumentation data 238 without
`
`modifying the gate-level design.” Id. at col. 5, ll. 31-33. In this
`
`embodiment, “[t]he instrumentation data 238 is likely to contain
`
`considerably more complex logic to evaluate during simulation.” Id. at
`
`ll. 42-45.
`
`
`
`The ’376 patent describes tradeoffs between the two main
`
`embodiments. Id. at l. 45. For example, the first embodiment reduces the
`
`complexity of the logic to be evaluated during simulation, resulting in faster
`
`simulation time. Id. at ll. 46-64. However, because the gate-level design
`
`used during simulation is modified to accommodate the debugging logic, the
`
`design actually used for production will differ from that used during
`
`simulation, and, thus, the simulation may not reproduce accurately the
`
`production behavior of the circuit. Id. On the other hand, the cross-
`
`reference embodiment typically results in greater complexity of
`
`instrumentation logic to evaluate during simulation, resulting in longer
`
`simulation time. Id. at ll. 65-67. In addition, some of the evaluation may be
`
`performed by software, instead of hardware, eliminating direct verification
`
`of the target system through in-situ verification. Id. at col. 5, l. 65 – col. 6,
`
`l. 11. However, the technique does not affect the original gate-level design,
`
`and the instrumentation data can be eliminated after testing without
`
`disrupting the gate-level design. Id. Because of these various tradeoffs, the
`
`’376 patent mentions generally, but does not describe in detail, alternate
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`embodiments that combine the two main embodiments “in order to trade off
`
`simulation speed, density, and verification accuracy.” Id. at col. 6, ll. 17-22.
`
`The ’376 patent subsequently describes (in Figures 3, 12, and 17 and
`
`the related text) three methods of modifying the gate-level netlist. Id. at
`
`col. 13, ll. 38-40. As described when discussing the first embodiment above,
`
`the ’376 patent discloses that these three methods can be applied either by
`
`modifying the RTL source code directly by applying the method to the
`
`source code before it is synthesized independently of the synthesis process
`
`(id. at ll. 55-59), as shown in Figures 3, 12, and 17, or they can be integrated
`
`into the synthesis tool so that actual modification of the RTL source code is
`
`not required (id. at ll. 60-67).
`
`Figure 3, reproduced below, illustrates a method of modifying RTL
`
`source code for sequential statements that depend only on the value of the
`
`inputs and can be synthesized to logic networks of combinatorial gates and
`
`latches (“level-sensitive RTL source code”). Id. at col. 7, ll. 13-22, 40-43.
`
`
`
`Figure 3, above, shows a method in which a unique local variable is
`
`created for each list of adjacent sequential statements in step 310, each of
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`these variables is initialized to zero in step 320, and one unique variable
`
`assignment statement is inserted into each list of adjacent sequential
`
`statements corresponding to an executable branch in step 330. Id. at ll. 40-
`
`50. At the end of the process, all the unique local variables are assigned to
`
`global signals in step 340. Id. at ll. 50-54.
`
`Figure 12, reproduced below, illustrates a method of modifying RTL
`
`source code having references to signal events, typically used to describe
`
`edge-sensitive devices such as flip-flops. Id. at col. 9, ll. 27-32, 63-64.
`
`
`
`The method shown in Figure 12, above, begins with step 1210, in
`
`which every signal whose state transition serves as the basis for the
`
`determination of another signal is sampled. Id. at ll. 63-67. An
`
`instrumentation signal event is generated in step 1220, and every process
`
`that references a signal event is duplicated in step 1230. Id. at col. 9, l. 67 –
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`col. 10, l. 7. In step 1240 each list of sequential statements within the
`
`duplicate version of the code is replaced by a unique local variable
`
`assignment. In step 1250, each time a signal event is referenced in the
`
`duplicated version of the code, it is replaced by the sampled signal event
`
`computed in step 1210. Id. at col. 10, ll. 7-12. Finally, the RTL source code
`
`is synthesized, in step 1260, to generate gate-level logic, including the
`
`instrumentation signals. Id. at ll. 12-14.
`
`Figure 17, reproduced below, illustrates a method of modifying RTL
`
`source code for processes themselves for subsequent determination of
`
`whether the process is active during gate-level simulation. Id. at col. 11,
`
`ll. 43-46.
`
`
`
`
`
`
`
`Figure 17, above, shows a method in which the sensitivity list of a
`
`process is identified in step 1710, logic is generated to compare the signals
`
`in the sensitivity list between consecutive simulation cycles in step 1720,
`
`and during gate-level simulation in step 1730, a determination is made as to
`
`whether an event has occurred on any of the sensitivity list signals. Id. at
`
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`ll. 48-53. If the signal indicates a difference during a simulation cycle, as
`
`indicated by step 1740, the process is active; otherwise, the process is
`
`inactive, as indicated by step 1750. Id. at ll. 53-58.
`
`C. Illustrative Claims
`
`Three of the claims involved in this proceeding, claims 1, 5, and 28,
`
`are independent. All three are reproduced below:
`
`1. A method comprising the steps of:
`
`a) identifying at least one statement within a register
`transfer level (RTL) synthesizable source code; and
`
`b) synthesizing the source code into a gate-level netlist
`including at least one instrumentation signal, wherein the
`instrumentation signal is indicative of an execution status
`of the at least one statement.
`
`5. A method of generating a gate level design, comprising the
`steps of:
`
`a) creating an instrumentation signal associated with at least
`one synthesizable statement contained in a register
`transfer level (RTL) synthesizable source code; and
`
`b) synthesizing the source code into a gate-level design
`having the instrumentation signal.
`
`28. A storage medium having stored therein processor
`executable instructions for generating a gate-level design from a
`register transfer level (RTL) synthesizable source code, wherein
`when executed the instructions enable the processor to
`synthesize the source code into a gate-level netlist including at
`least one instrumentation signal, wherein the instrumentation
`signal is indicative of an execution status of at least one
`synthesizable statement of the source code.
`
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`II. ANALYSIS
`
`A. 35 U.S.C. § 315(b)
`
`As a threshold issue, Mentor Graphics argues that this proceeding is
`
`barred by virtue of the relationship between Synopsys and the companies of
`
`Synopsys Emulation and Verification, S.A. and EVE-USA, Inc. (collectively
`
`“EVE”). PO Resp. 2-22. Mentor Graphics bases these arguments on the
`
`following facts.
`
`Luc Burgun, a named inventor of the ’376 patent, was, at one time, a
`
`Mentor Graphics employee. PO Resp. 3 (citing Ex. 2028: Ex. 5 at 1-4.1
`
`Burgun assigned all rights in the invention claimed in the ’376 patent to
`
`Mentor Graphics. Id. (citing Ex. 2029: Ex. 2 at 3). Subsequently, Burgun
`
`left Mentor Graphics and went to work for EVE. Id. In 2006, Mentor
`
`Graphics filed suit against EVE in the United States District Court for the
`
`District of Oregon, alleging that EVE’s ZeBu emulators infringed the ’376
`
`patent. Id. at 4 (citing Ex. 2001); Mentor Graphics Corp. v. EVE-USA, Inc.,
`
`06-341-AA (D. Or. 2006). That case was dismissed with prejudice pursuant
`
`to a settlement agreement. Ex. 2003. Shortly after filing the petition in the
`
`present case, EVE and Synopsys jointly filed a declaratory judgment action
`
`in the United States District Court for the Northern District of California,
`
`seeking a ruling of non-infringement and invalidity of the ’376 patent. Ex.
`
`2004. The complaint states that “[o]n September 27, 2012, Synopsys, Inc.
`
`entered into an agreement to acquire the business of EVE,” which
`
`acquisition “is expected to close in the immediate future.” Id. at ¶ 13.
`
`
`1 Exhibits 2028 and 2029 are large exhibits, not paginated consecutively,
`including many non-sequentially numbered Exhibits. Throughout this
`Decision, citations to these exhibits will be of the form “Ex. 202[8 or 9]:
`[Ex. # within Ex. 202X at page number of that Ex. #].”
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`Mentor Graphics contends that the acquisition took place on October 4,
`
`2012. PO Resp. 4-5 (citing Ex. 2029: Ex. 34 at 20).
`
`1. Privity
`
`Mentor Graphics argues that this inter partes review is barred because
`
`Synopsys and EVE were in privity at the time of the Decision to Institute.
`
`Id. at 6-7. Mentor Graphics asserts that based on this relationship the
`
`complaint served on EVE in the May 2006 case should trigger § 315(b). Id.
`
`at 6. We disagree with Mentor Graphics’s contentions.
`
`35 U.S.C. § 315(b) states as follows:
`
`An inter partes review may not be instituted if the
`petition requesting the proceeding is filed more than 1 year after
`the date on which the petitioner, real party in interest, or privy
`of the petitioner is served with a complaint alleging
`infringement of the patent. The time limitation set forth in the
`preceding sentence shall not apply to a request for joinder under
`subsection (c).
`
`The Office promulgated a rule interpreting § 315(b), 37 C.F.R.
`
`§ 42.101(b), which states that:
`
`A person who is not the owner of a patent may file with the
`Office a petition to institute an inter partes review of the patent
`unless:
`. . .
`(b) The petition requesting the proceeding is filed more than
`one year after the date on which the petitioner, the petitioner’s
`real party-in-interest, or a privy of the petitioner is served with a
`complaint alleging infringement of the patent.
`
`This rule makes clear that it is only privity relationships up until the time a
`
`petition is filed that matter; any later-acquired privies are irrelevant.
`
`Furthermore, privity is a “flexible and equitable” doctrine rooted in
`
`common law. Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756,
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`48,759 (Aug. 14, 2012). Consistent with this doctrine, we also take into
`
`consideration the nature of the relationship between the parties at the time
`
`that the statutorily-referenced complaint was served. See, e.g., Taylor v.
`
`Sturgell, 553 U.S. 880, 892 (2008) (“A person who was not a party to a suit
`
`generally has not had a ‘full and fair opportunity to litigate’ the claims and
`
`issues settled in that suit.”); Mars Inc. v. Nippon Conlux Kabushiki-Kaisha,
`
`58 F.3d 616, 619 (Fed. Cir. 1995) (applying res judicata to parent
`
`corporation because it controlled wholly-owned subsidiary during prior
`
`litigation). Mentor Graphics has not alleged that Synopsys was a privy of
`
`EVE in 2006 when EVE was served with a complaint alleging infringement
`
`of the ’376 patent. Thus, there is no contention that Synopsys had any
`
`control of this previous suit or even had notice of it, along with an
`
`opportunity to participate while it was still pending. See Richards v.
`
`Jefferson Cnty., Ala., 517 U.S. 793 (1996) (holding no estoppel where
`
`subsequent plaintiffs were not provided notice of first suit nor adequately
`
`represented in it). Thus, this lack of relationship between Synopsys and
`
`EVE in the 2006 litigation is another reason to conclude that there was no
`
`privity relationship between Synopsys and EVE sufficient to trigger
`
`§ 315(b)’s prohibitions.
`
`Moreover, no record evidence suggests that Synopsys’s petition for
`
`review was timed to inject delay into an already-pending litigation and, thus,
`
`this case does not implicate the concerns that this statute appears designed to
`
`address. H.R. REP. NO. 112-98, at 45 (2011) (explaining § 315(b) as “Time
`
`limits during litigation. Parties who want to use inter partes review during
`
`litigation are required to seek a proceeding within 12 months of being served
`
`with a complaint alleging infringement of the patent.”); 157 CONG. REC.
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`S1326 (daily ed. Mar. 7, 2011) (statement of Sen. Sessions) (“The bill also
`
`includes many protections that were long sought by inventors and patent
`
`owners . . . . It imposes time limits on starting an inter partes or post-grant
`
`review when litigation is pending . . . . All of these reforms will help to
`
`ensure that post-grant review operates fairly and is not used for purposes of
`
`harassment or delay.” (emphasis added)).
`
`Thus, we conclude that there was no privity relationship between
`
`Synopsys and EVE sufficient to trigger § 315(b)’s prohibitions, and we
`
`decline to dismiss the inter partes review on this basis.
`
`2. Real Party-in-interest
`
`Mentor Graphics argues that this inter partes review is barred because
`
`EVE is a real party-in-interest to this inter partes review. PO Resp. 7-14.
`
`Mentor Graphics asserts that, therefore, the complaint served on EVE in the
`
`May 2006 case should trigger § 315(b). Id. at 6. Mentor Graphics admits
`
`that “on the date the petition for this [inter partes review] was filed,
`
`Synopsys had not yet acquired EVE and therefore had at best merely a
`
`prospective interest in the ZeBu products.” Id. at 9. Mentor Graphics,
`
`however, asserts that because Synopsys had a prospective interest in
`
`invalidating the ’376 patent when the petition was filed, “Synopsys was
`
`acting as an agent for the benefit of EVE.” Id. at 10. Thus, according to
`
`Mentor Graphics, at the time of filing, Synopsys was a third-party
`
`beneficiary for whose benefit the action was brought and, therefore, a real
`
`party-in-interest. Id. at 7-10.
`
`Mentor Graphics also contends that Synopsys allowed EVE to direct
`
`or control content of the petition for this inter partes review because
`
`Synopsys (1) specifically acquired EVE because of its expertise in the
`
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`technology field to which the ’376 patent is directed; (2) jointly asserted
`
`with EVE the same non-infringement and invalidity claims and defenses
`
`with respect to the ’376 patent, using the same counsel, in the jointly-filed
`
`declaratory judgment litigation; and (3) planned and coordinated the timing
`
`of the filing of the petition in this case and the declaratory judgment
`
`complaint with EVE. PO Resp. 12-13. Based on these contentions, Mentor
`
`Graphics asserts that Synopsys and EVE “conspired together to conceal
`
`EVE’s status as a ‘real party-in-interest’ to circumvent and thwart the
`
`statutory estoppel provisions.” Id. at 14.
`
`As discussed above, 37 C.F.R. § 42.101(b) makes clear that it is only
`
`relationships up until the time a petition is filed that matter. Mentor
`
`Graphics does not point to persuasive evidence to support its assertions that
`
`Synopsys allowed EVE to direct or control content of the petition filed in
`
`this case or any other evidence that EVE was a real party-in-interest prior to
`
`the filing of the petition. Although Mentor Graphics filed a Motion for
`
`Additional Discovery on the topic of real party-in-interest (Paper 21), this
`
`motion was denied because it did not articulate clearly why such discovery
`
`was “necessary in the interest of justice” as required by 35 U.S.C.
`
`§ 316(a)(5) (Paper 24). In fact, the entirety of Mentor Graphics’s
`
`explanation of why it needed additional discovery on the subject of real
`
`party-in-interest was the following:
`
`Thus, while the request interest of justice, [sic] as required by
`37 C.F.R. § 42.51(b)(2), in order to allow the Patent Owner an
`opportunity to show the applicability of a § 315(b) bar under
`the legal standard adopted by the Board. This includes the
`opportunity to show further (1) . . . (4) the status of EVE as a
`real party-in-interest to this IPR.
`
`Paper 21 at 2-3.
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`Thus, because Mentor Graphics has not supported sufficiently its
`
`assertions that EVE was a real party-in-interest at the time the petition in this
`
`case was filed, we decline to dismiss the inter partes review on this basis.
`
`B. Assignor Estoppel
`
`Mentor Graphics argues that Synopsys is barred from challenging the
`
`validity of the ’376 patent by assignor estoppel. PO Resp. 14-22. The
`
`Board has determined previously, and we agree, that assignor estoppel is not
`
`a basis for denying a petition requesting inter partes review:
`
`Under the AIA, “a person who is not the owner of a
`patent may file with the Office a petition to institute an inter
`partes review of the patent.” 35 U.S.C. § 311(a) (emphasis
`added). Consequently, under the statute, an assignor of a
`patent, who is no longer an owner of the patent at the time of
`filing, may file a petition requesting inter partes review. This
`statute presents a clear expression of Congress’s broad grant of
`the ability to challenge the patentability of patents through inter
`partes review.
`
`Athena Automation Ltd. v. Husky Injection Molding Sys. Ltd., IPR2013-
`
`00290, slip op. at 12-13 (PTAB Oct. 25, 2013), Paper No. 18; see also Palo
`
`Alto Networks, Inc. v. Juniper Networks, Inc., IPR2013-00369, slip op. at
`
`11-14 (PTAB Dec. 19, 2013), Paper No. 16.
`
`Mentor Graphics further asserts that even if Synopsys is not barred
`
`from requesting inter partes review, the Board should exercise its discretion
`
`to dismiss this inter partes review because of the relationship between Mr.
`
`Burgun and Synopsys.2 PO Resp. 16-19. Mentor Graphics further argues,
`
`
`2 This case does not require us to reach the issue of whether Mr. Burgun is in
`privity with Synopsys, as asserted by Mentor Graphics (PO Resp. 16-19),
`because we conclude that even if Mentor Graphics established such a
`relationship, Mentor Graphics has not shown a sufficient basis to bar
`
`16
`
`
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`
`more generally, that equitable considerations weigh against granting the
`
`petition, including that Synopsys is in privity with EVE and shares personnel
`
`with EVE, including Mr. Burgun. Id. at 19. Moreover, according to Mentor
`
`Graphics, “[i]t would be wholly against the principles of assignor estoppel to
`
`allow Synopsys to receive the benefit of the acquisition of EVE, but avoid
`
`EVE’s equitable obligations.” Id. at 22.
`
`We are not persuaded, however, that the equitable doctrine of assignor
`
`estoppel provides an exception to the statutory mandate that any person who
`
`is not the owner of a patent may file a petition for inter partes review.
`
`Accordingly, we decline to dismiss the inter partes review based on Mentor
`
`Graphics’s estoppel arguments.
`
`C. Claim Construction
`
`In an inter partes review, claim terms in an unexpired patent are
`
`interpreted according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 100(b); Office
`
`Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`
`Claim terms are also given their ordinary and customary meaning, as would
`
`be understood by one of ordinary skill in the art in the context of the entire
`
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`
`2007).
`
`If an inventor acts as his or her own lexicographer, the definition must
`
`be set forth in the specification with reasonable clarity, deliberateness, and
`
`precision. Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243,
`
`1249 (Fed. Cir. 1998). The construction that stays true to the claim language
`
`
`Synopsys from further participation in, or dismissal of, this inter partes
`review.
`
`17
`
`
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`
`and most naturally aligns with the inventor’s description is likely the correct
`
`interpretation. Id. at 1250.
`
`1. “Instrumentation Signal”
`
`Construction of the term “instrumentation signal,” required by each of
`
`the claims at issue in this proceeding, is central to the patentability
`
`determination. See PO Resp. 29-37; Reply 2-8. For example, claims 1 and
`
`28 recite “including at least one instrumentation signal, wherein the
`
`instrumentation signal is indicative of an execution status.” Claim 5, the
`
`third, and final, challenged independent claim, recites “creating an
`
`instrumentation signal associated with at least one synthesizable statement
`
`contained in a register transfer level (RTL) synthesizable source code.”
`
`a. Construction Adopted in the Decision to Institute
`
`Although neither the petition nor the preliminary response set forth a
`
`specific construction for “instrumentation signal,” the Board adopted, for
`
`purposes of the Decision to Institute, an interpretation that “the claimed
`
`instrumentation signal at least encompasses an output signal created during
`
`synthesis of RTL source code by inserting additional logic, preserved from
`
`the source code, that indicates whether the corresponding RTL source code
`
`statement is active.” Decision to Institute 10.
`
`Mentor Graphics argues that this construction is only partially correct.
`
`PO Resp. 30. Specifically, Mentor Graphics agrees that “instrumentation
`
`signals” encompass “inserting additional logic.” Id. According to Mentor
`
`Graphics, however, the requirement that the “additional logic is preserved
`
`from the source code” is contrary to how one of ordinary skill in the art
`
`would understand the term in light of the specification. Id. at 35 (citing Ex.
`
`2027 ¶¶ 38-39). Mentor Graphics points to language in the ’376 patent
`
`18
`
`
`
`Case IPR2012-00042
`Patent 6,240,376 B1
`
`specification stating that “[i]nstrumentation is the process of preserving
`
`high-level information through the synthesis process.” PO Resp. 35-36
`
`(quoting Ex. 1001, col. 5, ll. 3-4). Mentor Graphics’s expert, Dr. Majid
`
`Sarrafzadeh, states that preserving information here refers to permitting
`
`relation back from the execution of the gate level netlist to the corresponding
`
`statements in the RTL source code, not the preservation of logic itself from
`
`the source code. Ex. 2027 ¶ 40.
`
`We find this argument, along with the supporting evidence,
`
`persuasive. The language of the ’376 patent also supports this conclusion.
`
`For example, immediately following the language quoted above, the ’376
`
`specification states that “[i]nstrumentation permits simulation of a gatelevel
`
`netlist at the level of abstraction of RTL simulation by preserving some of
`
`the information available at the source code level through the synthesis
`
`process.” Ex. 1001, col. 5, ll. 4-8 (emphasis added).
`
`b. Definition of “Instrumentation”
`
`In proposing an alternative construction for “instrumentation signal,”
`
`Mentor Graphics initially asserts that the customary meaning of the term
`
`“instrumentation” to those of skill in the art is “additional code inserted into
`
`a program to monitor and/or collect information about the program behavior
`
`or operation during program execution.” PO Resp. 31. Dr. Sarrafzadeh
`
`testifies that this is how the term is “generally recognized and understood in
`
`the programming language arts.” Ex. 2027 ¶ 30 (citing IEEE Standard
`
`Glossary of Software Engineering Terminology, IEEE Std 610.12-1990 at
`
`41 (“Devices or instructions installed or inserted into hardware or software
`
`to monitor the operation of a system or component.”); National Bureau of
`
`Standards [NBS] Special Publication 500-75 Validation, Verification, and
`
`19
`
`
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`Case IPR2012-00042
`Patent 6,240,376 B1
`
`Testing of Computer Software at 48 (1981) (“The insertion of additional
`
`code into the program in order to collect information about program
`
`behavior during program execution.”)). We agree that this is the ordinary
`
`and customary meaning of the first word—“instrumentation”—of the term
`
`“instrumentation signal.”
`
`c. Specification
`
`Mentor Graphics further asserts that the term “instrumentation signal”
`
`requires that “the signal be provided by logic that is additional to the design
`
`logic resulting from the synthesis of the RTL source code.” PO Resp. 30. In
`
`other words, the instrumentation signal cannot be created solely by
`
`preserving circuit components.
`
`Synopsys argues that Mentor Graphics’s construction is too narrow
`
`and that the broadest reasonable construction of “instrumentation signal” is
`
`broad enough to include creation solely using preservation of circuit
`
`components. Reply 4-8.
`
`According to Mentor Graphics, one of ordinary skill would
`
`understand the following excerpts of the specification “to effectively define”
`
`“instrumentation signal” to require that i
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