` Trials@uspto.gov
`571-272-7822
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`Paper 59
`Date: December 27, 2013
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`SYNOPSYS, INC.
`Petitioner,
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`v.
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`MENTOR GRAPHICS CORPORATION
`Patent Owner.
`____________
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`Case No. IPR2012-00042
`Patent 6,240,376
`____________
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`Held: November 14, 2013
`____________
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`Before SALLY C. MEDLEY, HOWARD B. BLANKENSHIP, and
`JENNIFER S. BISK, Administrative Patent Judges.
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`APPEARANCES:
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`ON BEHALF OF THE PETITIONER:
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`WILLIAM H. WRIGHT, ESQUIRE
`
`
`TRAVIS M. JENSEN, ESQUIRE
`
`
`Orrick, Herrington & Sutcliffe, LLP
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`
`1000 Marsh Road
`Menlo Park, California 94025-1015
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`
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`
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`
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`Case Nos. IPR2012-00042
`Patent 6,240,376
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`
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`ON BEHALF OF THE PATENT OWNER:
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`MARK E. MILLER, ESQUIRE
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`O’Melveny & Myers, LLP
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`
`Two Embarcadero Center
`28th Floor
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`San Francisco, California 94111-3823
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`and
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`CHRISTOPHER L. McKEE, ESQUIRE
`MICHAEL S. CUVIELLO, ESQUIRE
`Banner & Witcoff, Ltd.
`1100 13th Street, N.W.
`Suite 1200
`Washington, D.C. 20005-4051
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`The above-entitled matter came on for hearing on Thursday,
`November 14, 2013, commencing at 2:00 p.m., at the U.S. Patent and
`Trademark Office, 600 Dulany Street, Alexandria, Virginia.
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`P R O C E E D I N G S
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`JUDGE MEDLEY: Good afternoon. Please be seated.
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`This is the hearing for IPR2012 -0042 between Petitioner
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`Synopsys and Patent Owner Mentor Graphics.
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`At this time we'd like the parties to introduce
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`themselves, starting with Petitioner.
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`MR. WRIGHT: Thank you, Your Honor. William
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`Wright of Orrick, Herrington & Sut cliffe on behalf of Petitioner
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`Synopsys. With me today is my colleague Travis Jensen and also
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`with me is David Pursley, Associate General Counsel for
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`Synopsys.
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`JUDGE MEDLEY: Thank you. And for Pat ent
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`Owner?
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`MR. McKEE: Good morning, Your Honors, or good
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`afternoon, Your Honors, Christopher McKee, lead counsel for
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`Mentor Graphics, and with me is backup counsel, Mark Miller
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`with O'Melveny & Myers who will be presenting the argument
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`today for Mentor Graphics, and also backup counsel, Michael
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`Cuviello with Banner & Witcoff, and we also have with us Tom
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`Evans, corporate counsel for Mentor Graphics.
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`JUDGE MEDLEY: Great. Thank you very much.
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`Okay. Per the order we sent out October 31st, you know that
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`each side has 60 minutes total time to present your arguments,
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`and we'd like the Petitioner to begin with its case with regard to
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`the challenge claims on which the Board instituted trial, and then
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`the Patent Owner can respond to the Petitioner's case and then at
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`that point we'd also l ike the Patent Owner to discuss their motion
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`to amend claims.
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`Then, Petitioner, you can take the rest of your time to
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`respond to all issues, and then, lastly, the Patent Owner, you can
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`respond, but only address the issues in connection with your
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`motion to amend.
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`So is that clear on how we're going to proceed?
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`MR. MILLER: Yes.
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`JUDGE MEDLEY: And also one other administrative
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`matter, when you're discussing your demonstratives so that we
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`can follow through the transcript, when we look back on the
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`transcript, if you could just refer to the slide number you're
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`discussing when you're up there, so then it will make sense in the
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`context of the transcript. That would be great, a big help for us.
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`Okay. So we'll begin with the Petitioner, and if you
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`could let us know how much time, rebuttal time, you'd like to
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`have.
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`MR. WRIGHT: Thank you, Your Honor. I would like
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`to reserve 15 minutes for rebuttal time. It may be 20 minutes,
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`but certainly reserve 15 minutes for rebuttal.
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`Your Honor, if I could, we have copies of the
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`materials that we'll be discussing. Could Mr. Jensen approach
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`and provide you those copies?
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`JUDGE MEDLEY: Yes, please. Thank you.
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`MR. WRIGHT: We have provided a copy of the
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`materials to the court report er and we'll provide copies to
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`counsel as well.
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`JUDGE MEDLEY: And we did receive both parties'
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`demonstratives in the record, so we appreciate that.
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`MR. WRIGHT: Good afternoon, Your Honor. If it
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`may please the Court, we'd like to discuss the Petition for Inter
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`Partes Review of U.S. Patent Number 6,240,376. Trial was
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`granted on Claims 1 through 9, 11, 28 and 29 over U.S. Patent
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`Number 6,132,109 to Gregory, et al. Gregory, et al. is a
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`Synopsys patent that predates the 376 Patent by -- at least by --
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`for filing date by several years.
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`The technology at issue here is related to what's
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`called EDA, design of integrated circuits using programming
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`language called HDL or RTL. It looks a great deal like a
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`computer language, but it is, instead, translated int o integrated
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`circuit designs.
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`The specific patents, the 376 Patent and the 109
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`Patent, are both directed to our debugging integrated circuits
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`relating the initial high -level design language or registered
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`transfer level design language to the circuitry wi thin a
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`simulation or emulation environment.
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`The Gregory Patent is directed to -- also towards
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`debugging. You can see debugging in its title. Debugging is
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`discussed throughout the background of the invention. And the
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`specific challenge that Gregory was addressing was the fact that
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`in optimizing HDL code to form an integrated circuit, you lose a
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`great deal of information, and it be confusing or difficult to track
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`circuitry back to the original text of the HDL language.
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`The Gregory 109 Patent introduces something it calls
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`probes to retain information about that original HDL textual
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`description of the design so that it's easier to understand the
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`debugging results that you get from simulation of the end
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`product, integrated circuit.
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`The 376 Patent comes s everal years later and has two
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`primary embodiments, one in which the designer inserts
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`additional language into the textual RTL description of the code,
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`specifically for tracking the relationship between the HDL and
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`the end circuit.
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`There's a second embod iment, which is important to
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`our discussion today, whereas the designer highlights a particular
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`RTL statement to be associated with an instrumentation signal, a
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`database keeps track of the association between the HDL text and
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`the instrumentation signal so that you have a database that tracks
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`everything, all the signals in the circuit so that that forms the
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`resource for being able to work backward and understand how a
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`debugging result relates to the original HDL textual description.
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`Mentor's --
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`JUDGE BISK: Can I stop you there and ask a little
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`bit more about the second embodiment?
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`MR. WRIGHT: Certainly.
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`JUDGE BISK: So how do they differ than in the next
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`phase of the -- I guess the next level down?
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`MR. WRIGHT: After the HDL is written, you go
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`through a synthesis process to produce what's called a netlist. A
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`netlist is a list of components and connections, relationships
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`between the components. The what we'll call a primary
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`embodiment of the 376 Patent, the added lines of RTL code are
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`synthesized, translated into a netlist description, along with the
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`rest of the circuit.
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`For the -- if we would, the pure database embodiment,
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`the database keeps track of what signals are created by the
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`synthesis from HDL code into the netlist. The database keeps
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`track of those instrumentation signals rather than having those
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`signals be newly created within the code in the circuit.
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`JUDGE BISK: So I'm a little -- so where is the
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`instrumentation signal, in the database?
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`MR. WRIGHT: The instrumentation signal is
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`something that's created in -- or it is part of the netlist. It's part
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`of the circuit design.
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`JUDGE BISK: Right.
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`MR. WRIGHT: It's a signal that you can track and
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`understand what is happening, and the instrumentation signal is
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`represented in the databas e and associated with the original HDL
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`text.
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`JUDGE BISK: Okay. So what is the exact -- do we
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`know the exact differences in the actual circuit than between
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`primary embodiment and secondary embodiment?
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`MR. WRIGHT: There may be no differences in the
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`circuit. There may be additional logic in the primary
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`embodiment. There may be different logic. Because you go
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`through an optimization process, you may optimize to a different
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`circuit when you have the additional lines of code.
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`So I'll show you an examp le where an aspect of the
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`circuit is completely the same and where it is changed as
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`opposed to the synthesis.
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`JUDGE BISK: Thank you.
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`MR. WRIGHT: Referring now to Slide 2, the petition
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`characterized the two embodiments and generally stating that the
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`instrumentation logic is added to or tracked within the RTL
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`source code description of a circuit, and that logic is synthesized
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`with a circuit description to provide a gate -level design
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`incorporating the instrumentation logic, so -- and I'll discuss in
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`some detail.
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`The embodiments either track within the database or
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`add information to the HDL code. So from the broadest
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`perspective, the concept of instrumentation signal is either
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`something that is added to the original HDL code or it's some
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`part of the HDL c ode that is kept intact and tracked through the
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`database.
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`The Board granted review as shown on page 3 and
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`construed four claim terms. Only one is relevant to our
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`discussion this afternoon and that's instrumentation signal. And
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`the Board stated, "we con clude that the broadest reasonable
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`interpretation of the claimed instrumentation signal at least
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`encompasses an output signal created during synthesis of RTL
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`source code by inserting additional logic, preserved from the
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`source code that indicates whether t he corresponding RTL source
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`code statement is active."
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`We'll discuss here that there's ample support for the
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`Board's construction of instrumentation signal. There's support
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`for an even broader interpretation where rather than speaking in
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`terms of inserting additional logic, the Board could have stated
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`inserting or tracking logic from the source code.
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`JUDGE BISK: Can I ask you a question? The Patent
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`Owner seems to be saying that there's an inconsistency internally
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`in this statement between inserting ad ditional logic and
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`preserved from the source code. So do you think that's
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`consistent or if tracking is missing from this statement, does
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`preserved from the source code not make sense?
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`MR. WRIGHT: There is certainly information
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`inserted into the source code regardless of the embodiment. You
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`are identifying a statement and associating that with an
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`instrumentation signal. In some cases that results in additional
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`logic and in some cases it doesn't.
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`The -- to some extent it depends on how broadly you
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`define logic, and we understand logic to have its broad
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`definition. I believe when Patent Owner is arguing that that's an
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`inconsistency, they're expecting that the term logic implies the
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`addition of logic gates where we'll show embodiments within the
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`376 Patent where the logic is the attachment of a wire so that you
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`can track a signal at a particular node.
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`So from a broad definition of logic, we view it as
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`consistent, and I believe Patent Owner's finding of inconsistency
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`is based on their particular definition of logic.
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`JUDGE BISK: Okay. Thank you.
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`MR. WRIGHT: Patent Owner's position I would say
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`reads out not only the alternate embodiment, but quite a bit of
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`the primary embodiment. You need to have a compass to figure
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`out what it is in the primary em bodiment that the Patent Owner
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`considers to be an instrumentation signal.
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`But if you take a look solely at the 376 Patent,
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`particularly we'll discuss Figure 10 and the SIG_TRACE1,
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`SIG_TRACE2, SIG_TRACE3 and SIG_TRACE4 instrumentation
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`signals. We'll see that you could have part of the patent defines
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`instrumentation signals as sometimes being associated with
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`additional logic gates and sometimes associated with preserving
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`a signal or allowing that signal to be observed from outside of
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`the circuit design.
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`On Slide 4 I've quoted a section of the 376 Patent that
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`discusses the alternate embodiment. This is in column 5, lines
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`31 to 45. I will not read it here, but, in part, it states that the
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`cross-reference database contains a cross -reference between
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`these instrumentation logic output signals, the instrumentation
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`signals, and the position of the corresponding statement in the
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`source code. So the database is doing a fairly simple job for a
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`database of keeping track of the signal name and its relationship
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`to other names within a source code.
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`Perhaps if the Board has some familiarity with
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`programming, in simple programming I know I was taught to
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`sometimes insert a statement that could easily be observed as
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`having been executed to make sure that my program or m y draft
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`program had proceeded through that part of the execution.
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`And so the 376 Patent is in many ways applying a
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`very basic programming technique to the creation of -- or the
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`design of integrated circuits.
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`JUDGE BISK: Is that -- the Patent Owner in those
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`claims have a couple other terms that they construe. I'm not sure
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`if they're construed as part of instrumentation signal or separate,
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`but they have active and I think one other one.
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`MR. WRIGHT: I believe it may be --
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`JUDGE BISK: Execution statu s.
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`MR. WRIGHT: Yes.
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`JUDGE BISK: Do you have any position on those? I
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`think your reply really talked about those. It seems kind of like
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`what you're talking about here.
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`MR. WRIGHT: I do believe that -- I don't honestly
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`recall their definition of act ive. I believe that their definition of
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`execution status specifically ignores the alternate embodiment
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`where the database is what is identifying a signal as being active.
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`So I don't recall the wording of their defi nition, but I
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`believe that their definition of execution status specifically
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`requires that you ignore the alternate embodiment, and I will
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`illustrate I believe whether you adopt Patent Owner's position of
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`the Board's stated interpretation or an even broader interpretation
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`as we believe is suppo rted by the plain language of the 376
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`specification, the Gregory Patent anticipates under any of those
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`constructions.
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`In the course of the trial, we had the opportunity to
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`depose Dr. Sarrafzadeh, Patent Owner's expert, and I think the
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`deposition is a strong indication of the extent that Patent O wner
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`has to reach for to obtain their construction.
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`On Slide 5 is an excerpt from Dr. Sarrafzadeh's
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`deposition discussing the alternate embodiment as it's included
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`in the summary of the invention of the 376 Paten t at column 2,
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`starting at line 66 and continuing into column 3. It talks about --
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`or the 376 Patent states, "With respect to source code analysis,
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`cross-reference instrumentation data, including the
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`instrumentation signals, can be used to count the numbe r of
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`times a corresponding statement is executed in the source code."
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`I think that that statement indicates how execution
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`status relates to the alternate embodiment. When questioned
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`about that, Dr. Sarrafzadeh dismissed the disclosure of the 376
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`Patent, saying it was just inadequate for him to understand what
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`was going on. His answer was, "You see, they don't show a
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`method for doing this, they just draw certain conclusions, and
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`without showing and describing these designs, I would not have
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`-- it would not be clear what they mean here."
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`That dismissal of the disclosure of the 376 Patent is
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`reflected again on Slide 6, where in discussing the alternate
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`embodiment Dr. Sarrafzadeh -- I referred Dr. Sarrafzadeh to a
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`particular paragraph within column 9 and, again, asked his
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`understanding, and he said, "I do understand what this paragraph
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`is saying. I'm saying it doesn't provide enough details for
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`somebody to build a system of this type."
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`On the right-hand side is the paragraph that I had
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`directed his atten tion to that is apparently the alternate
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`embodiment. It states in part, "In one embodiment, the
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`cross-reference file contains a mapping between original source
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`code line numbers and instrumentation signals. Each time an
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`instrumentation variable (and its associated signal) is added to
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`the source code, all the line numbers of the statements in the list
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`associated with the instrumentation variable are added to the file.
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`This cross-reference file (i.e., instrumentation data 238) can be
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`used by the gate-level simulation environment to convert the
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`designer's break-points into actual conditions on instrumentation
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`signals."
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`This is a paragraph that Dr. Sarrafzadeh said that he
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`found to have too little detail to understand or to build a system.
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`If you would continue with me to Slide 7, we see that
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`the concept of cross -reference instrumentation data mapping is
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`explicitly stated in Claim 9. I think this language tracks very
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`closely the paragraph of Claim 9 that I discuss with Dr.
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`Sarrafzadeh in his deposition. And Claim 9 clearly covers this
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`alternate embodiment, clearly is referring to a database with a
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`cross-reference mapping. Claim 9 depends from Claim 5.
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`And so by the principles of claim differentiation or
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`common sense, Claim 5 has to be considered broad enough to
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`encompass the alternate embodiment.
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`I asked Dr. Sarrafzadeh if there was anything about
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`the specification or the claims that allowed him to dismiss parts
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`of it, and with respect to Claim 1, as shown on Slide 8, he didn't
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`refer to the claim lang uage, instead he said you have to look at
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`all of the patent and come to a conclusion that Claim 1 is
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`limited, not only to the primary embodiment rejecting the
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`alternate embodiment. Claim 1 is limited to only certain aspects
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`for the primary embodiment, and that's because according to Dr.
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`Sarrafzadeh and the Patent Owner, the term instrumentation
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`signal has to do with adding logic.
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`And following up on that concept, I asked Dr.
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`Sarrafzadeh about the specific statement in the background of the
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`invention that talks about the gate-level netlist not being
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`modified for the alternate embodiment, and his answer, again, is
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`on Slide 10. I'm not clear what they are trying to do with this.
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`It's not described in detail.
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`Slide 11 shows a portion of the decision of th is Board
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`granting Inter Partes Review of certain claims of the 376 Patent.
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`This is a reference to Figure 9 of the 376 Patent and it illustrates
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`the methodology.
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`For the 376 Patent, the designer goes into the HDL
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`code and adds signals, TRACE1, TRACE2, TR ACE3, TRACE4,
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`and assigns those signal values within that HDL code to
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`SIG_TRACE1, SIG_TRACE2, SIG_TRACE3, SIG_TRACE4.
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`The Board correctly identified SIG_TRACE1,
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`SIG_TRACE2, SIG_TRACE3 and SIG_TRACE4 as
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`instrumentation signals. However -- and this is confirmed by the
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`text of the 376 Patent at Column 9, Lines 10 to 14, which states,
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`the instrumentation signals, SIG_TRACE1, SIG_TRACE2,
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`SIG_TRACE3 and SIG_TRACE4 are the result of combinatorial
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`logic only.
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`So the patent in plain English says the instrumenta tion
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`signals, this group of four instrumentation signals, are generated
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`in a particular way. Dr. Sarrafzadeh dismisses two of these
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`signals as not being instrumentation signals. He only finds
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`SIG_TRACE3 and SIG_TRACE4 to be instrumentation signals
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`and dismisses SIG_TRACE1 and SIG_TRACE2, and that is
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`because SIG_TRACE -- as you will see in Figure 10 and we'll
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`discuss this in the context of the infringement case, SIG
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`TRACE1 and SIG_TRACE2 do not add any logic. They simply
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`report what's going on inside of t he circuit. They're a tap from a
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`node, a wire going out somewhere that can be detected, and so
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`according to Patent Owner that is not an instrumentation signal
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`and according to the patent, column 9, lines 10 to 14, that is
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`indeed an instrumentation signal.
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`So it's our view that instrumentation signal is a
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`broader term than the Patent Owner has argued, and there is
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`ample support for the interpretation stated by the Board in its
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`decision to institute review.
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`As we've discussed today, we think there's even
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`broader support, but we don't need to reach that under any of
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`these constructions. The Gregory Patent anticipates the claims at
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`issue of the 109 Patent -- I'm sorry, of the 376 Patent.
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`JUDGE BISK: Now, what about under the Patent
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`Owner's construction, would Gregory anticipate?
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`MR. WRIGHT: Yes, we believe so and we'll
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`demonstrate that with specific reference to Figures 16 and 18 of
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`the Gregory 109 Patent.
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`Slide 15 shows directly from the petition a claim chart
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`with the first part of Claim 1, the pr eamble, and Step A of
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`identifying at least one statement within a registered transfer
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`level (RTL) synthesizable source code, and this is easily
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`illustrated in Figure 8 of the Gregory 109 Patent.
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`The Gregory 109 Patent uses figures of -- a design
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`stated in Figure 6 and represented in Figures 6 through 9. Also,
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`I believe 20 through 23 are about the same circuit, and it's a
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`basic example. It's elaborated on in other figures.
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`In fact, it's a particularly simple example, and I'll
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`explain why it was used and the pitfalls of that example in just a
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`bit. So Figure 8 shows the addition of a particular comment into
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`HDL source code. The Synopsys probe statement with the two
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`dashes beforehand to identify it as a comment, and the compiler
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`understands this language a s being special to keep -- and causes
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`this portion to be synthesized in a different way to retain the
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`original text so that it's more easily debugged.
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`Continuing on, on Slide 17, the Mentor -- I'm sorry,
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`the Patent Owner spends a great deal of time attac king the
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`embodiment shown in Figures 6 to 9, but it doesn't address the
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`language that was specifically cited in the claim chart of
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`Gregory, which states in describing the probe statement, that it
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`adds additional information or components to the initial cir cuit
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`that indicate that certain components should not be replaced
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`during optimization.
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`That language alone shows that Gregory is teaching
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`the addition of logic as needed to the initial circuit, the HDL
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`description, and I think rebuts their position on Greg ory not
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`teaching the addition of logic gates.
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`Continuing on, Slide 18 quotes more of Gregory that
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`is relevant to the infringement analysis. In the second paragraph
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`on Slide 18, there's a statement that really captures what Gregory
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`is about. "Any analytic result related to temporary input 203 or
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`temporary output 221 can be identified with the probe statement
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`401 in the HDL."
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`So the Gregory 109 Patent is teaching us to put
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`information or components into the HDL code so that we can
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`track any analytic res ult relating to that position within the
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`circuit. This is illustrated on Slide 19, which shows, again,
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`Figure 8, which is the HDL text with the addition of the
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`Synopsys probe statement, and Figure 9, which shows the
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`tempout and tempin signals that are cre ated there so that you can
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`sense what is going on at that node. You can keep track of that,
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`the analytic results related to that point in the circuit.
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`For comparison purposes, on Slide 20 we have Figure
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`10 of the 376 Patent. Figure 10 is generated from the Figure 9
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`code that the Board quoted in its decision to institute this review,
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`and it shows for you the signals, SIG_TRACE1, SIG_TRACE2,
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`SIG_TRACE3 and SIG TRACE4.
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`On the left I've include a section from the Sarrafzadeh
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`deposition in which Dr. Sarraf zadeh identifies only
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`SIG_TRACE3 and SIG_TRACE4 as being instrumentation
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`signals contradicting the findings of this Board and contradicting
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`Figure 10 of the 376 Patent and column 9, lines 10 to 14 of the
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`376 Patent, which identifies SIG_TRACE1 and SIG_TRAC E2 as
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`instrumentation signals.
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`As I said, much of Patent Owner's argument is an
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`attack on Figures 6 through 9 of the Gregory Patent, and the
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`Gregory Patent uses Figures 6 through 9 for specific purposes.
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`It's there to show you how much of a description can be
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`optimized away.
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`The HDL statement of Figure 6 is in Figure 8 we've
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`discussed already, and that's a snippet of code with three logic
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`gates and a multiplexor, as shown in Figure 6 on Slide 21. But if
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`you optimize a circuit, you get exactly what's s hown in Figure 7,
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`which is an inverter inverting the signal on point B.
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`It is an incredibly simple circuit for the purpose of
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`showing you how much change can occur when a circuit, such as
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`what's shown in Figure 6, is optimized. Figure 6 optimizes to
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`what's shown in Figure 7. In the portion of Dr. Sarrafzadeh's
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`deposition on Slide 21 he agrees.
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`The Patent Owner will then argue that there's no real
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`difference in the Figure 9 representation of the Gregory 109
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`circuit, because the tempout and the tempin a re connected at
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`some different level and you don't add any logic to the circuit,
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`and they'll attack it as not showing an execution status, because,
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`in fact, that point in the circuit is never executed.
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`But this is because Gregory used this particular
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`degenerate result or degenerate circuit example to show you how
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`simple and how much information you can lose when going from
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`the Figure 8/Figure 6 description of the circuit to the optimized
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`Figure 7 description.
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`Figure 9 and tempout accurately reports that that
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`portion of the circuit is never exercised. It's a meaningless,
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`perhaps a programming mistake, perhaps a young designer that
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`didn't think through the design or simply the reflection that
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`designs are complex and sometimes signals that you think are
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`important simply aren't.
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`So we've illustrated that Claim 1 is anticipated by
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`Gregory and we pointed to language that says that Gregory
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`teaches us to add information or components to the original code
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`so that we can monitor analytic results to debug the cir cuit.
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`Claim 2 is on Slide 23, and it's simply giving the
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`specific analog of the information being available as if it were an
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`assignment statement, that is, as if some value were being
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`assigned to a signal or variable, and so it really is an analogy and
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`what we've discussed is fully operable.
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`Let me in the interest of using my time efficiently, let
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`me discuss Claim 5 briefly and then Claim 28 so that we cover
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`the independent claims. Claim 5 is very similar to Claim 1.
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`JUDGE BISK: Actually could I have you instead talk
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`about the Patent Owner's claim construction and how you think
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`Gregory would anticipate under those?
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`MR. WRIGHT: Then let me proceed to Claim 28 and
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`deal with execution status in the context of Figures 16 and 18.
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`JUDGE BISK: Thank you.
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`MR. WRIGHT: And the presentation materials
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`discuss Claim 28 starting at Slide 38 and on Slide 39 references
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`the Figure 16, VHDL source code of the Gregory 109 Patent that
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`is synthesized to what is shown in Figure 18 using what Gregory
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`calls the block pro be, and the block probe just sets an initial
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`bound and ending bound and causes all of those signals within
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`them to be preserved by the Synopsys probe statement.
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`And this discussion is repeated elsewhere, but let me
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`proceed to the example at -- of Claim 29 on Slide 41, which
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`shows the excerpt from the Figure 16, the HDL description with
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`the Synopsys block probe capturing a process and all of the
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`different cases for a status check or for a controller, and that
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`produces the circuit that's shown on Slide 42, and it can either --
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`that particular statement produces the circuits shown on Slide 42
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`as Figure 18.
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`If you don't have the Synopsys block probe structure,
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`the circuit that's produced is in Figure 14, also on Slide 42. And
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`so you can compare the optimize d synthesized version of the
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`code in Figure 14 with the code that results in Figure 18, and you
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`can see counting up the gates you have at least two more gates in
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`Figure 18 than you do in Figure 14.
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`So to preserve the signals that are demanded by the
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`Synopsys block probe statement, you have to add a couple more
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`gates so that you can keep track of and reproduce the signals in
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`the finished circuit. So I've circled two of the NAND gates, both
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`are indicated as ND2, so it's less useful because there's three
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`ND2 NAND gates in Figure 18, but you can compare.
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`There's at least one other gate that is different
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`between Figure 14 and Figure 18, but clearly the two NAND
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`gates that are circled on Slide 42 are additional logic, and so
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`under -- and this is showing instr umentation signal and execution
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`status as those terms are used in Claim 28 and illustrates that
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`Gregory, indeed, no