UNIFIED PATENTSUNIFIED PATENTS
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`UNIFIED PATENTS
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`EXHIBIT 1005
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`EXHIBIT 1005EXHIBIT 1005
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`UNIFIED PATENTS EXHIBIT 1005
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`

`
`(12) Ulllted States Patent
`Schneider
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,594,275 B1
`Jul. 15, 2003
`
`US006594275B1
`
`(54) FIBRE CHANNEL HOST BUS ADAPTER
`
`BUFFER FOR REDUCED POWER
`
`7/1997 Widmer .................... .. 341/100
`5,648,776 A *
`4/2000 Carr et al.
`341/100
`6,052,073 A *
`
`6,128,681 A * 10/2000 Shephard . . . . .
`. . . . .. 710/71
`1/2001 Ryan ........................ .. 341/101
`6,169,501 B1 *
`
`(75)
`
`Inventor: Thomas R. Schneider, Anaheim, CA
`(US)
`
`* Cited by examiner
`
`(73) Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. N0.: 09/160,920
`(22)
`Filed:
`S81). 25, 1993
`
`Reiared U-S- APPiiC3ri0i1 Dara
`
`(63) C°iiiiiiiiaii°ii‘iii‘Pari Or aPPii°aii°ri N°- 09/055497» died 0“
`Apr‘ 3’ 1998'
`Int. Cl.7 ................................................. .. H04J 3/16
`(51)
`(52) U.s. Cl.
`...................... .. 370/465; 370/503, 370/537
`(58) Field of Search ............................... .. 370/537, 539,
`370/465, 466, 467, 366, 503, 506, 508,
`509’ 510’ 513’ 532; 341/100’ 101
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`Primary Examiner—Alpus H. Hsu
`Assistant Examiner—Thien Tran
`
`(74) Attorney, Agent, or Firm—Robert D. Marshall, Jr.; W.
`James Brady’ HI; Frederick J’ Telecky’ Jr’
`(57)
`ABSTRACT
`
`A Fiber Channel host bus adapter has a low power, high
`spleed serial tol pdiarallel dalta ionlvertedr ffor coéivertinlg f_:1y1:_
`c ronous seria
`a a in o c oc a igne ,
`rame , para e
`a a
`utilizing a serial in, parallel out register for receiving asyn-
`chronous serial data and for providing unframed parallel
`data. An array of parallel in, parallel out registers is config-
`ured to receive parallel data from the serial in, parallel out
`data register and move the data in a parallel fashion between
`the parallel
`in, parallel out registers thereof. A pattern
`detection circuit identifies a location of a delimiter character
`Within the array of a parallel in, parallel out registers. A
`Seieeiieri eireiiii reads desired daia bits rrerri the array or
`parallel in, parallel out registers in a parallel fashion, based
`upon the location of the delimiter character, to define a
`framed parallel output Word. A data alignment circuit aligns
`the framed parallel output Word with respect to a clock to
`define a clock aligned, framed parallel output Word.
`
`4,157,458 A *
`
`6/1979 Roche .................... .. 179/15 A
`
`26 Claims, 4 Drawing Sheets
`
`30
`
`I00
`
`
`
`
`:0
`FT1 —k
`3 3
`H :1
`3’
`
`10 BIT
`
`PARALLEL
`OUTPUT
`WORD
`(100 MHZ)
`
`
`
`|
`_______ _ _ J SIGNALS I
`
`CLOCK
`
`i G"'Z
`CLOCK
`500 MHZ
`CLOCK
`
`PATTERN
`DETECTION
`AND wonn
`ALIGNMENT
`
`ALIGN BY 5ns
`
`
`PATTERN
`DETECTED
`
`100 MHZ
`RBCI
`
`.______°E°"_‘5_°M_“Z’_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___I
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 2
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`ASYNCHFIONOUS
`SERIAL
`DATA 1 GHZ
`500 MHZ CLOCK
`32
`-1
`
`E”.
`
`‘I
`I
`
`I‘ ' '
`I
`
`
`
`F '
`I
`
`IIIII
`
`I
`I
`I
`:
`I
`|
`L
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 2
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`

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`U.S. Patent
`
`Jul. 15, 2003
`
`Sheet 1 014
`
`US 6,594,275 B1
`
`INPUT
`
`20
`
`OUTPUTS
`
`18
`FIBRE CHANNEL RECEIVER
`BLOCK (DIGITAL)
`
` I PARALLEL
`
`,
`1
`DATA
`
`.100 MHz
`1
`[100 MHz CLOCK
`
`
`1 GHz
`
`.
`1 GHz CLOCK
`L ________________________ _ _ .1
`
`FIG. I
`(PRIOR ARI)
`
`TIME ->
`
`LSB1
`MSB1
`1
`I
`17C
`I
`053
`I
`I
`
`O10111010:0O1‘I111010:1100101000:101100101O
`LAST WORD
`'
`COMMA
`'
`FIRST WORD
`'
`SECOND WORD
`
`FIG. 4
`
`
`
`CASE 1 -44,]
`
`CASE 2
`
`CASE 3
`
`CASE 4
` FIG. 5
`
`CASE 5
`
`UNIFIED PATENTS EXHIBIT 1005
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`UNIFIED PATENTS EXHIBIT 1005
`PAGE 3
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`

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`U.S. Patent
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`Jul. 15, 2003
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`Sheet 2 of4
`
`US 6,594,275 B1
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`n__._u_oca
`
`><$_<ma:n__._u_mxv
`
`
`
`
`
`><E<n_o._u_
`
`530N_.__>_2:
`
`UNIFIED PATENTS EXHIBIT 1005
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`UNIFIED PATENTS EXHIBIT 1005
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`

`
`U.S. Patent
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`Jul. 15,2003
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`US 6,594,275 B1
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`“W
`
`9L
`
`L.
`
`||I'I||I‘I|I|||IIIINI'||IIIIIJ_|0350.5__uuuuuuuuuuuuuuuI:mN15.2:__.._580__N_._s_2:A__:,m_>_zw:<9%.,__"Q>Zz<___Ban04__BBEQasEzw:<ZEEE__M__ZEEE__MEs.82_1nnnnIn_M2,___Sno__dj<m<n___TRE2E+1_E0mE._S_
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`U
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`IED PATENTS EXHIBIT 1005
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`____
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`UNIFIED PATENTS EXHIBIT 1005
`PAGE 5
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`

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`U.S. Patent
`
`Jul. 15, 2003
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`Sheet 4 of4
`
`US 6,594,275 B1
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`10ns
`10ns
`
`
`Po< (9:0)
`
`17C
`
`053 -
`
`RBC1 (50 MHz) 1
`
`RBCO (50 MHZ) :
`
`COMMA |_:_j_
`DETECTED
`
`FIG. 6
`
`104
`
`I" """"""" ' ' 1/"""""" "' "I
`I
`'
`
`
`
`I
`PARALLEL
`I
`I
`TO SERIAL
`'
`:
`CONVERTER
`.
`:
`I
`I
`I
`
`FIBRE CHANNEL
`PROTOCOL
`CONTROLLER
`
`
`
`1 GHZ
`DATA our
`
`1 GHZ
`DATA IN
`
`
`
`
`
`
`10
`
`
`
`
`Z
`
`
`I
`SERIAL TO
`CQMPUTER I
`I
`PARALLEL
`:
`
`I
`— CONVERTER
`I
`100
`I
`I
`—
`I
`|
`I
`I
`I
`|
`I
`|
`I
`|
`
`I
`|
`I. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._ _ _I
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 6
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`UNIFIED PATENTS EXHIBIT 1005
`PAGE 6
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`

`
`US 6,594,275 B1
`
`1
`FIBRE CHANNEL HOST BUS ADAPTER
`HAVING MULTI-FREQUENCY CLOCK
`BUFFER FOR REDUCED POWER
`CONSUMPTION
`
`RELATED APPLICATIONS
`
`This patent application is a continuation-in-part of U.S.
`Ser. No. 09/055,197, filed on Apr. 3, 1998, and entitled
`SERIAL/PARALLEL GHz TRANSCEIVER WITH
`PSEUDO-RANDOM BUILT IN SELF TEST PATTERN
`
`the entire contents of which are hereby
`GENERATOR,
`incorporated by reference.
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to high speed data
`transmission and conversion systems. The present invention
`relates more particularly to a Fibre Channel host bus adapter
`having a multi-frequency clock buffer which facilitates
`conversion of asynchronous serial data into clock aligned,
`framed, parallel data in a manner which reduces power
`consumption by driving selected portions of a serial
`to
`parallel data converter at reduced clock speeds.
`
`BACKGROUND OF THE INVENTION
`
`High speed data transmission systems for communicating
`data between a computer and its associated peripherals, as
`well as between computers themselves, are well known. One
`example of such a high speed data communication system is
`Fibre Channel, which provides data transmission rates up to
`approximately 1 GHz when used with an optical fibre or
`coaxial cable transmission medium. When an optical fibre
`transmission medium is used, a Fibre Channel data trans-
`mission system can transmit data at such speeds even when
`the sender and receiver are separated by relatively great
`distances.
`
`Data is transmitted over the optical fibre of a Fibre
`Channel system according to an asynchronous serial data
`transmission protocol. However, as those skilled in the art
`will appreciate, the internal architecture of contemporary
`computers is based upon parallel, byte-multiple signal buses
`(typically 8-bit, 16-bit or 32-bit buses). Thus, it is necessary
`to convert between the asynchronous serial data used for
`Fibre Channel communications and the parallel data used
`internally by the computer.
`In a Fibre Channel system, byte-multiple parallel data
`must be converted by the transmitter into a 1 GHz asyn-
`chronous serial data signal for transmission along an optical
`fibre or coaxial cable and must be converted by the receiver
`from 1 GHz asynchronous serial data back into byte-
`multiple parallel data for internal use by a computer or
`peripheral.
`In accordance with the Fibre Channel physical and sig-
`naling interface specification, defined in ANSI X3.230-
`1994, information to be transmitted over an optical fibre or
`wire cable is encoded, 8-bits at a time, into a 10-bit Trans-
`mission Character which is subsequently serially transmitted
`by bit. The data provided over a typical computer system
`parallel architecture is encoded and framed such that each
`data byte (8-bits from the point of view of the computer
`system) is formed into a Transmission Character in accor-
`dance with the Fibre Channel 8B/10B Transmission Code.
`The resulting 8B/10B Character is then transmitted as 10
`sequential bits at approximately a 1 GHz data rate in
`accordance with the interface specification. Likewise, an
`incoming 8B/10B encoded Transmission Character must be
`
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`serially received at an approximately 1 GHz data rate and
`converted (framed) into the corresponding 10-bit Transmis-
`sion Character. The 10-bit Transmission Character is then
`
`further decoded into an 8-bit byte which is recognizable by
`such conventional computer architectures.
`According to contemporary methodology, the conversion
`of high speed, e.g., 1 GHz, asynchronous serial data into
`byte-multiple data suitable for internal processing by a
`contemporary computer is performed by receiving the asyn-
`chronous serial data into a deserializer which comprises a
`serial in, parallel out shift register. The serial in, parallel out
`shift register is typically large enough-to capture an entire
`byte-multiple word of data, so as to facilitate the detection
`of a delimiter character, i.e., a character such as a comma
`which facilitates the proper framing of the data as byte-
`multiple parallel data words. The serial in, parallel out shift
`register must also be large enough to accommodate the
`byte-multiple data words themselves (which are typically of
`the same length as the delimiter character).
`A pattern detection circuit facilitates identification and
`location of the delimiter character within the serial
`in,
`parallel out shift register and a word alignment circuit effects
`alignment of the framed delimiter and subsequent data
`words to a desired clock signal, e.g., a 100 MHz clock.
`However, one problem commonly associated with such
`contemporary, high speed, serial to parallel data converters
`is the undesirably high power consumption associated there-
`with. Atypical contemporary serial to parallel data converter
`suitable for converting approximately 1 GHz asynchronous
`serial data into 10-bit, 100 MHz parallel data comprises
`approximately 50 flip flops, of which approximately 40 are
`clocked at 1 GHz. Of course, each of these flip flops
`consumes electrical power and also contributes to the heat
`load of any integrated circuit of which it forms a part.
`Further, the clock driver required to drive the flip flops has
`to provide sufficient power to accommodate the fanout
`associated therewith.
`
`The power consumption of such a contemporary, high
`speed, serial to parallel data converter is higher than desired
`because many of the flip flops thereof must be clocked at 1
`GHz, thereby undesirably increasing power consumption, as
`discussed further below. One contemporary high speed
`serial to parallel data converter which utilizes fully synchro-
`nous design techniques is known to have a worst case power
`consumption of approximately 500 mW.
`the heat
`As those skilled in the art will appreciate,
`dissipation of a circuit is directly proportional to the power
`consumed thereby. When a circuit is embodied in an inte-
`grated circuit chip,
`then it
`is particularly important
`to
`mitigate the heat dissipation thereof, so as to minimize the
`circuit’s contribution to the total heat load of the integrated
`circuit chip. The total heat loading of an integrated circuit
`must be maintained below a predetermined level so that the
`heat can be extracted from the integrated circuit chip (such
`as by using a heat sink, fan, or thermoelectric cooler, if
`necessary). If the heat generated by an integrated circuit chip
`cannot be removed therefrom fast enough, then the tempera-
`ture of the integrated circuit chip increases and the inte-
`grated circuit chip is subject to malfunction and/or prema-
`ture failure. Since every individual circuit of an integrated
`chip contributes to the heat loading thereof, it is desirable to
`minimize the heat
`load contribution of each individual
`
`circuit, so as to reduce the heat
`integrated circuit chip.
`It is well known that the power consumption of a circuit
`is directly proportional to the frequency at which the flip
`
`loading of the entire
`
`UNIFIED PATENTS EXHIBIT 1005
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`UNIFIED PATENTS EXHIBIT 1005
`PAGE 7
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`

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`US 6,594,275 B1
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`3
`flops thereof operate, according to the formula: power=
`capacitance><frequency><voltage2. Thus, it is clear that reduc-
`ing the frequency, i.e., clock rate, of selected flip flops by
`half reduces the power required to operate the selected flip
`flops by half as well.
`In view of the foregoing, it is desirable to provide a serial
`to parallel data converter which operates with a substantial
`number of the flip flops thereof being clocked at a reduced
`rate, so as to mitigate power consumption and heat dissipa-
`tion thereof.
`
`SUMMARY OF THE INVENTION
`
`The present invention specifically addresses and allevi-
`ates the above-mentioned deficiencies associated with the
`
`prior art by providing a serial to parallel data converter
`which has reduced power requirements. Reduced power
`consumption is facilitated by the use of an array of parallel
`registers for pattern detection which are clocked at a lower
`rate than the serial register of contemporary serial to parallel
`converters and therefore consume substantially less power
`than the contemporary serial register.
`More particularly, the present invention comprises a Fibre
`Channel host bus adapter having a low power, high speed,
`serial to parallel data converter for converting asynchronous
`serial data into clock aligned, framed, parallel data. The data
`converter of the present invention comprises a serial in,
`parallel out register for receiving asynchronous serial data
`and for providing unframed parallel data. An array of
`parallel in, parallel out registers is configured to receive the
`unframed parallel data from the serial in, parallel out register
`and to move the received data in a parallel fashion between
`the parallel in, parallel out registers of the array.
`A pattern detection circuit identifies the location of a
`delimiter character, e.g., a comma, within the array of
`parallel in, parallel out registers. A selection circuit reads
`desired data bits from the array of parallel in, parallel out
`registers in a parallel fashion, based upon the location of the
`delimiter character, so as to define a framed parallel output
`word containing either the delimiter character or a subse-
`quent data word. A data alignment circuit aligns the framed
`parallel output word with respect to a desired clock, so as to
`define a clock aligned, framed parallel output word. Some
`data alignment may optionally be performed by the selection
`circuit, as well.
`According to the present invention, the number of flip
`flops which are clocked at 1 GHZ is substantially reduced as
`compared to contemporary high speed serial to parallel data
`converters. Reducing the speed at which the flip flops are
`clocked proportionally reduces the power consumption and
`heat dissipation thereof. The data converter of the present
`invention further comprises a multi-frequency clock. The
`multi-frequency clock comprises a first clock output port for
`providing a first clock signal to the serial in, parallel out
`register. The multi-frequency clock further comprises a
`second clock output port for providing a second clock signal
`to the array of parallel in, parallel out registers and to the
`detection circuit. The multi-frequency clock further com-
`prises a third clock output port for providing a third clock
`signal to the data alignment circuit. The rate of the first clock
`signal is greater than the rate of the second clock signal and
`the rate of the second clock signal is greater than the rate of
`the third clock signal.
`As those skilled in the art will appreciate, a 1 GHZ clock
`signal is necessary to facilitate operation of the serial in,
`parallel out register when receiving asynchronous serial data
`at a rate of 1 GHZ. However, since the serial in, parallel out
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`register provides parallel data output at one fifth of the rate
`at which asynchronous serial data is input thereto, the array
`of parallel in, parallel out registers can be clocked at a rate
`lower than 1 GHZ, e.g., 500 MHZ. The final output of the
`serial to parallel data converter of the present invention is at
`100 MHZ, thus facilitating operation of the data alignment
`circuit at 100 MHZ.
`
`invention, a progression of
`According to the present
`slower clock signals is provided from the input of the serial
`to parallel data converter to the output
`thereof.
`In this
`manner, the frequency of selected portions of the serial to
`parallel converter is substantially reduced, thereby providing
`a corresponding reduction in power consumption and heat
`dissipation of the selected portions of the circuit. The use of
`the array of parallel in, parallel out registers (as opposed to
`the serial register used in contemporary devices) for pattern
`detection and data selection facilitates such reduced clock
`rates.
`
`Thus, according to the preferred embodiment of the
`present
`invention,
`the first clock signal comprises an
`approximately 1 GHZ clock signal for facilitating reception
`of asynchronous data by the serial in, parallel out register at
`approximately 1 GHZ; the second clock signal comprises an
`approximately 500 MHZ clock signal for facilitating iden-
`tification of the delimiter character as data moves through
`the array of parallel in, parallel out registers; and the third
`clock signal comprises an approximately 100 MHZ clock
`signal for facilitating generation of 10-bit, clock aligned,
`framed parallel output words at approximately 100 MHZ.
`The multi-frequency clock preferably further comprises a
`clock recovery circuit for facilitating generation of the first,
`second, and third clock signals from the asynchronous serial
`data. The clock recovery circuit preferably comprises a
`phase lock loop clock recovery circuit which generates or
`regenerates an asynchronous timing reference signal from a
`serial data stream and provides a timing reference to mark in
`time the anticipated occurrence of serial data bits. In effect,
`the phase-lock loop generates a synchronous stream of
`successive timing references, each timing reference
`representing, for example, a bit period with which a data bit
`may be associated.
`According to the preferred embodiment of the present
`invention, the serial in, parallel out register has a smaller bit
`siZe than the bit siZe of the clock aligned, framed parallel
`output word. Preferably, the serial in, parallel out register
`comprises a 5-bit register and the framed output word
`comprises a 10-bit output word.
`The serial in, parallel out register preferably comprises a
`serial in, parallel out shift register and the array of parallel
`in, parallel out register preferably comprise an array of
`parallel in, parallel out shift registers. The array of parallel
`in, parallel out shift registers preferably comprise four 5-bit
`parallel in, parallel out shift registers and a single 1-bit
`register.
`The pattern detection circuit is preferably configured to
`detect a 10-bit delimiter word. More particularly, the pattern
`detection circuit is preferably configured to detect a 7-bit
`delimiter character contained within a 10-bit word which
`also contains 3 don’t care bits.
`
`Because the location of the starting bit of the delimiter
`character is unknown when the delimiter character is
`
`is
`it
`in, parallel out register,
`received within the serial
`necessary to locate the delimiter character as the delimiter
`character progresses through the array of parallel in, parallel
`out registers. Since a 5-bit serial in, parallel out register is
`utiliZed according to the preferred embodiment of the
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 8
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`UNIFIED PATENTS EXHIBIT 1005
`PAGE 8
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`

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`US 6,594,275 B1
`
`5
`present invention, the delimiter character may be located at
`one of five different starting positions within the array of
`parallel in, parallel out registers. Thus, the pattern detection
`circuit is configured to detect the delimiter character when
`the delimiter character is located at one of the five different
`
`starting positions within the array of parallel in, parallel out
`registers.
`According to the preferred embodiment of the present
`invention,
`the selection circuit comprises a plurality of
`multiplexers configured to select a desired sequence of bits
`from within the array of parallel in, parallel out registers and
`to provide an output representative of the selected bits. The
`selection circuit preferably comprises a first multiplexer
`array configured to select one of two different sequences of
`bits within the array of parallel in, parallel out registers, so
`as to provide a first selection which comprises the delimiter
`character as well as some superfluous bits. The selection
`circuit also comprises a second multiplexer array configured
`to select a desired sequence of bits from within the first
`selection so as to provide a second selection. The second
`selection defines the framed parallel output word.
`According to the preferred embodiment of the present
`invention, the selection circuit comprises fourteen 2:1 mul-
`tiplexers configured to select one of two different sequences
`of 14 bits within the array of parallel in, parallel out registers
`to provide a 14-bit first selection and comprises ten 5:1
`multiplexers configured to select one of five different
`sequences of 10-bits within the first selection so as to
`provide a 10-bit second selection which defines the framed
`parallel output word.
`Since the desired 10-bit word is moving through the array
`of parallel in, parallel out registers, it will pass through both
`of the 14-bit sequences of registers which potentially com-
`prises the first selection. The two 14-bit selections are 5
`nanoseconds apart within the array. Thus,
`the 14-bit
`sequence selected is that sequence which enhances align-
`ment of the desired 10-bit data word with the desired clock
`
`signal.
`According to the preferred embodiment of the present
`invention,
`the data alignment circuit comprises a delay
`register for receiving the framed parallel output word from
`the selection circuit and an output multiplexer for selecting
`the framed parallel output word from either the selection
`circuit or the delay register. The output multiplexer selects
`the framed parallel output word which enhances alignment
`of the framed parallel output word with a desired clock
`signal. Thus,
`the output multiplexer selects the framed
`parallel output word directly from the selection circuit if no
`delay is needed to enhance alignment of the framed parallel
`output word with the desired clock signal. The output
`multiplexer selects the framed output word from the delay
`register if the delay provided thereby enhances alignment of
`the framed parallel output word with the desired clock
`signal. The output multiplexer provides a substantially clock
`aligned, framed, parallel output word.
`According to the preferred embodiment of the present
`invention,
`the data alignment circuit comprises a 10-bit
`parallel
`in, parallel out delay register for receiving the
`framed, parallel output word from the selection circuit and
`ten 2:1 output multiplexers for selecting the framed parallel
`output word from either the selection circuit or the delay
`register. The ten 2:1 output multiplexers select the frame
`parallel output word in a manner which further enhances
`alignment of the framed parallel output word with the
`desired clock signal. A ten nanosecond timing difference is
`provided between the output of the ten 2:1 multiplexers and
`
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`the ten 2:1 output multiplexers
`the delay register. Thus,
`provide a substantially clock aligned, framed parallel output
`word.
`
`An output register receives the course clock aligned,
`framed parallel output word from the output multiplexer.
`The output register further aligns the substantially clock
`aligned, framed parallel output word to the desired clock
`signal so as to provide a clock aligned, framed parallel
`output word. According to the preferred embodiment of the
`present invention,
`the output register comprises a 10-bit
`output register.
`Thus, the present invention provides a high speed serial to
`parallel data converter suitable for use in a Fibre Channel
`receiver. The serial to parallel converter uses less power than
`contemporary serial to parallel data converters and is thus
`more suitable than contemporary serial
`to parallel data
`converters for implementation as an integrated circuit.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other features, aspects and advantages of the
`present invention will be more fully understood when con-
`sidered with respect to the following detailed description,
`appended claims and accompanying drawings, wherein:
`FIG. 1 is a block diagram showing a prior art Fibre
`Channel serial to parallel data converter;
`FIG. 2 is a block diagram of a serial to parallel data
`converter according to the present invention;
`FIG. 3 is a block diagram showing the serial to parallel
`data converter of FIG. 2 in further detail;
`FIG. 4 shows an exemplary asynchronous serial data
`stream which includes a delimiter character, i.e., a comma,
`and two 10-bit data words;
`FIG. 5 shows the five possible cases for the location of a
`7-bit delimiter character within the array of parallel
`in,
`parallel out registers of FIGS. 2 and 3;
`FIG. 6 is a timing diagram showing the phase relationship
`of the received asynchronous serial data,
`the 100 MHZ
`clock, i.e., RBC1 and RBCO, and the COMMA DETECTED
`signal; and
`FIG. 7 is a block diagram of a Fibre Channel host bus
`adapter having a serial to parallel converter according to the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`The detailed description set forth below in connection
`with the appended drawings is intended as a description of
`the presently preferred embodiment of the invention, and is
`not intended to represent the only form in which the present
`invention may be constructed or utilized. The detailed
`description sets forth the construction and functions of the
`invention, as well as the sequence of steps for operating the
`invention in connection with the illustrated embodiment. It
`
`is to be understood, however, that the same or equivalent
`functions may be accomplished by different embodiments
`which are also intended to be encompassed within the spirit
`and scope of the invention.
`Prior to describing a presently preferred embodiment of
`the serial to parallel data converter of the present invention,
`it may be beneficial to provide a description of a prior art
`serial
`to parallel data converter. The prior art serial
`to
`parallel data converter described below contains approxi-
`mately 50 flip flops (approximately 40 of which are clocked
`at 1 GHZ) and consumes, in the worst case, approximately
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 9
`
`UNIFIED PATENTS EXHIBIT 1005
`PAGE 9
`
`

`
`US 6,594,275 B1
`
`7
`500 mW. As discussed above, the consumption of such a
`comparatively high amount of electrical power has serious
`disadvantages associated therewith. Not only are the overall
`power requirements of the system increased undesirably, but
`also the clock buffer must accommodate the fan out required
`by the comparatively large number of flip flops which
`operate at high clock speeds. Further, the heat generated by
`such a prior art circuit is undesirably excessive.
`Referring now to FIG. 1, an exemplary serial to parallel
`data converter is embodied as Fibre Channel receiver block
`20. An asynchronous 1 GHZ signal is provided to both phase
`lock loop 10 and deserialiZer and comma detect circuit 12.
`The deserialiZer and comma detect circuit 12 provides 10-bit
`parallel data to word alignment circuit 18 which, in turn,
`provides 10-bit parallel data at 100 MHZ as an output for the
`Fibre Channel receiver block 20.
`
`The phase lock loop 10 provides a clock output at 1 GHZ
`to clock buffer 14, which provides a 1 GHZ clock drive
`signal to the deserialiZer and comma detect circuit 12 and to
`the clock generator 16. The clock generator provides a 100
`MHZ clock signal to the word alignment circuit 18.
`In operation, the phase lock loop 10 provides a 1 GHZ
`clock output which is recovered from the 1 GHZ asynchro-
`nous serial data signal provided thereto, according to well
`known principles. The clock buffer 14 provides clock output
`drive signals to the deserialiZer and comma detect circuit 12
`and to the clock generator 16. The deserialiZer and comma
`detect circuit 12 operates at 1 GHZ. According to contem-
`porary practice, the deserialiZer and comma detect circuit 12
`comprises a serial register (rather than an array of parallel
`registers as in the present invention). That is, all the circuitry
`necessary to convert
`the asynchronous serial data input
`signal into a parallel signal and to detect the delimiter therein
`is clocked at 1 GHZ according to contemporary practice.
`The clock generator 16 generates a 100 MHZ clock signal
`from the 1 GHZ clock provided thereto. The clock generator
`16 then provides the 100 MHZ clock signal to word align-
`ment 18.
`
`Word alignment 18 aligns the parallel data word provided
`by deserialiZer and comma detect circuit 12 to the 100 MHZ
`clock such that a clock aligned, framed 10-bit parallel data
`word is provided at 100 MHZ as an output of the Fibre
`Channel receiver block 20. The 100 MHZ clock signal from
`the clock generator is also provided as an output from the
`Fibre Channel receiver block 20 for use elsewhere, e.g., by
`circuitry which receives the 10-bit parallel data output word
`of the Fibre Channel receiver block 20.
`
`Referring now to FIG. 2, a low power, high speed serial
`to parallel data converter for converting asynchronous serial
`data into clock aligned, framed, parallel data according to
`the present invention is shown. Asynchronous serial data at
`approximately 1 GHZ is provided to 5 -bit deserialiZer 30 and
`to phase lock loop 36. The phase lock loop 36 provides a 1
`GHZ clock signal
`to clock buffer 38. Clock buffer 38
`provides a 1 GHZ clock signal to the 5-bit deserialiZer 30; a
`500 MHZ clock signal to the 4x5 flip flop array 32 and to
`pattern detect and word alignment circuit 34; and a 100 MHZ
`clock signal to 2x10 flip flop array 46 (which defines word
`alignment circuit 48).
`The 5-bit deserialiZer provides unframed 5-bit parallel
`data which is not clock aligned to the 4x5 flip flop array 32.
`The 4><5 flip flop array 32 provides 14-bit parallel data to the
`2:1 MUX array 40. The 2:1 MUX array provides partially
`clock aligned 14-bit parallel data to the 5:1 MUX array 42.
`The 5:1 MUX array 42 provides 10-bit parallel data to the
`2x10 flip flop array 46. The 2><10 flip flop array 46 provides
`framed, clock aligned, 10-bit parallel output at 100 MHZ.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`The 4><5 flip flop array 32 provides 11-bits of parallel data
`to pattern detect and word alignment circuit 34. Pattern
`detect and word alignment circuit 34 provides control sig-
`nals to the 2:1 MUX array 40, the 5 :1 MUX array 42 and the
`2x10 flip flop array 46 to effect selections by the multiplex-
`ers thereof which select the desired data word and which
`
`enhance desired clock alignment.
`Use of the 4x5 flip flop array 32 (rather than a serial
`register as in contemporary serial to parallel converters)
`facilitates clocking of the pattern detection and word align-
`ment circuit 34 at 500 MHZ, instead of 1 GHZ as required in
`contemporary serial to parallel converters. Such reduced
`clock rate provides a reduction in power consumption of 50
`percent for the affected circuitry.
`In operation, the 5-bit deserialiZer 30 converts the asyn-
`chronous serial data received thereby into 5-bit parallel data
`which moves through the 4x5 flip flop array 32 in a manner
`which facilitates detection of a delimiter character, e.g., a
`comma, by pattern detect and word alignment circuit 34, as
`discussed in detail below.
`
`The 2:1 MUX array 40 and the 5 :1 MUX array 42, taken
`together, define a selection circuit 44 which selects one of
`two 14-bit sequences of consecutive bits from the 4x5 flip
`flop array 32 and which provide a 10-bit delimiter word or
`data word. Thus, the selected sequence of 14 bits contains
`either the 7-bit delimiter character, or a subsequent 10-bit
`data word. Selection of the 14 bits is performed by pattern
`detection and word alignment circuit 34 in a manner which
`enhances alignment of the framed parallel output word with
`the 100 MHZ clock signal.
`The 5 :1 MUX array 42 selects one of five different 10-bit
`sequences from the 14-bit sequence output by the 2:1 MUX
`array 40. The selected 10-bit sequence contains either the
`delimiter word or a subsequent data word. The 2><10 flip flop
`array 46 effects word alignment by either selecting the direct
`10-bit output of the 5 :1 MUX array 42 or a 10-bit delayed
`output of the 5 :1 MUX array 42. These operations are
`discussed in detail below.
`
`It is important to note that the pattern and word alignment
`circuit 34 detects the location of a delimiter character within
`
`the 4x5 flip