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`UNIFIED PATENTS
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`EXHIBIT 1006
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`UNIFIED PATENTS
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`EXHIBIT 1006
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`UNIFIED PATENTS EXHIBIT 1006
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`UNIFIED PATENTS EXHIBIT 1006
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`Unified Patents, Inc.,
`
`Petitioner,
`
`v.
`
`Parallel Iron, LLC
`
`Patent Owner
`____________
`
`IPR2013-__
`
`Patent No. 7,197,662
`
`____________
`
`DECLARATION OF DR. JOSHUA D. ENO, Ph.D.
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
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`i
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`TABLE OF CONTENTS
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`I. Qualifications ....................................................................................................... 2
`II. My Understanding of Claim Construction ......................................................... 5
`III. My Understanding of Anticipation .................................................................... 5
`IV. My Understanding of Obviousness ................................................................... 5
`V. Level of Ordinary Skill in the Art ...................................................................... 6
`VI. The ‘662 Patent Claims ..................................................................................... 6
`VII. Claim Interpretation ......................................................................................... 10
`A. “memory section” ......................................................................................... 10
`B. “memory interface device” ........................................................................... 11
`C. “switch fabric” .............................................................................................. 12
`D. “shift register” ............................................................................................... 13
`VIII. State of the Art as of 2002 ............................................................................... 14
`IX. Discussion of Relevant Prior Art .................................................................... 21
`A. Chong ............................................................................................................ 22
`B. Matsunami ..................................................................................................... 57
`C. The Combination of Chong and Matsunami ................................................ 92
`D. The Combination of Matsunami and Schneider .........................................101
`X. Conclusion ......................................................................................................123
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`ii
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`DECLARATION OF DR. JOSHUA D. ENO, Ph.D.
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`I, Dr. Joshua D. Eno, Ph.D., declare as follows:
`
`
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`1.
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`I have been retained on behalf of Unified Patents, Inc. (“Unified
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`Patents”) in connection with its Petition for Inter Partes Review of U.S. Patent No.
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`7,197,662 (“the ‘662 patent,” Ex. 1001). I understand that the ‘662 patent is titled
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`“Methods and Systems for a Storage System,” issued March 27, 2007, and is
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`currently assigned to Parallel Iron, LLC.
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`2.
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`I have reviewed and am familiar with the specification and claims of
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`the ‘662 patent as well as the ‘662 patent’s file history.
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`3.
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`I have reviewed and am familiar with the following prior art used in
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`the Petition for Inter Partes Review of the ‘662 patent:
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` U.S. Patent No. 6,370,604 to Chong, Jr. (“Chong,” Ex. 1003).
`
` U.S. Patent No. 6,701,410 to Matsunami et al. (“Matsunami,” Ex.
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`1004).
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` U.S. Patent No. 6,594,275 to Schneider (“Schneider,” Ex. 1005).
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`4.
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`I will cite to the ‘662 patent and to prior art patents using the
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`following format: (Ex. 1001 at 3:7-25.). This example citation points to the ‘662
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`patent at column 3, lines 7-25.
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`1
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`5.
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`I am familiar with the technology at issue as of the October 31, 2002
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`filing date of the ‘662 patent.
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`6.
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`I have been asked to provide my technical review, analysis, insights,
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`and opinions regarding the above-noted references as they relate to the ‘662 patent.
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`I.
`
`Qualifications
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`7. My academic and professional pursuits are closely related to the
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`subject matter of the ‘662 patent.
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`8.
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`I am currently Senior Software Engineer and Chief Technology
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`Officer for EquityNet LLC, a crowdsourcing platform used by thousands of
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`entrepreneurs, investors, government entities, business incubators, and other
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`members of the entrepreneurial community to plan, analyze, and capitalize
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`privately-held businesses. EquityNet has helped entrepreneurs raise over $207
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`million in capital since 2005. As CTO, I am responsible for research,
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`development, and advancement of EquityNet’s technological backbone—its
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`software, database, and statistical systems.
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`9.
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`From 2005 until December 2012, I was affiliated with the University
`
`of Arkansas Department of Computer Science, first as a Distinguished Doctoral
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`Fellow and later as a Postdoctoral Researcher. During this time, I authored or
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`co-authored over a dozen publications; participated in major research grants from
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`the National Science Foundation and the Acxiom Corporation; received a National
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`2
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`Science Foundation grant for my doctoral research; served on peer review
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`committees for ACM/IEEE Web Intelligence, the ACM Conference on
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`Information and Knowledge Management, and IEEE Internet Computing; and
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`developed applications for industry partners.
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`10.
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`I received a Doctor of Philosophy (Ph.D.) degree in the field of
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`Computer Science from the University of Arkansas, a Masters of Science (M.S.)
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`degree in computer science from the University of Arkansas, and a Bachelor of
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`Science (B.S.) degree in computer science and mathematics from Southwestern
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`Adventist University.
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`11. For more than a decade, I have studied, designed, worked, and
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`published in the field of computer science. In 1999 and 2000, I worked as a
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`software developer for MatchMaker.com prior to the company’s sale to Lycos. In
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`2000 and 2001, I worked as senior software engineer for Always24x7.com, where I
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`developed a PHP rapid deployment architecture for dynamic database driven
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`websites. During my time at MatchMaker.com, I evaluated several new storage
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`solutions for a revision to our core systems, including network storage solutions
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`from EMC and Oracle. At Always24x7.com, I was responsible for choosing and
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`implementing storage solutions for clients, including both open source and
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`enterprise databases using MySQL, PostgreSQL, and Oracle. From 2001 to 2009,
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`I worked as a consultant for a wide range of clients in the areas of web
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`3
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`applications, scientific computing, and data science before becoming EquityNet's
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`CTO.
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`12.
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`In my fourteen years of industry experience, I have built, fixed,
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`analyzed, and improved networked applications that utilize the technology of the
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`‘662 patent, including networked storage, distributed databases, fault-tolerant
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`applications, and distributed backup and recovery systems. As CTO of EquityNet,
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`I build, fix, and analyze systems that rely on network storage, hardware and
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`software storage failure recovery systems, cloud-based applications, and system
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`management interfaces.
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`13.
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`In my professional and academic experience, I have supervised
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`persons of ordinary skill in the field of storage in distributed systems. At the time
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`the ‘662 patent was filed, I was a person of ordinary skill in this field.
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`14. My Curriculum Vitae is attached as Appendix A to this Declaration,
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`and contains further details on my education, experience, publications, and other
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`qualifications to render an expert opinion. My work on this case is being billed at
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`a rate of $150 per hour, with reimbursement for actual expenses. My
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`compensation is not contingent upon the outcome of this inter partes review.
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`
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`4
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`II. My Understanding of Claim Construction
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`15.
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`I understand that, at the Patent Office, claims are to be given their
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`broadest reasonable construction in light of the specification as would be read by a
`
`person of ordinary skill in the relevant art.
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`III. My Understanding of Anticipation
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`16.
`
`I understand that a claim is unpatentable if every element is actually
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`disclosed in a reference as recited in the claims. The disclosure may be explicit,
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`implicit, or inherent. I understand that a reference is read from the perspective of a
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`person of ordinary skill in the art at the time of the invention.
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`IV. My Understanding of Obviousness
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`17.
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`It is my understanding that a claimed invention is unpatentable if the
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`differences between the invention and the prior art are such that the subject matter
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`as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains. I
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`understand that an obviousness analysis involves a consideration of (1) the scope
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`and content of the prior art; (2) the differences between the claimed invention and
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`the prior art; (3) the level of ordinary skill in the pertinent field; and (4) secondary
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`considerations of non-obviousness.
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`18.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one should consider whether there exists a teaching, suggestion, or
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`5
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`motivation to combine the references so as to avoid impermissibly applying
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`hindsight when considering prior art. I understand this test should not be rigidly
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`applied, but that the test can be important to avoid such hindsight.
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`19.
`
`It is my understanding that “obviousness” is a question of law based
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`on underlying factual issues including the scope and content of the prior art and the
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`level of skill in the art. For that reason, I do not reach any conclusions here with
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`respect to the ultimate question of obviousness. Rather, my expert testimony is
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`focused on the underlying facts and analysis that are relevant to the obviousness
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`inquiry.
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`V.
`
`Level of Ordinary Skill in the Art
`
`20. Based on the technologies disclosed in the ‘662 patent, one of
`
`ordinary skill in the art would have had a B.S. in Computer Science or
`
`Engineering, as well as one to two years of academic or industry experience in the
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`field of storage in distributed systems.
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`VI. The ‘662 Patent Claims
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`21. The ‘662 patent was filed on October 31, 2002 and relates generally to
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`data storage systems and methods. The patent purports to solve a need in the prior
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`art “for large capacity storage to provide sufficient throughput for high-volume,
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`real-time applications, especially, for example in emerging applications to
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`6
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`financial, defense, research customer management, and homeland security areas.”
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`(Ex. 1001 at 2:1-5.)
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`22. The basic solution claimed by the ‘662 patent, embodied in common
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`elements that appear in each of the patent’s twenty-one claims, is a storage system
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`comprising three components: (1) one or more memory sections, (2) one or more
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`switches, and (3) a management system. (See id. at 29:27-36:20.) A memory
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`section includes “memory device(s)” and a “memory section controller” that
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`detects errors and transmits error messages. (Id. at 29:28-33). A switch includes
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`interface(s) to external devices and a switch fabric that connects the memory
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`section(s) to the interfaces based on an algorithm. (Id. at 29:33-42.) The
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`management system receives fault messages from the memory section controller
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`and removes the faulty memory section from service. (Id. at 29:42-45.) The
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`management system also determines an algorithm for use by the switch fabric and
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`instructs the switch to execute the algorithm. (Id. at 29:45-50.)
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`23. The first thirteen claims (claims 1-13) recite, or depend from a claim
`
`that recites, the language below:
`
`A storage system, comprising:
`one or more memory sections, including
`one or more memory devices having storage
`locations for storing data, and
`a memory section controller capable of detecting
`faults in the memory section and transmitting a
`fault message in response to the detected faults;
`and
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`one or more switches, including
`one or more interfaces for connecting to one or
`more external devices; and
`a switch fabric connected to one or more memory
`sections and the external device interfaces and
`interconnecting the memory sections and the
`external device interfaces based on an algorithm;
`and
`a management system capable of receiving fault
`messages from the memory section controllers and
`removing from service the memory section from
`which the fault message was received, and wherein
`the management system
`is further capable of
`determining an algorithm for use by a switch fabric
`in interconnecting the memory sections and the
`external device interfaces, and instructing the switch
`to execute the determined algorithm . . . .
`
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`24. The final eight claims (claims 14-21) recite, or depend from a claim
`
`that recites, the language below:
`
`A method for use in a storage system, comprising:
`storing data in storage locations in a memory device,
`the memory device included in a memory section;
`a management system determining an algorithm for
`use by a switch in connecting the memory section
`and an external device interface;
`the management system instructing the switch to
`execute the determined algorithm;
`the switch connecting the memory section to the
`external device interfaces based on the algorithm;
`detecting by a memory section controller a fault in
`regard to the data stored in the memory device and
`transmitting a fault message in response to the
`detected fault to the management system;
`receiving the fault message at the management
`system;
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`8
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`the management system removing from service the
`memory section from which the fault message was
`received . . . .
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`25. The elements in ¶ 22-23 are common to every claim of the ‘662
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`patent. Accordingly, I refer collectively to these elements as “the Common
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`Elements” in this Declaration.
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`26. Each claim of the ‘662 patent adds at least one element to those cited
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`above. In particular:
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` Claims 1-3 and 17-18 add elements relating to non-volatile memory used
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`as backup for the storage device(s).
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` Claim 4 adds an element relating to an external management system.
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` Claims 5, 10-11, and 19-20 add elements relating to shift registers.
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` Claims 6-9 and 17-18 add elements relating to data packet rerouting
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`(combining data with an identifier for use in forwarding the data to a
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`requesting host).
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` Claim 12 adds elements relating to control and administrative processors
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`within the management system.
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` Claims 13 and 21 add elements relating to temporary storage used when a
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`target memory device is busy.
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`27.
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`I refer collectively to the elements in ¶ 25 as “the Additional
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`Elements” in this Declaration.
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`9
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`28. The Chong, Matsunami, and Schneider prior art patents include all of
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`the Common Elements and the Additional Elements.
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`VII. Claim Interpretation
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`29.
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`In the following section, I address my interpretation of specific terms
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`used in the ‘662 patent.
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`A.
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`“memory section”
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`30. The term “memory section(s)” appears multiple times in each
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`independent claim of the ‘662 patent.
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`31.
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` One of ordinary skill would recognize that the specification of the
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`‘662 patent broadly defines the term “memory section” as follows:
`
`As used herein, the term “memory section” refers to any
`subsystem including one or more memory devices that
`may be used for storing information. This architecture is
`applicable to any device that can store data. (Ex. 1001 at
`5:9-15.)
`
`32. Based on the ‘662 patent specification (most notably the definitional
`
`language quoted above), the claims themselves, and the “broadest reasonable
`
`construction” standard I understand to be applicable to this proceeding, one of
`
`ordinary skill would interpret “memory section” in the ‘662 patent claims to mean
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`“any subsystem including one or more memory devices that may be used for
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`storing information.”
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`10
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`33.
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`I am informed that the Patent Owner is currently asserting the ‘662
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`patent in infringement proceedings in one or more district courts. I understand that
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`in at least one of those proceedings, the Patent Owner has publicly filed the
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`following proposed construction for the ‘662 patent term “memory section”: “a
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`subsystem including one or more memory device for storing information.” (Ex.
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`1002 at 6.) This further supports my opinion as to how one of ordinary skill
`
`would define this term.
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`B.
`
`“memory interface device”
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`34. The term “memory interface device(s)” appears in claims 6, 9, 10, 11,
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`17, 18, 19, and 20 of the ‘662 patent.
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`35. One of ordinary skill would recognize that the specification of the
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`‘662 patent broadly defines the term “memory interface device” as follows:
`
`Although, [sic] the term memory interface device is used
`herein, it should be understood that this term should be
`interpreted broadly to include any type of access device
`capable of accessing information stored in a memory
`device. (Ex. 1001 at 11:21-24.)
`
`36. Based on the ‘662 patent specification (most notably the definitional
`
`language quoted above), the claims themselves, and the “broadest reasonable
`
`construction” standard I understand to be applicable to this proceeding, one of
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`ordinary skill would interpret “memory interface device” in the ‘662 patent claims
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`11
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`to mean “any type of access device capable of accessing information stored in a
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`memory device.”
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`C.
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`“switch fabric”
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`37. The term “switch fabric” appears in each independent apparatus claim
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`(claims 1, 4-6, and 12-13) of the ‘662 patent.
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`38. One of ordinary skill would recognize that the specification of the
`
`‘662 patent broadly defines the term “switch fabric” as follows:
`
`The switches 22 may be any type of switch using any
`type of switch fabric, such as, for example, a time
`division multiplexed
`fabric or a space division
`multiplexed fabric. As used herein, the term “switch
`fabric” the [sic] physical interconnection architecture that
`directs data from an incoming interface to an outgoing
`interface. For example, the switches 22 may be a Fibre
`Channel switch, an ATM switch, a switched fast Ethernet
`switch, a switched FDDI switch, or any other type of
`switch. The switches 22 may also include a controller
`(not shown) for controlling the switch. (Ex. 1001 at 6:3-
`12.)
`
`39. Based on the ‘662 patent specification (most notably the definitional
`
`language quoted above), the claims themselves, and the “broadest reasonable
`
`construction” standard I understand to be applicable to this proceeding, one of
`
`ordinary skill would interpret “switch fabric” in the ‘662 patent claims to mean
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`“the physical interconnection architecture that directs data from an incoming
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`interface to an outgoing interface.”
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`
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`12
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`40.
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`I understand that the Patent Owner has publicly stated that this
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`definition is correct. (Ex. 1002 at 10.) This further supports my opinion as to how
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`one of ordinary skill would define this term.
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`D.
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`“shift register”
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`41. The term “shift register” appears in claims 5, 10-11, and 19-20 of the
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`‘662 patent.
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`42. One of ordinary skill would recognize that the specification of the
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`‘662 patent broadly defines the term “shift register” as follows:
`
`As used herein, the term “shift register” refers to any
`register, device, stage or anything else with one or more
`selectable inputs that allows a signal to be received at an
`input and then output on the occurrence of some event,
`such as, for example, a control or clock signal. (Ex. 1001
`at 17:6-11.)
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`43. The specification of the ‘662 patent acknowledges that the definition
`
`of “shift register” within the context of the ‘662 patent is different from the term’s
`
`ordinary meaning. (See Ex. 1001 at 17:6-27.) It is my understanding, therefore,
`
`that one of ordinary skill would recognize that the patentee acted as its own
`
`lexicographer with respect to the term “shift register.”
`
`44. Based on the ‘662 patent specification (most notably the patentee’s
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`acknowledgment of acting as its own lexicographer), the claims themselves, and
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`the “broadest reasonable construction” standard I understand to be applicable to
`
`this proceeding, one of ordinary skill would interpret “shift register” in the ‘662
`
`13
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`patent claims to mean “any register, device, stage or anything else with one or
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`more selectable inputs that allows a signal to be received at an input and then
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`output on the occurrence of some event.”
`
`45.
`
`I understand that the Patent Owner has publicly filed the following
`
`agreed-upon construction for the ‘662 patent term “shift register” in district court
`
`proceedings: “any register, device, stage or anything else with one or more
`
`selectable inputs that allows a signal to be received at an input and then output on
`
`the occurrence of some event, such as, for example, a control or clock signal.”
`
`(Ex. 1002 at 18.) This further supports my opinion as to how one of ordinary skill
`
`would define this term.
`
`VIII. State of the Art as of 2002
`
`46.
`
`I understand that the ‘662 patent was filed on October 31, 2002, and
`
`that the patent does not claim priority to any earlier application.
`
`47. The basic subject matter of the ‘662 patent is directed to storage in
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`distributed systems. Storage systems have their roots from the mid-twentieth
`
`century, when businesses and other large entities began storing information in
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`electronic databases. For example, a patent filed in 1948 describes a system that
`
`may be used to store information concerning reservations
`on public carriers such as airplane lines, railway lines,
`etc. . . . whereby persons at a plurality of remote
`positions may insert and withdraw information from a
`centrally located storage unit comprising a plurality of
`registers each of which will hold
`its
`information
`14
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`permanently unless changed by new data from any one of
`the positions. (Ex. 1007 at 1:8-19.)
`
`In the decades following 1948, the use (and importance) of computers
`
`48.
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`to collect and store data grew exponentially—as did the amount of data that needed
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`to be stored by businesses, universities, government agencies, and the like.
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`However, computer storage hardware did not evolve at the same pace as the
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`demand for storage capacity. By the 1980s, single-unit magnetic storage devices
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`capable of handling enterprise-scale storage were simultaneously a speed
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`bottleneck and prohibitively expensive for many enterprises. (See, e.g., Ex. 1008
`
`at 109-10; Ex. 1009 at 1:12-20.)
`
`49. An alternative emerged in the 1980s in the form of “disk arrays.” The
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`advent of personal computers led to the development and commercialization of
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`lower-cost—but lower performance, lower reliability, and lower capacity—
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`magnetic storage disks. A standard disk array groups numerous lower-end
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`physical storage disks into a single logical unit under control of a management
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`processor known as a storage controller. From the perspective of a host computer
`
`external to the disk array, dozens (or more) physical disks appear as a single,
`
`large-capacity logical storage unit. (See, e.g., Ex. 1008 at 109-10; Ex. 1009 at
`
`1:12-20.)
`
`50. Early disk arrays suffered from a significant problem, however: in an
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`array of dozens (or even hundreds) of relatively unreliable disks, reliability
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`(measured by Mean Time To Failure (MTTF)) plummets. For example, in an array
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`of 100 disks, each with a MTTF of 30,000 hours (almost 3 ½ years), the aggregate
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`MTTF shrinks to 300 hours (less than two weeks). (Ex. 1008 at 110.) In 1988,
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`academics at the University of California, Berkeley published a proposed solution
`
`to this problem that quickly became an industry standard: RAID (short for
`
`Redundant Array of Inexpensive Disks). (See id.)
`
`51.
`
` As described in U.S. Patent No. 5,974,502, filed in 1995:
`
`When used in conjunction with a host computer, a RAID
`system appears to behave just like a single disk system.
`RAID systems, however, offer many advantages over
`single disk systems. Among the advantages of RAID
`technology are improved reliability and performance.
`Reliability is improved through the use of redundancy
`information in the array which allows the system to
`continue operating even though one of the drives in the
`array has failed. The failed drive may then be replaced,
`and the lost data regenerated, without having to shut
`down the system. Conversely, if the one disk in a single
`disk system fails, the system is rendered inoperable and
`valuable data may be lost. RAID systems may achieve
`improvement in performance over single disk systems
`by, among other things, allowing data to be read from
`and written to multiple disks in the array in parallel. This
`greatly increases the speed with which I/O operations can
`be performed. (Ex. 1009 at 1:21-38.)
`
`52. By the early 1990s, RAID arrays were standard in the enterprise
`
`
`
`storage industry. A description of a “typical” RAID system from a patent filed in
`
`1995 appears below:
`
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`FIG. 1 illustrates a typical RAID system 10. This system
`10 may be used to implement any of the five RAID levels.
`As seen in the figure, the system 10 includes: a host
`computer 12, a disk array controller 14, and an array of
`disk drives 16. The host computer 12, in addition to other
`tasks, is operative for sending I/O commands to the disk
`array controller 14, instructing the controller 14 to
`perform certain read and/or write operations. The disk
`array controller 14 receives the commands from the host
`computer 12 and coordinates the transfer of data between
`the host computer 12 and the array of disk drives 16 in
`accordance with specific stored algorithms. The array of
`disk drives 16 includes a plurality of drives which are
`each independently coupled to and controlled by the disk
`array controller 14 for receiving, storing, and retrieving
`data delivered to it by the controller 14. (Ex. 1009 at
`1:49-64.)
`
`
`
`As described above, the disk array controller 14 includes
`stored algorithms which
`the controller 14 uses
`to
`coordinate the transfer of data between the host computer
`12 and the array 16. The algorithms perform such tasks as
`determining and reserving an adequate amount of buffer
`space to perform a particular transfer, controlling the
`delivery of data between the buffer and the host computer
`12, calculating the redundancy data to be stored in the
`disk array 16, distributing write data and redundancy data
`to the separate drives in the array 16, and retrieving data
`from the disk array 16. It should be apparent that the
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`algorithm used to perform any particular transfer will
`depend on both the I/O function being requested and the
`RAID level being implemented. (Id. at 1:65-2:10.)
`
`
`In the late 1980s, a communications technology called switched fabric
`
`53.
`
`Fibre Channel was introduced. Fibre Channel uses “point-to-point” physical
`
`interconnections between devices (called “ports” in the Fibre Channel protocol) to
`
`transport large amounts of data at high speed. “Switched fabric” refers to a Fibre
`
`Channel topology in which ports can be selectably point-to-point connected to one
`
`another using routing algorithms and a sophisticated hardware device called a
`
`Fibre Channel switch. By the early 1990s, engineers were integrating switched
`
`fabric networking and RAID technology to develop networked multi-array storage
`
`systems. For example, U.S. Patent No. 5,237,658, filed in 1991 and published in
`
`1993, discloses a “switching network . . . coupled between a plurality of CPU’s
`
`and a plurality of disk array systems. The switching network provides the ability
`
`for any CPU to be directly coupled to any disk array.” (Ex. 1010 at 4:9-13.)
`
`Figure 2 from this patent is shown below:
`
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`54. By the late 1990s, the integration of switched fabric Fibre Channel
`
`and RAID technology was quite mature, and the widespread trend in the enterprise
`
`storage industry was to combine the technologies to form what is now known as a
`
`“Storage Area Network” (SAN). For example, U.S. Patent No. 6,370,605
`
`(“Chong,” Ex. 1003), filed in 1999, and U.S. Patent No. 6,701,410 (“Matsunami,”
`
`Ex. 1004), effectively filed in 1999, each disclose storage systems that integrate
`
`RAID storage subsystems with switched fabric networking technology. (See supra
`
`at ¶¶ 61-95.)
`
`55.
`
`In a standard late-1990s SAN configuration—exemplified, for
`
`example, by the respective systems disclosed in Chong and Matsunami—a number
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`of storage subsystems (for example, RAID arrays) are interconnected by Fibre
`
`Channel switches. Each subsystem has its own controller (for example, a RAID
`
`controller), and a central management system communicates with the subsystem
`
`controllers and the Fibre Channel switches to efficiently manage requests and
`
`maintenance tasks system wide. (See, e.g., Ex. 1003 at Figs. 3A-3E, 4A-4B, 5; Ex.
`
`1004 at Figs. 1, 2; see also supra at ¶¶ 61-95.)
`
`56.
`
` The claimed subject matter of the ‘662 patent is another example of
`
`the standard late-1990s SAN configuration discussed above. Each of the Common
`
`Elements in the ‘662 patent claims maps directly to a late-1990s SAN analog: the
`
`claimed memory section is no more than a RAID subsystem (which comprises the
`
`claimed memory devices—i.e., disks, and the claimed memory section controller—
`
`i.e., a RAID controller); the claimed switch is no more than a Fibre Channel switch
`
`(which comprises the claimed switch fabric and the claimed point-to-point
`
`connection between storage device and host interface based on an algorithm); and
`
`the claimed management system is no more than a system controller, used in a
`
`standard SAN to control the multi-array storage system as a whole.
`
`57. The Additional Elements of the ‘662 patent claims have also been
`
`well-known to storage systems since at least the mid-to-late 1990s. In short, the
`
`‘662 patent added nothing new to the state of the art.
`
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`58. For example, numerous patent filings from this period disclose non-
`
`volatile cache memory used for dual purposes of backup and temporary storage.
`
`(See, e.g., Ex. 1004 at 9:1-50; Ex. 1011 (U.S. Patent No. 5,617,530, effectively
`
`filed in 1993) at 1:18-21 (“This invention relates to computer system data storage,
`
`and more particularly to a fault-tolerant storage device array using a copyback
`
`cache storage unit for temporary storage.”), 5:40-44 (“The copyback cache storage
`
`unit is preferably non-volatile, so that data will not be lost on a power failure. If
`
`the copyback cache storage unit is a disk drive, it may be paired with a ‘mirror’
`
`storage unit for additional fault tolerance.”).
`
`59. Additionally, numerous patent filings from this period disclose Fibre
`
`Channel frame substitution rerouting (i.e., combining requested data with an
`
`identifier for forwarding to a host device), including both Chong and Matsunami.
`
`(See Ex. 1003 at 18:45-19:20; Ex. 1004 at 9:25-10:23.)
`
`60. Patent filings from the 1990s also disclose the use of shift register
`
`arrays to deserialize Fibre Channel data for use with parallel SCSI computer
`
`interfaces (see, e.g., Ex. 1005 at 3:22-59; Fig. 7) and an interface to an external
`
`management system (see, e.g., Ex. 1004 at Fig. 18).
`
`IX. Discussion of Relevant Prior Art
`
`61.
`
`I understand that the Petition cha