`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`Unified Patents, Inc.,
`
`Petitioner,
`
`v.
`
`Parallel Iron, LLC
`
`Patent Owner
`____________
`
`IPR2013-__
`
`Patent No. 7,197,662
`
`____________
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`
`
`identified in 37 C.F.R. § 42.204(b)(2) and evidence relied upon to support the
`
`EXHIBIT LIST ........................................................................................................ iii
`I.
`INTRODUCTION ................................................................................................ 1
`II. MANDATORY NOTICES ................................................................................. 2
`A. Real Party-in-Interest ...................................................................................... 2
`B. Related Matters ............................................................................................... 2
`C. Lead and Backup Counsel .............................................................................. 3
`D. Service Information ........................................................................................ 4
`III. PAYMENT OF FEES ....................................................................................... 4
`IV. REQUIREMENTS FOR INTER PARTES REVIEW ....................................... 4
`A. Grounds for Standing ...................................................................................... 4
`B.
`Identification of Challenge ............................................................................. 5
`1. The specific art and statutory ground(s) on which the challenge is based .. 5
`2. How the construed claims are unpatentable under the statutory grounds
`challenge ............................................................................................................ 6
`V. FACTUAL BACKGROUND............................................................................. 6
`A. Declaration Evidence ...................................................................................... 6
`B. The State of the Art ........................................................................................ 7
`C. The ‘662 Patent ............................................................................................... 8
`VI. BROADEST REASONABLE CONSTRUCTION ........................................ 10
`A. “memory section(s)” ..................................................................................... 11
`B. “memory interface device(s)” ....................................................................... 11
`C. “switch fabric” .............................................................................................. 12
`D. “shift register(s)” .......................................................................................... 13
`VII. GROUNDS SHOWING THAT PETITIONER HAS A REASONABLE
`LIKELIHOOD OF PREVAILING .......................................................................... 13
`A. Chong renders obvious claims 1-3, 12, and 14-16 ....................................... 14
`B. Matsunami anticipates claims 4, 6-9, 12, and 17-18 under § 102(e) ........... 29
`C. Chong in view of Matsunami renders obvious claims 13 and 21 ................ 45
`D. Matsunami in view of Schneider renders obvious claims 5, 10-11,
`and 19-20 .............................................................................................................. 49
`VIII. CONCLUSION ............................................................................................... 56
`
`
`
`ii
`
`

`

`1001
`
`1002
`
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`
`
`1009
`
`1010
`
`1011
`
`
`
`
`EXHIBIT LIST
`
`U.S. Patent No. 7,197,662 to Bullen et al.
`
`Joint Claim Construction Charts filed July 26, 2013, in Parallel
`Iron, LLC v. Netflix, Inc., 1:12-cv-1035 (D. Del.) (publicly
`available and accessed through PACER)
`
`U.S. Patent No. 6,370,605 to Chong Jr.
`
`U.S. Patent No. 6,701,410 to Matsunami et al.
`
`U.S. Patent No. 6,594,275 to Schneider
`
`Declaration of Joshua D. Eno, Ph.D.
`
`U.S. Patent No. 2,611,813 to Sharpless et al.
`
`Patterson et al., A Case for Redundant Arrays of Inexpensive
`Disks (RAID), ACM SIGMOD Record, Vol. 17, Issue 3 (June
`1988) at 109
`
`U.S. Patent No. 5,974,502 to DeKoning et al.
`
`U.S. Patent No. 5,237,658 to Walker et al.
`
`U.S. Patent No. 5,617,530 to Stallmo et al.
`
`
`
`
`
`iii
`
`

`

`I.
`
`
`
`INTRODUCTION
`
`Petitioner Unified Patents, Inc. (“Unified Patents” or “Petitioner”)
`
`respectfully requests inter partes review of claims 1-21 of U.S. Patent No.
`
`7,197,662 (“the ‘662 patent,” attached as Ex. 1001) in accordance with 35 U.S.C.
`
`§§ 311-319 and 37 C.F.R. § 42.100 et seq.
`
`
`
`The ‘662 patent, which was filed October 31, 2002 and makes no claim to
`
`earlier priority, is generally directed toward systems and methods for high
`
`throughput data storage. (See Ex. 1001 at 1:18-19.) The patent’s twenty-one
`
`claims consist of thirteen “storage system” apparatus claims (claims 1-13) and
`
`eight “method for use in a storage system” method claims (claims 14-21). (See id.
`
`at 29:26-36:21.) As demonstrated by prior art U.S. Patent Nos. 6,370,605 to
`
`Chong, Jr. (“Chong,” Ex. 1003), 6,701,410 to Matsunami et al. (“Matsunami,” Ex.
`
`1004), and 6,594,275 to Schneider (“Schneider,” Ex. 1005) (none of which were
`
`before the Examiner); the petition itself; and the attached Declaration of Joshua D.
`
`Eno, Ph.D. (“Eno Declaration,” Ex. 1006), every claim in the ‘662 patent is
`
`unpatentable as anticipated and/or obvious.
`
`
`
`Petitioner seeks review and cancellation of all twenty-one claims of the ‘662
`
`patent.
`
`
`
`
`
`1
`
`

`

`II. MANDATORY NOTICES
`
`
`
`Pursuant to 37 C.F.R. § 42.8(a)(1), Unified Patents provides the following
`
`mandatory disclosures.
`
`A. Real Party-in-Interest
`
`
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner certifies that Unified Patents is
`
`the real party-in-interest, and further certifies that no other party exercised control
`
`or could exercise control over Unified Patents’ participation in this proceeding, the
`
`filing of this petition, or the conduct of any ensuing trial.
`
`B. Related Matters
`
`
`
`As of the filing date of this petition, the ‘662 patent is the subject of many
`
`district court actions, none of which involve Unified Patents:
`
`Venue Status
`Case No.
`6:11-cv-00036 E.D.
`terminated
`Tex.
`1:11-cv-00799 D. Del.
`1:12-cv-00121 D. Del.
`1:12-cv-00500 D. Del.
`
`terminated
`terminated
`terminated
`
` Caption
`1 Parallel Iron, LLC v. Accela
`Communications, Inc., et al.
`2 Parallel Iron, LLC v. EMC Corp.
`3 Parallel Iron, LLC v. Hortonworks, Inc.
`4 Parallel Iron, LLC v. Hitachi Data
`Systems Corp., et al.
`5 Parallel Iron, LLC v. LSI Corp.
`terminated
`1:12-cv-00501 D. Del.
`6 Parallel Iron, LLC v. Netapp, Inc.
`terminated
`1:12-cv-00502 D. Del.
`7 Parallel Iron, LLC v. Oracle Corp.
`terminated
`1:12-cv-00503 D. Del.
`8 Parallel Iron, LLC v. Adknowledge, Inc. 1:12-cv-00762 D. Del.
`terminated
`9 Parallel Iron, LLC v. Amazon Web
`1:12-cv-00763 D. Del. pending
`Services LLC, et al.
`10 Parallel Iron, LLC v. EMC Corp.
`11 Parallel Iron, LLC v. Hitachi Data Sys.
`Corp., et al.
`12 Parallel Iron, LLC v. LSI Corp.
`13 Parallel Iron, LLC v. NetApp Inc.
`
`
`1:12-cv-00764 D. Del. pending
`1:12-cv-00766 D. Del. pending
`
`terminated
`1:12-cv-00767 D. Del.
`1:12-cv-00769 D. Del. pending
`
`2
`
`

`

`14 Parallel Iron, LLC v. Oracle Corp.
`15 EMC Corp. v. Parallel Iron, LLC
`
`terminated
`terminated
`
`1:12-cv-00880 D. Del. pending
`1:12-cv-00881 D. Del.
`terminated
`
`1:12-cv-00917 D. Del.
`
`terminated
`
`1:12-cv-00995 D. Del.
`
`terminated
`
`1:12-cv-01035 D. Del. pending
`1:12-cv-01468 D. Del.
`terminated
`
`1:13-cv-00307 D. Del. pending
`
`1:13-cv-00367 D. Del. pending
`1:13-cv-00443 D. Del. pending
`
`1:12-cv-00770 D. Del.
`1:12-cv-11096 D.
`Mass.
`16 Parallel Iron, LLC v. Adobe Systems Inc. 1:12-cv-00874 D. Del. pending
`17 Parallel Iron LLC v. Citigroup, Inc.
`1:12-cv-00875 D. Del.
`terminated
`18 Parallel Iron, LLC v. Facebook Inc.
`1:12-cv-00876 D. Del. pending
`19 Parallel Iron, LLC v. LinkedIn Corp.
`1:12-cv-00877 D. Del. pending
`20 Parallel Iron, LLC v. Morgan Stanley
`1:12-cv-00878 D. Del.
`terminated
`21 Parallel Iron, LLC v. Motorola Mobility
`1:12-cv-00879 D. Del.
`terminated
`LLC
`22 Parallel Iron, LLC v. Orbitz LLC
`23 Parallel Iron, LLC v. UBS Financial
`Servs., Inc.
`24 Parallel Iron, LLC v. Accenture Inc., et
`al.
`25 Parallel Iron, LLC v. Bank of America,
`N.A.
`26 Parallel Iron, LLC v. Netflix Inc.
`27 Parallel Iron, LLC v. Accenture Inc., et
`al.
`28 Parallel Iron, LLC v. AT&T Services
`Inc., et al.
`29 Parallel Iron, LLC v. Google Inc.
`30 Parallel Iron, LLC v. Cloudera Inc., et
`al.
`31 Rackspace US, Inc. v. Parallel Iron,
`LLC, et al.
`32 EMC Corp. v. Parallel Iron, LLC
`
`5:13-cv-00274 W.D.
`Tex.
`D. Del. pending
`
`1:13-cv-916
`
`pending
`
`C.
`
`Lead and Backup Counsel
`
`
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), Petitioner provides the following
`
`designation of counsel: Lead counsel is Michael L. Kiklis (Reg. No. 38,939) and
`
`back-up counsel is Scott A. McKeown (Reg. No. 42,866).
`
`
`
`3
`
`

`

`D.
`
`Service Information
`
`
`
`Pursuant to 37 C.F.R. § 42.8(b)(4), papers concerning this matter should be
`
`served on the following.
`
`Address:
`
`
`
`Email:
`
`Telephone:
`Fax:
`
`III. PAYMENT OF FEES
`
`Michael L. Kiklis or Scott McKeown
`Oblon Spivak
`1940 Duke Street
`Alexandria, VA 22314
`cpdocketkiklis@oblon.com and
`cpdocketmckeown@oblon.com
`(703) 413-3000
`(703) 413-2220
`
`
`
`The undersigned authorizes the Office to charge the required fees as well as
`
`any additional fees that might be due to Deposit Account No. 15-0030.
`
`IV. REQUIREMENTS FOR INTER PARTES REVIEW
`
`
`
`As set forth below and pursuant to 37 C.F.R. § 42.104, each requirement for
`
`inter partes review of the ‘662 patent is satisfied.
`
`A. Grounds for Standing
`
`
`
`Pursuant to 37 C.F.R. § 42.104(a), Petitioner hereby certifies that the ‘662
`
`patent is available for inter partes review and that Petitioner is not barred or
`
`estopped from requesting inter partes review challenging the claims of the ‘662
`
`patent on the grounds identified herein.
`
`
`
`4
`
`

`

`B.
`
`Identification of Challenge
`
`
`
`Pursuant to 37 C.F.R. §§ 42.104(b) and (b)(1), Petitioner requests inter
`
`partes review of ‘662 patent claims 1-21 (“the challenged claims”), and requests
`
`that the Patent Trial and Appeal Board (“PTAB”) institute trial and cancel those
`
`claims.
`
`1.
`
`The specific art and statutory ground(s) on which the
`challenge is based
`
`
`
`Pursuant to 37 C.F.R. § 42.204(b)(2), inter partes review of claims 1-21 of
`
`the ‘662 patent is requested in view of the following references, each of which is
`
`prior art to the ‘662 patent under 35 U.S.C. § 102(e). None of these references
`
`were considered in the original prosecution of the ‘662 patent, and none are
`
`cumulative of prior art that was considered by the Examiner.
`
`
`
`(1) U.S. Patent No. 6,370,605 to Chong, Jr. (“Chong,” Ex. 1003), issued
`
`Apr. 9, 2002, from an application filed July 21, 1999.
`
`
`
`(2) U.S. Patent No. 6,701,410 to Matsunami (“Matsunami,” Ex. 1004),
`
`issued Mar. 2, 2004, from an application with an effective filing date of Dec. 21,
`
`1999.
`
`
`
`(3) U.S. Patent No. 6,594,275 to Schneider (“Schneider,” Ex. 1005),
`
`issued Jul. 15, 2003, from an application filed Sep. 25, 1998.
`
`
`
`
`
`Grounds of Unpatentability
`
`1. Chong renders obvious claims 1-3, 12, and 14-16 under § 103.
`
`5
`
`

`

`2. Matsunami anticipates claims 4, 6-9, 12, and 17-18 under § 102(e).
`
`3. Matsunami and Chong render obvious claims 13 and 21 under § 103.
`
`4. Matsunami and Schneider render obvious claims 5, 10-11 and 19-20 under
`
`§ 103.
`
`2.
`
`How the construed claims are unpatentable under the
`statutory grounds identified in 37 C.F.R. § 42.204(b)(2) and
`evidence relied upon to support the challenge
`
`
`
`Pursuant to 37 C.F.R. §§ 42.204(b)(4), an explanation of how ‘662 patent
`
`claims 1-21 are unpatentable under the statutory grounds identified above,
`
`including the identification of where each element of the claim is found in the prior
`
`art, is provided in the form of claim charts in Section VII below. Pursuant to 37
`
`C.F.R. § 42.204(b)(5), the exhibit numbers of the supporting evidence relied upon
`
`to support the challenges and the relevance of the evidence to the challenges
`
`raised, including identifying specific portions of the evidence that support the
`
`challenges, are provided in Section VII in the form of claim charts.
`
`V.
`
`FACTUAL BACKGROUND
`
`
`
`A. Declaration Evidence
`
`
`
`This petition is supported by the Declaration of Joshua D. Eno, Ph.D.
`
`(attached as Ex. 1006). Dr. Eno offers his opinion with respect to the content and
`
`state of the prior art. Dr. Eno has fourteen years of industry experience designing,
`
`building, analyzing, and improving networked applications utilizing networked
`
`
`
`6
`
`

`

`storage, distributed databases, and fault-tolerant applications, including in his
`
`current position as Senior Software Engineer and Chief Technology Office for
`
`EquityNet LLC, a crowdsourcing platform used by thousands of entrepreneurs,
`
`investors, and business incubators. Dr. Eno has studied, taught, and published in
`
`the field of computer science for more than a decade, most recently as a
`
`Distinguished Doctoral Fellow and Postdoctoral Researcher in the Department of
`
`Computer Science at the University of Arkansas, where Dr. Eno received a
`
`National Science Foundation grant for his doctoral research. (See Ex. 1006.)
`
`
`
`B.
`
`The State of the Art
`
`
`
`The basic subject matter of the ‘662 patent has its roots in the mid-twentieth
`
`century, when businesses and other large entities began storing information in
`
`electronic databases. (See Ex. 1006 at ¶ 46.) In the decades between 1948 and
`
`2002, the technology of network-accessible storage improved significantly. (See
`
`id. at ¶ 48-53.) Of particular applicability to the ‘662 patent are the technologies
`
`known as “RAID” (Redundant Array of Independent Disks), developed in the
`
`1970s and 1980s; and switched fabric Fibre Channel, developed in the late 1980s
`
`and early-to-mid 1990s. (See id.) RAID combines multiple physical disk drives
`
`into a logical unit under control of a “controller,” with data distributed among the
`
`drives by the controller according to selectable algorithms. (See id. at ¶ 48-51.)
`
`Switched fabric Fibre Channel is a communications technology in which high
`
`
`
`7
`
`

`

`speed data transport between computing devices is achieved through temporary,
`
`selectable “point-to-point” interconnections using routing algorithms and a
`
`sophisticated hardware device called a Fibre Channel switch. (See id. at ¶ 52-53.)
`
`
`
`By the late 1990s, the widespread trend in the enterprise storage industry
`
`was to combine switched fabric Fibre Channel technology with existing solutions
`
`like RAID to form what is now known as a “Storage Area Network” (SAN). (See
`
`id. at ¶ 53.) In a standard late-1990s SAN configuration, a number of storage
`
`subsystems (for example, RAID arrays) are interconnected by Fibre Channel
`
`switches. (See id. at ¶ 54.) Each subsystem has its own controller (for example, a
`
`RAID controller), and a central management system communicates with the
`
`subsystem controllers and the Fibre Channel switches to efficiently manage
`
`requests and maintenance tasks system wide. (See id.) Examples of this
`
`architecture can be seen in numerous patent filings and publications from the late
`
`1990s, including two of the prior art patents that underlie this petition, Chong (a
`
`Sun Microsystems patent filed in 1999) and Matsunami (a Hitachi patent filed in
`
`1999). (See id.)
`
`
`
`C.
`
`The ‘662 Patent
`
`
`
`The ‘662 patent was filed on October 31, 2002. The patent relates generally
`
`to data storage, and purports to solve a need in the prior art “for large capacity
`
`storage to provide sufficient throughput for high-volume, real-time applications,
`
`
`
`8
`
`

`

`especially, for example in emerging applications to financial, defense, research
`
`customer management, and homeland security areas.” (Ex. 1001 at 2:1-5.)
`
`
`
`The basic solution claimed by the ‘662 patent, embodied in common
`
`elements that appear in each of the patent’s twenty-one claims, is a storage system
`
`comprising three components: (1) one or more memory sections, (2) one or more
`
`switches, and (3) a management system. (See id. at 29:27-36:20.) A memory
`
`section includes “memory device(s)” and a “memory section controller” that
`
`detects errors and transmits error messages. (Id. at 29:28-33). A switch includes
`
`interface(s) to external devices and a switch fabric that connects the memory
`
`section(s) to the interfaces based on an algorithm. (Id. at 29:33-42.) The
`
`management system receives fault messages from the memory section controller
`
`and removes the faulty memory section from service. (Id. at 29:42-45.) The
`
`management system also determines an algorithm for use by the switch fabric and
`
`instructs the switch to execute the algorithm. (Id. at 29:45-50.) These
`
`components, arranged the same way as the claims, are found throughout prior art
`
`from the late 1990s, including the Chong and Matsunami references cited in this
`
`petition. (See Ex. 1006 at ¶ 70, 89.)
`
`
`
`Each claim of the ‘662 patent adds one or more elements to those described
`
`above. Without exception, the additional elements are generic, well-known
`
`
`
`9
`
`

`

`components and/or steps that interact with other claim elements in predictable
`
`ways. (See Ex. 1006 at ¶ 26-27, 56-59.)
`
`VI. BROADEST REASONABLE CONSTRUCTION
`
`
`
`Pursuant to 37 C.F.R. § 42.204(b)(3), the claims subject to inter partes
`
`review shall receive the “broadest reasonable construction in light of the
`
`specification of the patent in which [they] appear[].” Under this standard,
`
`the PTO applies to verbiage of the proposed claims the
`broadest reasonable meaning of the words in their
`ordinary usage as they would be understood by one of
`ordinary skill in the art, taking into account whatever
`enlightenment by way of definitions or otherwise that
`may be afforded by the written description contained in
`the applicant’s specification.
`In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). All claim terms not
`
`specifically addressed below have been accorded their broadest reasonable
`
`interpretation in light of the specification of the ‘662 patent. The construction of
`
`the below terms is supported by the declaration of Dr. Eno, in which he states how
`
`one of ordinary skill would interpret these terms using the broadest reasonable
`
`construction (“BRC”) standard. (See Ex. 1008 at ¶ 28-44.)
`
`Claim Term
`memory section
`
`memory interface device
`
`Broadest Reasonable Construction
`any subsystem including one or more memory devices
`that may be used for storing information
`any type of access device capable of accessing
`information stored in a memory device
`
`
`
`10
`
`

`

`switch fabric
`
`shift register
`
`the physical interconnection architecture that directs
`data from an incoming interface to an outgoing
`interface
`any register, device, stage, or anything else with one or
`more selectable inputs that allows a signal to be
`received at an input and then output on the occurrence
`of some event
`
`A.
`
`“memory section(s)”
`
`
`
`The term “memory section” should be interpreted as “any subsystem that
`
`includes one or more memory devices that may be used for storing
`
`information.” This interpretation is consistent with the specification of the ‘662
`
`patent, which broadly defines “memory section” as follows:
`
`As used herein, the term “memory section” refers to any
`subsystem including one or more memory devices that
`may be used for storing information. This architecture is
`applicable to any device that can store data.
`
`(Ex. 1001 at 5:9-15.) This construction matches the one proposed by the Patent
`
`Owner in public court filings. (See Ex. 1003 at 5; see also Ex. 1006 at ¶ 29-32.)
`
`B.
`
`“memory interface device(s)”
`
`
`
`The term “memory interface device” should be interpreted as “any type of
`
`access device capable of accessing information stored in a memory device.”
`
`This interpretation is consistent with the specification of the ‘662 patent, which
`
`broadly defines “memory interface device” as follows:
`
`
`
`11
`
`

`

`Although, [sic] the term memory interface device is used
`herein, it should be understood that this term should be
`interpreted broadly to include any type of access device
`capable of accessing information stored in a memory
`device.
`
`(Ex. 1001 at 11:21-24; see also Ex. 1006 at ¶ 33-35.).
`
`C.
`
`“switch fabric”
`
`
`
`The term “switch fabric” should be interpreted as “the physical
`
`interconnection architecture that directs data from an incoming interface to
`
`an outgoing interface.” This interpretation is consistent with the specification of
`
`the ‘662 patent, which broadly defines “switch fabric” as follows:
`
`The switches 22 may be any type of switch using any
`type of switch fabric, such as, for example, a time
`division multiplexed
`fabric or a space division
`multiplexed fabric. As used herein, the term “switch
`fabric” the [sic] physical interconnection architecture
`that directs data from an incoming interface to an
`outgoing interface. For example, the switches 22 may
`be a Fibre Channel switch, an ATM switch, a switched
`fast Ethernet switch, a switched FDDI switch, or any
`other type of switch. The switches 22 may also include a
`controller (not shown) for controlling the switch.
`
`Ex. 1001 at 6:3-12. This construction matches the one proposed by the Patent
`
`Owner in public court filings. (See Ex. 1003 at 10; see also Ex. 1006 at ¶ 36-39.)
`
`
`
`12
`
`

`

`D.
`
`“shift register(s)”
`
`
`
`The term “shift register” should be interpreted as “any register, device,
`
`stage, or anything else with one or more selectable inputs that allows a signal
`
`to be received at an input and then output on the occurrence of some event.”
`
`This interpretation is consistent with the specification of the ‘662 patent, which
`
`broadly defines “shift register” as follows:
`
`As used herein, the term “shift register” refers to any
`register, device, stage or anything else with one or more
`selectable inputs that allows a signal to be received at an
`input and then output on the occurrence of some event,
`such as, for example, a control or clock signal.
`
`(Ex. 1001 at 17:7-11.) The specification of the ‘662 patent admits this definition is
`
`inconsistent with the ordinary meaning, and therefore, the Patent Owner served as
`
`its own lexicographer. (See Ex. 1001 at 17:7-27.) This construction matches one
`
`agreed upon by the Patent Owner and defendants in public court filings. (See Ex.
`
`1003 at 18; see also Ex. 1006 at ¶ 40-44.)
`
`VII. GROUNDS SHOWING THAT PETITIONER HAS A REASONABLE
`LIKELIHOOD OF PREVAILING
`
`
`
`Pursuant to 37 CFR § 42.104(b)(4), Petitioner provides in the following
`
`claim charts a detailed comparison of the claimed subject matter and the prior art
`
`specifying where each element of the challenged claim is found in the prior art
`
`references.
`
`
`
`13
`
`

`

`A. Chong renders obvious claims 1-3, 12, and 14-16
`
`
`
`As explained by Dr. Eno and as presented in the following claim chart,
`
`Chong renders obvious ‘662 patent claims 1-3, 12, and 14-16. (See Ex. 1006 at
`
`22-57.) For ease of reference, a table showing ‘662 patent claim terms and
`
`corresponding disclosures in Chong appears below:
`
`Claim Term from ‘662 Patent
`memory section
`memory device
`memory section controller
`fault message
`switch
`external device interface
`
`switch fabric
`management system
`non-volatile storage device
`memory interface device
`identifier/address for use in
`forwarding data
`
`Correspondence to Chong
`storage device 18
`storage disk in storage device 18
`resident RAID controller in storage device 18
`RAID “ending status” message
`switch 22
`logic and/or hardware in switch 22 (e.g., one or
`more ports) that couples switch 22 and host
`computer 12 via one or more interconnect links
`Fibre Channel fabric in switch 22
`control module 24 in storage controller 26
`non-volatile cache 34
`Fibre Channel interface
`node address of host 12
`
`
`
`The following claim chart demonstrates, on a limitation-by-limitation basis,
`
`how claims 1-3, 12, and 14-16 of the ‘662 patent are rendered obvious by Chong
`
`under 35 U.S.C. § 103. The Chong patent discloses every element of these claims,
`
`however it loosely uses language regarding alternative embodiments. (See Ex.
`
`1006 at ¶ 81-84.) Petitioner believes that the disclosures relied upon in the below
`
`claim chart constitute a single embodiment and would support an anticipation
`
`rejection under § 102(e) for the identified claims. Nevertheless, Petitioner presents
`
`
`
`14
`
`

`

`this ground of rejection under § 103 to show that, even if some disclosures were
`
`considered alternative embodiments, such alternatives were simple design choices
`
`contemplated and suggested by the Chong patent. (See also Ex. 1006 at ¶ 81-84.).
`
`US 7,197,662 Claim
`Language
`[1] A storage system,
`comprising:
`
`[1A] one or more
`memory sections,
`including
`
`[1Ai] one or more
`memory devices having
`storage locations for
`storing data, and
`
`[1Aii] a memory section
`controller capable of
`detecting faults in the
`memory section and
`transmitting a fault
`message in response to
`the detected faults; and
`
`
`Correspondence to Chong (Ex. 1003)
`
`Chong discloses a storage system with all elements of
`claim 1, as described below in this chart. (See Ex. 1003
`at 3:39-41; see also id. at Figs. 3A-3E, 4A-4B; Ex. 1006
`at 33.)
`Chong discloses the claimed “one or more memory
`sections” through one or more storage device(s) 18:
`
`
`The storage device 18 may typically include
`more than one storage disk and the storage
`disks (not shown) may be organized into disk
`arrays
`in case of RAID-based storage
`architecture. (Ex. 1003 at 7:38-41.)
`
`
`
`[T]he storage device 18 may be a storage
`subsystem with more than one disk drives
`and a resident RAID controller. (Id. at 7:43-
`45.)
`
`(See also id. at 3:39-41, 7:38-65, 13:65-14:2; Figs. 3A-
`3E, 4A-4B, 5; Ex. 1006 at 33-34.)
`Chong discloses the claimed “one or more memory
`devices” through one or more disk drives within
`storage device 18. (See Ex. 1003 at 7:38-41, 7:43-49;
`see also id. at 7:38-65; Figs. 3A-3E and 4A-4B; Ex.
`1006 at 34.)
`Chong discloses the claimed “memory section
`controller” through a resident RAID controller in
`storage device 18. (See Ex. 1003 at 7:43-45.)
`
`The resident RAID controller in storage device 18 is
`capable of detecting faults (for example, read operation
`errors) in storage device 18 and transmitting a fault
`15
`
`

`

`US 7,197,662 Claim
`Language
`
`Correspondence to Chong (Ex. 1003)
`
`message (for example, a read operation error status
`packet) in response to the detected faults:1
`
`Following generation and transmission of the
`first and data packets, storage devices 18a-b
`generate respective first and second status
`packets relaying the status of the read
`operations.
` FIG. 12B
`illustrates an
`exemplary flow of status packets during the
`read operation. (Id. at 24:58-62; see also id.
`at 27:7-11.)
`
`
`
`
`
`Each status packet may indicate whether the
`corresponding read operation was successful,
`i.e. whether the data read was valid. (Id. at
`2:26-28; see also id. at 2:37-40 (disclosing a
`“read operation error” status packet).)
`
`
`
`1 Where a figure includes red or blue text or graphics, these are annotations added
`by the Petitioner and do not appear in the original figure.
`
`16
`
`

`

`US 7,197,662 Claim
`Language
`
`Correspondence to Chong (Ex. 1003)
`
`[1B] one or more
`switches, including
`
`[1Bi] one or more
`interfaces for
`connecting to external
`devices; and
`
`
`(See also id. at 1:66-2:42, 11:58-60, 12:10-35, 24:58-
`25:2, 25:44-54; Figs. 4A-4B; Ex. 1006 at 34-37.)
`Chong discloses switch 22:
`
`
`The switch 22 in the storage controller 26
`functions to route command, status and data
`information between two or more circuit
`elements. (Ex. 1003 at 10:52-54.)
`
`
`(See also 6:36-46; 10:52-11:11; Figs. 3A-3E, 4A-4B;
`Ex. 1006 at 37.)
`Chong discloses interface logic and/or hardware (for
`example, one or more ports) in switch 22 that connects
`switch 22 and external host computer 12 via one or
`more interconnect links. (See Ex. 1003 at 8:61-67;
`10:38-65).
`
`
`
`17
`
`

`

`US 7,197,662 Claim
`Language
`
`Correspondence to Chong (Ex. 1003)
`
`
`Fig. 4B above shows interconnect links 371 between
`switch 22 and external host 12. Each link 371 connects
`to interface logic and/or hardware in switch 22:
`
`
`FIG. 4B shows internal flow of data and
`control packets over the links 371-375 for an
`embodiment where the interconnect links
`371-375 are SCSI over Fibre Channels, and
`the switch 22 is modified to manage direct
`data transfer from the storage device 18 to
`the host 12 as previously described. It is
`noted, however, that the flow of data and
`control packets as generally depicted in FIG.
`4B may be implemented in any suitable
`interface protocol in addition to the Fibre
`Channel protocol, with or without minor
`modifications. (Id. at 12:1-10.)
`
`[T]he link interconnects may employ serial
`or parallel data transfer modes.
` Some
`examples of an interconnect architecture
`include a Fibre Channel, a parallel electrical
`
`
`
`18
`
`

`

`US 7,197,662 Claim
`Language
`
`[1Bii] a switch fabric
`connected to one or
`more memory sections
`and the external device
`interfaces and
`interconnecting the
`memory sections and
`the external device
`interfaces based on an
`algorithm; and
`
`
`
`Correspondence to Chong (Ex. 1003)
`
`bus, a USB bus, an ATM bus, a HIPPI
`interface, a SCSI bus, a FireWire bus, etc.
`(Id. at 10:41-46.) . . . The switch 22 may
`need to be configured depending on the
`interface
`standard
`(SCSI, SSA, Fibre
`Channel, ATM, etc.) for the interconnect
`links 371-375. (Id. at 10:66-11:1.)
`
`The host 12 is external to the storage system. See id. at
`3:38-40 (“The one or more storage devices, the storage
`controller, and the switch make up a storage system of
`the computer system.”); Figs. 3A-3E, 4A-4B..
`
`(See also id. at 10:51-65, 11:7-20, 11:35-52; Figs.
`3A-3E, 4A-4B, and 5; Ex. 1006 at 37-39.)
`Switch 22 includes a Fibre Channel fabric. (See Ex.
`1003 at 11:6-20). The Fibre Channel fabric connects to
`one or more storage devices 18 and to the host interface
`logic and/or hardware in switch 22:
`
`
`In one embodiment, the host 12 to controller
`26 and the controller 26 to storage device 18
`links, 371 and 374 respectively, implement
`SCSI protocol over Fibre Channel. As is
`known in the art, a Fibre Channel port simply
`manages a point-to-point connection between
`itself and the Fibre Channel fabric (here, the
`switch 22).
` Fibre Channel
`is a high
`performance serial link supporting its own, as
`well as other higher level protocols such as
`FDDI (Fibre Distributed Data Interface),
`SCSI, HIPPI, IPI (Intelligent Peripheral
`Interface), etc. (Id. at 11:6-15.)
`
`
`The switch fabric interconnection between storage
`device(s) 18 and the host interface(s) on switch 22 is
`based on a routing algorithm. As one example, Chong
`discloses a Fibre Channel data redirection algorithm
`19
`
`

`

`Correspondence to Chong (Ex. 1003)
`
`executed by hardware in switch 22 that routes data
`packets directly from storage device(s) 18 to host(s) 12
`via switch 22 (bypassing control module 24) by
`replacing header information on data packets. (See id. at
`11:36-51.) Chong discloses additional switch routing
`algorithms as alternatives or complements to the Fibre
`Channel data redirection algorithm. (See id. at 12:6-10.)
`Chong also discloses data storage management
`algorithms suitable for routing data read and write
`operations via switch 22. For example, Chong discloses
`“sample read and write operations . . . described with
`reference to various RAID levels.” (Id. at 12:10-12.)
`Nonetheless,
`
`
`that any data storage
`is evident
`[i]t
`management algorithm may be employed
`along with
`the
`scalable performance
`architecture in, for example, FIGS. 3A-3E
`and 4B to accomplish fault tolerance and
`reliable data storage. (Id. at 12:12-16.)
`
`
`(See also 19:7-63, 27:7-11; Figs. 9, 10A-10B, 11,
`12A-12B; Ex. 1006 at 39-42.)
`Chong discloses the claimed management system
`through control m