U.S. Patent No. 7,836,371
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`TOSHIBA CORPORATION
`Petitioner
`
`
`v.
`
`INTELLECTUAL VENTURES I LLC
`Patent Owner
`____________________
`
`Case No. IPR2014-00310
`Patent 7,836,371
`
`____________________
`
`
`
`PETITIONER TOSHIBA CORPORATION’S DEMONSTRATIVE
`
`EXHIBITS
`
`
`
`
`
`Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandra, VA 22313-1450
`
`WEST\254337206.1
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`TOSHIBA CORPORATION
`Petitioner
`
`
`v.
`
`INTELLECTUAL VENTURES I LLC
`Patent Owner
`____________________
`
`Case No. IPR2014-00310
`Patent 7,836,371
`
`____________________
`
`
`
`PETITIONER TOSHIBA CORPORATION’S DEMONSTRATIVE
`
`EXHIBITS
`
`
`
`
`
`Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandra, VA 22313-1450
`
`WEST\254337206.1
`
`
`
`U.S. Patent No. 7,836,371
`
`
`
`
`
`CERTIFICATE OF SERVICE
`
`The undersigned certifies that a true copy of the foregoing PETITIONER
`
`TOSHIBA CORPORATION’S DEMONSTRATIVE EXHIBITS was served
`
`electronically via e-mail on February 10, 2015, in its entirety on the following:
`
`Lori A. Gordon
`Email: lgordon-PTAB@skgf.com
`
`Michael D. Specht
`Email: mspecht-PTAB@skgf.com
`
`Donald J. Coulman
`Email: dcoulman@intven.com
`
`
`February 10, 2015
`
` /Gerald K. Sekimura/
`Gerald T. Sekimura
`Registration No. 30,103
`
`DLA PIPER LLP (US)
`555 Mission Street, Suite 2400
`San Francisco, CA 94105
`Phone: (415) 836-2576
`Fax: (415) 659-7476
`
`Lead Counsel for Petitioner
`
`
`Dated:
`
`
`
`
`WEST\254337206.1
`
`
`
`
`
`Inter Partes Review of
`U.S. Patent No. 7,836,371
`IPR2014-00310
`Toshiba Corporation
`Petitioner
`v.
`Intellectual Ventures I LLC (“IV”)
`Patent Owner
`
`Petitioner Toshiba Corporation’s Demonstratives
`Oral Hearing: February 12, 2015
`
`
`
`IV’s ’371 Patent
`
`(’371 patent, cover page – TOSH‐1001.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 2
`
`
`
`IV’s ’371 Patent: Service Processor Unit
`
`(’371 patent, Figures 1b & 2 – TOSH – 1001, annotated.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 3
`
`
`
`’371 Claims
`
`(’371 Patent, Claim 1 – TOSH-1001.)
`
`(’371 Patent, Claim 7 – TOSH-1001.)
`
`Petition sets forth invalidity of claims 1‐10:
`• Claims 1‐3, 5‐10 – Anticipated: US 5,802,273 to Levine, et al.
`• Claim 4 – Obvious: Levine in view of US 5,623,500 to Whetsel.
`
`(Petition at 23, 26-40.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 4
`
`
`
`Levine ’273 Patent
`
`(Levine, cover page – TOSH-1004.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 5
`
`
`
`Levine ’273 Patent
`
`(Levine, Fig. 1, TOSH‐1004)
`
`Petitioner Toshiba Corporation – TOSH‐1017 6
`
`
`
`IV’s Arguments (Claims 1 & 7) – Outside the Box
`Argument
`
`IV argues: Figure 4 of Levine
`depicts memory components
`(“buffer memory”) outside the
`performance monitor
`(“service processor unit”) and
`therefore that Levine does not
`disclose a “service processor
`unit . . . comprising a buffer
`memory”.
`(Response at 4‐6.)
`
`(TOSH‐1004 – Levine, Fig. 4 – annotated by Patent Owner, Response at 6.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 7
`
`
`
`IV’s Arguments (Claims 1 & 7) – Outside the Box
`Argument
`
`IV argues: Fig. 7 dotted line
`connections between the
`performance monitor and
`memory registers implies that
`the memory registers are
`external to the performance
`monitor and therefore that
`Levine does not disclose a
`“service processor unit . . .
`comprising a buffer memory”.
`(Response at 7.)
`
`(Levine Fig. 7 – TOSH‐1004.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 8
`Petitioner Toshiba Corporation - Exhibit XXX 6
`
`
`
`IV’s Arguments (Claims 1 & 7) – Outside the Box
`Argument
`
`RESPONSE: Levine discloses a “service processor unit
`(. . .) comprising . . . a buffer memory”:
`• Prior art not required to use same naming convention or designate
`functional blocks in same fashion as challenged patent.
`• Levine describes that:
`
`•
`
`(Levine 5:5‐6, 13‐15 – TOSH‐1004.)
`Figs. 4 & 7 illustrate what Levine describes as the performance
`monitor(ing), including control aspects as well as buffer
`memory aspects as recited in claims 1 & 7.
`(Reply at 2‐3, Petition at 27‐28.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 9
`
`
`
`IV’s Arguments (Claims 1 & 7) – Outside the Box
`(I/O Space) Argument
`
`IV and its expert argue: Levine’s memory components
`cannot be in the performance monitor because Levine
`states that such components are “suitably provided as
`registers or addresses in I/O space.”
`(Response at 6‐7.)
`
`RESPONSE: Levine discloses components in I/O space can
`alternatively exist in the performance monitor:
`• Levine describes memory components (MMCRn) that are included
`in the performance monitor but can also reside in I/O space. (See,
`9:39‐40, 51‐53.)
`(Reply at 3.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 10
`
`
`
`IV’s Arguments (Claim 1) – Selectable
`Multiplexer Argument
`
`IV argues: Levine does not
`disclose a “multiplicity of
`selectable probes” because
`the Levine’s multiplexers are
`not themselves selectable.
`(Response at 7‐8.)
`
`(TOSH‐1004 ‐ Levine Fig. 7.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 11
`
`
`
`IV’s Arguments (Claim 1) – Selectable
`Multiplexer Argument
`RESPONSE: Levine discloses selectable probes:
`• Levine’s multiplexers each have a multiplicity of inputs
`(probes) of which one is selected for output.
`• The same multiplexing functionality to select probes is
`disclosed in the ’371 patent:
`• SPU sets the scan flip flops “so that only signals from the
`selected probe point are allowed to flow through the
`probe string 402.” (See, ’371 10:25‐34.)
`
`(Reply at 4‐5; Petition at 28.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 12
`
`
`
`IV’s Arguments (Claim 1) – Teaching Away
`Argument
`
`IV argues: Levine teaches away from using probes
`because, purportedly, Levine states that probes are
`“prohibitively expensive.”
`(Response at 8.)
`
`RESPONSE: Levine’s cited “Background Information” discussion
`is not a teaching away:
`• “Prohibitively expensive” refers to “test instruments,” not probes.
`• Levine does not prohibit the use of probes.
`• The ’371 patent does not restrict probes to a particular type.
`(Reply at 5‐6.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 13
`
`
`
`IV’s Arguments (Claim 7) – “System Bus”
`Argument
`
`IV argues: Levine does not disclose a “system bus” or “system
`bus interface”.
`(Response at 10‐14.)
`
`• “Busses are different from individual connections
`because busses can interconnect multiple components
`and permit those components to exchange data.”
`• “A bus is a communication path that can be shared.”
`
`(Response at 13.)
`RESPONSE: IV’s argument is based on overly narrow
`definitions that do not appear in and are not supported by
`the ’371 disclosure.
`•
`IV is improperly attempting to alter claim scope
`without amending.
`(Reply at 6‐8.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 14
`
`
`
`IV’s Arguments (Claim 7) – “System Bus”
`Argument
`
`•
`
`IV’s own expert has published a broader definition of
`“bus”:
`
`(Reply at 7‐8, Ganssle and Barr, EMBEDDED SYSTEMS DICTIONARY ‐ TOSH‐1015.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 15
`
`
`
`IV’s Arguments (Claim 7) – “System Bus”
`Argument
`Claim 7 recites:
`“Service processor unit is adapted to perform capture and analysis of
`system operations signals on said system bus during normal system
`operation through said system bus interface.”
`(‘371 Patent , Claim 7 – TOSH‐1001.)
`
`• “System bus” of claim 7 cannot be limited to a bus such as
`“system bus 105” of the ’371 patent.
`•
`’371 patent does not disclose service processor unit access to the “system
`bus 105” for capture and analysis during normal system operation.
`’371 patent does not teach use of the system bus interface to capture or
`analyze signals on “system bus 105” during normal system operation.
`In contrast: ’371 patent does describe access to “system bus 105” for test
`purposes ‐ “periodic patterns . . . in a memory test . . . output . . . via the
`system bus.” (10:15‐21.)
`(Petition at 16‐17, Reply at 7, Narad Decl. ¶¶ 41‐43 – TOSH‐1007.)
`
`•
`
`•
`
`Petitioner Toshiba Corporation – TOSH‐1017 16
`
`
`
`IV’s Arguments (Claims 2 & 8) ‐ Parallel or Serial
`Ports Argument
`IV argues: Levine does not disclose a parallel I/O port or
`a serial I/O port.
`(Response at 16‐23.)
`
`RESPONSE: Parallel and/or serial ports are inherent in
`Levine.
`•
`Signals to and from circuits are serial and/or parallel – there is no
`other format
`“I don’t see any other mechanism that could be used for – for
`moving data in and out.” (Narad Dep. Tr. ‐ IV 2002 ‐ at 136:3‐22.)
`(Reply at 8‐9.)
`
`•
`
`Petitioner Toshiba Corporation – TOSH‐1017 17
`
`
`
`IV’s Arguments (Claims 2 & 8) ‐ Parallel or Serial
`Ports Argument
`IV argues: since PMC and MMCR registers of the processor can
`be accessed using a bus interface, inherency of a parallel or
`serial port fails.
`(Response at 17‐18.)
`
`RESPONSE: IV acknowledges that PMC and MMCR registers are
`accessed using special register instructions.
`(Response at 18.)
`
`• An input and output interface is inherent in Levine in order
`for the user to receive information from those registers.
`•
`“The user is somewhere outside the chip, and, therefore, I/O is
`required.” (Narad Dep. Tr. ‐ IV 2002 ‐ at 128:8‐129:5.)
`(Reply at 10.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 18
`
`
`
`IV’s Arguments (Claim 2 & 8) – External Console
`Argument
`IV argues: Levine does not disclose an “external diagnostic
`console.”
`(Response at 20.)
`RESPONSE: Levine expressly describes user activities external
`to the processor 10:
`• Using “profiling mechanism, such as a histogram.”
`•
`“Analysis of collected data . . . using such tools as . . . a graphical
`performance visualization tool.”
`• User readable and settable counters, and accessible data.
`(Reply at 11‐12, Petition at 33‐35, Narad Decl. ¶¶ 51‐56.)
`
`• Levine’s described user activities involve a keyboard, display
`(or screen or monitor), which are external to processor 10.
`(Reply at 11‐12; Narad Decl. ¶¶ 51‐56; Narad Dep. Tr. 137:18‐24.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 19
`
`
`
`Whetsel ’500 Patent
`
`(Whetsel, cover page ‐ TOSH‐1011.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 20
`
`
`
`IV’s Arguments (Claim 4) – Levine and Whetsel
`
`IV argues: Neither Levine nor Whetsel discloses a selectable
`analog probe.
`(Response at 25‐27.)
`RESPONSE: Whetsel discloses selectable analog probes
`(analog signal monitor):
`
`(TOSH‐1011 ‐ Whetsel 21:22‐36; Petition at 23, 36.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 21
`
`
`
`IV’s Arguments (Claim 4) – Levine and Whetsel
`
`IV argues: Proper reasoning not provided for combining Levine and Whetsel.
`(Response at 27‐29.)
`
`RESPONSE: Petitioner provided rational underpinnings for combining Levine
`and Whetsel:
`•
`Levine and Whetsel are analogous art: Both are directed to circuits embedded in
`integrated circuits which capture and analyze system operation signals in the
`integrated circuit during normal operation.
`(Petition at 36, referring to charts applying Levine and Whetsel to claim 1)
`• Whetsel is evidence that observability and sampling of analog signals is among the
`functions of interest and is a design choice for designers in the circuit testing art for
`use in embedded testing architectures.
`(Petition at 36, Reply at 13‐14, Narad Dec. ¶ 58.)
`• For example, one would want to add analog probes to Levine because there is
`interest in knowing “whether ground balance occurred because it may tell you
`something that happened after that moment is incorrect”.
`(Reply at 13‐14, Narad Tr. 147:14‐18.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 22
`
`
`
`IV’s Arguments (Claim 4) – Levine and Whetsel
`
`•
`
`Identified reasons for combining include:
`
`• Counting analog related events, determining ground
`balance, evaluating voltage sags.
`
`• “Analog probes might be used to monitor e.g.,
`temperature or e.g., voltage levels at one or more points
`on the chip during specific operating or processing
`conditions.”
`(Narad Decl. ¶58; Reply at 13‐14; Narad Dep. Tr. 147:2‐17.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 23
`
`
`
`IV’s Arguments (Claim 4) ‐ “Selectable Analog
`Probes” Argument
`IV argues: the combination of Levine and Whetsel does
`not result in selectable probes…because multiplexers are
`always on….
`(Response at 26‐27.)
`
`RESPONSE: For the same reasons Levine’s multiplexers provide
`selectable probes (slide 12), Whetsel’s multiplexers (slide 21)
`provide selectable analog probes.
`
`The combination results in a teaching of selectable analog
`probes.
`
`(Petition at 23, 36, Reply at 14.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 24
`
`
`
`Dependent Claims Unpatentable
`
`IV provides no separate arguments for the validity of
`dependent claims 3, 5, 6, 9‐10.
`
`(Response at 25.)
`
`Petitioner Toshiba Corporation – TOSH‐1017 25
`
`
`
`Conclusion
`
`• Claims 1‐3, 5‐10 – Anticipated: US 5,802,273 to
`Levine, et al.
`
`• Claim 4 – Obvious: Levine in view of US
`5,623,500 to Whetsel.
`
`Petitioner Toshiba Corporation – TOSH‐1017 26
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