UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.; TOSHIBA
`AMERICA ELECTONIC COMPONENTS, INC.; AND TOSHIBA AMERICA
`INFORMATION SYSTEMS, INC.,
`Petitioners,
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`v.
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`INTELLECTUAL VENTURES I LLC,
`Patent Owner
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`CASE: IPR2014-00310
`Patent 7,836,371
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`DECLARATION OF MICHAEL BARR IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`IV 2001
`IPR2014-00310
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.; TOSHIBA
`AMERICA ELECTONIC COMPONENTS, INC.; AND TOSHIBA AMERICA
`INFORMATION SYSTEMS, INC.,
`Petitioners,
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`v.
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`INTELLECTUAL VENTURES I LLC,
`Patent Owner
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`
`
`CASE: IPR2014-00310
`Patent 7,836,371
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`DECLARATION OF MICHAEL BARR IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`IV 2001
`IPR2014-00310
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`I, Michael Barr, declare as follows:
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`IPR2014-00310
`U.S. Patent No. 7,836,371
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`1.
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`I have been retained as an expert witness by Sterne, Kessler,
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`Goldstein & Fox PLLC to provide testimony on behalf of Intellectual Ventures I
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`LLC, as part of the above-captioned inter partes review proceeding. I understand
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`that this proceeding involves U.S. Patent 7,836,371 (“’371 patent”) and that the
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`Patent Trial and Appeal Board (“Board”) has assigned the proceeding the trial
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`number IPR2014-00310.
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`2.
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`In this inter partes review proceeding, I understand that the Patent
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`Office has instituted review of claims 1-10 of the ’371 patent based on two
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`references: U.S. Patent No. 5,802,273 to Levine, et al (“Levine”) and U.S. Patent
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`No. 5,623,500 to Whetsel (“Whetsel”). I understand that the Board instituted trial
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`on only the following two grounds:
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`(cid:120) Claims 1-3 and 5-10 under 35 U.S.C. § 102 as anticipated by
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`Levine
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`(cid:120) Claim 4 under 35 U.S.C. § 103 as obvious over Levine and
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`Whetsel
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`3.
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`In connection with this matter, I have reviewed and am familiar
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`with the following documents:
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`U.S. Patent No. 7,836,371
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`(cid:120) U.S. Patent No. 7,836,371 to Dervisoglu, et al. (provided as TOSH-
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`1001);
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`(cid:120) Declaration of Charles Narad (provided as TOSH-1007);
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`(cid:120) U.S. Patent No. 5,802,273 to Levine, et al. (provided as TOSH-1004);
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`(cid:120) U.S. Patent No. 5,623,500 to Whetsel, Jr. (provided as TOSH-1011);
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`(cid:120) PowerPC 604 User’s Manual, IBM Microelectronics, PowerPC,
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`Motorola 1994 (provided as TOSH-1008);
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`(cid:120) Decision: Institution of Inter Partes Review mailed July 11, 2014
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`(Paper 12); and
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`(cid:120) Transcript of the August 18, 2014 deposition of Charles Eric Narad
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`(provided as IV-2004).
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`4.
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`I understand that the ’371 patent is a continuation of U.S.
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`Application No. 11/261,762, filed on October 31, 2005, now Patent No. 7,080,301
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`which is a continuation of U.S. Application No. 10/767,265, filed on January 30,
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`2004, now U.S. Patent No. 6,964,001, which is a continuation of U.S. Application
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`No. 09/275,726, filed on March 24, 1999, now U.S. Patent No. 6,687,865. I
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`further understand that the ’371 patent claims benefit of Provisional Application
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`No. 60/079,316, filed March 25, 1998. I am familiar with the technology at issue
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`in the ’371 patent and the state of the art during these time periods.
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`5.
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`I have been asked to provide my technical review, analysis,
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`U.S. Patent No. 7,836,371
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`insights, and opinions regarding the above-noted references.
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`I.
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`Background and Qualifications
`6. My academic and professional pursuits are closely related to the
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`subject matter of the ’371 patent. I received my Bachelor of Science in Electrical
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`Engineering (BSEE) from the University of Maryland in 1994, and received my
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`Master of Science in Electrical Engineering (MSEE) from the University of
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`Maryland in 1997.
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`7.
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`During my Master’s program at the University of Maryland, I also
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`worked full-time at Hughes Network Systems (“Hughes”) as a software engineer.
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`While at Hughes, among other things, I maintained and supported a range of real-
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`time operating systems, bootloaders, and debugging tools such as ROM monitors,
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`remote debuggers, simulators, and in-circuit emulators. I also performed activities
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`relating to circuit board bring-up and testing.
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`8.
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`I later began working at TSI TelSys (“TSI”) as a principal software
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`engineer. While at TSI, I led the company’s effort to produce a software
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`development and prototyping platform for a microSPARC-IIep processor-based
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`FPGA plug-in card for Windows NT and Sun workstations. As part of this work, I
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`designed a suite of development and debugging tools for designers of applications
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`based on reconfigurable computing technology.
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`9.
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`After leaving TSI in 1998, I joined PropHead Development as a
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`software architect. At PropHead, I defined the embedded software architecture and
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`detailed design for a satellite TV set-top box joint venture involving Hughes and
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`America Online.
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`10.
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`I was only at PropHead a short time before I was offered, and
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`accepted, a position as the technical editor of “Embedded Systems Design,” a
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`monthly journal with over 60,000 subscribers. My role included working with
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`authors and columnists to refine their technical content. Later, as editor-in-chief, I
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`was responsible for all of the journal’s content. Starting at about the same time, in
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`January 1999, I founded an engineering consulting company called Netrino.
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`11.
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`In 2001, I became a member of the advisory board for the
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`Embedded Systems Conference, an annual technical conference that provides
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`attendees with information on the latest in embedded systems technology. As an
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`advisory board member, I oversaw several aspects of the conference, including
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`providing industry viewpoint and observations on emerging and ongoing trends in
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`the marketplace and suggesting panel and presentation topics relating to embedded
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`systems.
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`12. Presently, my primary occupation is as CTO of Barr Group, a
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`company that I co-founded in 2012. As part of my duties with Barr Group (and
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`Netrino before it), I created professional training curriculum and courses for
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`embedded software developers, including “Embedded Software Boot Camp” and
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`“Embedded Software Training in a Box.” Barr Group (again like Netrino before
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`it) is directly involved with the development and advancement of embedded
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`systems technology and testing/debugging. For example, we conducted new
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`product assessments of software development tools for companies introducing
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`products such as real-time operating systems and debugging tools into the
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`embedded market.
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`13.
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`In addition to my professional experience, I also have significant
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`academic and related experience.
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`14.
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`I was an adjunct professor at the University of Maryland from
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`2000 until 2002, and at Johns Hopkins University during Winter Semester 2012.
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`At the University of Maryland, I taught operating systems design to graduate and
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`undergraduate students and designed and supervised independent study projects
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`related to real-time embedded software development. While at Johns Hopkins, I
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`taught an undergraduate course on embedded software architecture.
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`15.
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`I am also an author or co-author of three books, all related to
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`embedded systems, and more than 70 articles and papers that are nearly all in the
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`field of embedded systems. I have also been awarded three patents as a co-inventor
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`for inventions relating to embedded systems.
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`16. My Curriculum Vitae is attached as IV 2002, which contains
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`further details on my education, experience, publications, and other qualifications
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`to render an expert opinion. My work on this case is being billed at a rate of $575
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`per hour, with reimbursement for actual expenses. My compensation is not
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`contingent upon the outcome of this inter partes review.
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`II. My Understanding of Claim Construction
`17.
`I understand that, at the Patent Office, claims are to be given their
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`broadest reasonable construction in light of the specification as would be read by a
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`person of ordinary skill in the relevant art.
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`III. My Understanding of Anticipation
`18.
`I understand that a claim is unpatentable if every element is
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`actually disclosed in a reference as recited in the claims. The disclosure may be
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`explicit, implicit, or inherent. I understand that a reference is read from the
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`perspective of a person of ordinary skill in the art at the time of the invention.
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`IV. My Understanding of Obviousness
`19.
`It is my understanding that a claimed invention is unpatentable if
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`the differences between the invention and the prior art are such that the subject
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`matter as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains
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`20.
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`I understand that for a single reference or a combination of
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`references to render the claimed invention obvious, a person of ordinary skill in the
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`art must have been able to arrive at the claims by altering or combining the applied
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`references.
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`21.
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`I also understand that when considering the obviousness of a patent
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`claim, one should consider whether a teaching, suggestion, or motivation to
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`combine the references exists so as to avoid impermissibly applying hindsight
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`when considering the prior art. I understand this test should not be rigidly applied,
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`but that the test can be important to avoid such hindsight.
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`V. Level of Ordinary Skill in the Art
`22. Based on the technologies disclosed in the ’371 patent, a person of
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`ordinary skill in the art would have had a B.S. degree in Electrical or Computer
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`Engineering or a related field, and two to three years of relevant work experience.
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`VI. U.S. Patent No. 5,802,273 to Levine
`23. As discussed below, in my opinion, Levine does not disclose,
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`U.S. Patent No. 7,836,371
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`expressly or inherently, the following elements of claims 1, 2, 7 and 8:
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`(cid:120) “a service processor unit comprising … a buffer memory” as
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`recited in independent claims 1 and 7
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`(cid:120) a “multiplicity of selectable probes” as recited in independent
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`claim 1
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`(cid:120) an integrated circuit comprising a “system bus”, a “service
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`processor unit comprising … a system bus interface” and “adapted
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`to perform capture and analysis of system operation signals on said
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`system bus during normal system operation through said system
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`bus interface” as recited in independent claim 1
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`(cid:120) “a parallel I/O (PIO) port,” “a serial I/O (SIO) port,” or “a JTAG
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`port” as recited in dependent claims 2 and 8
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`(cid:120) “wherein data and instructions are to be sent through at least one of
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`said ports to said service processor unit from an external
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`diagnostics console, and wherein result data is to be sent through at
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`least one of said ports from said service processor unit to said
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`external diagnostics console” as recited in dependent claims 2 and
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`8
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`A.
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`“Service Processor Unit Comprising … a Buffer Memory”
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`24. Both claims 1 and 7 recite a “service processor unit” that comprises “a
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`buffer memory.” In my opinion, Levine does not disclose a “service processor
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`unit” that comprises “a buffer memory.” In the Petition, the Petitioners identify the
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`performance monitor 50 of Levine as the recited “service processor unit” and the
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`special purpose registers 40 and/or system memory 58 as the recited “buffer
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`memory.” The special purpose registers 40 and system memory 58 are outside the
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`performance monitor. As a consequence, the performance monitor 58 of Levine
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`does not comprise either the special purpose registers 40 or the system memory 58.
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`25. Below, I have annotated FIG. 4 from Levine to highlight that the
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`special purpose registers 40 and system memory are outside the performance
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`monitor. The performance monitor is highlighted below in red. The elements
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`identified by Petitioners as the buffer memory are circled. As clearly shown in
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`FIG. 4, which Petitioners rely on to support their position, the special purpose
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`registers 40 and system memory 58 are external to the performance monitor 50.
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`26. FIG. 7 of Levine (reproduced below) also illustrates that the special
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`purpose registers, SIAR and SDAR, are outside the performance monitor 50.
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`Levine specifically depicts the connection between the performance monitor 50
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`and the SDAR and SIAR registers as a dotted line. As would be appreciated by a
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`person of skill in the art, the use of a dotted line, instead of the solid lines used
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`elsewhere in FIG. 7, indicates that these registers are placed away from (outside)
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`Levine’s performance monitor 50.
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`27. Chapter 9 of the PowerPC Manual also demonstrates that the special
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`purpose registers such as SIAR and SDAR are outside the performance monitor
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`explaining that “[t]he SIA register is located in the sequencer unit and the SDA
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`register is located in the LSU.” (PowerPC Manual, TOSH-1008, p. 9-2.) As
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`described in Levine, the sequencer unit 18 and the Load Store Unit 28 are separate
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`components of the processor 10. (Levine, 5:66-6:5.) Therefore, as would be
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`understood by a person of ordinary skill in the art, a register located in the
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`sequencer unit or in the load store unit is necessarily external to the performance
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`monitor.
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`28. Petitioners also cite to a sentence in Levine that “… the same data
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`(machine state data) is placed in SPRs 40 including SIAR, SDAR and SSR which
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`are suitably provided as registers or addresses in I/O space.” (Corrected Petition,
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`pp. 28, 31 (citing Levine 10:60-65).) However, providing a register in I/O space
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`does not require the register to be included in the performance monitor 50. To the
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`contrary, based on the architecture of Levine, in my opinion, if the SIAR or SDAR
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`registers are in I/O space, these registers would be external to both the performance
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`monitor 50 and to the processor 10.
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`29.
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`I/O space is a technique that creates a special address region separate
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`from addresses in memory space. Levine describes that processor 10 is a
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`“superscalar microprocessor.” (Levine, TOSH-1004, 5:49-50.) A component that
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`exists in I/O space in the architecture of Levine would be external to the processor
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`10 of Levine. And, because of the nature of I/O space and its special requirements,
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`a component that exists in I/O space would be external to the performance monitor
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`50 of the processor 10 in Levine.
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`B. A “Multiplicity of Selectable Probes”
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`30. Claim 1 recites a “multiplicity of selectable probes.” Because the
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`claimed probes are “selectable,” one or more probes in the “multiplicity of
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`selectable probes” may be selected while other probes may not be selected.
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`31. Petitioners equate the multiplexers disclosed in Levine (72 … 73 of
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`FIG. 7) to the claimed “multiplicity of selectable probes.” However, the
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`multiplexers 72 … 73 cannot be individually selected and therefore cannot
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`correspond to the recited “selectable probes.”
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`32. As shown in FIG. 7 (reproduced above), the multiplexers 72…73 of
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`the performance monitor are always outputting a signal (i.e., one of their received
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`input signals). The system of Levine does not have the capability to select or
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`deselect individual multiplexers. This is a fundamental characteristic of
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`multiplexers. As would be understood by persons of ordinary skill in the art, the
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`multiplexers of Fig. 7 in Levine are constructed of simple combinatorial logic that
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`cannot be turned on/off when the host device is functioning. Petitioner’s expert,
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`Charles Narad, supports my conclusion in stating that “combinatorial logic … are
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`not clocked elements” and “a combinatorial block, which is asynchronous, things
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`just flow through it.” (Narad Deposition Transcript, IV 2002, 102:11-22 (emphasis
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`added).)
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`C.
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`“System Bus” and “System Bus Interface”
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`33. Claim 7 recites “an integrated circuit” comprising “a system bus” and
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`a “service processor unit.” Claim 7 further recites that the “service processor unit
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`comprises “a system bus interface” and that the “service processor unit” is
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`“adapted to perform capture and analysis of system operation signals on said
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`system bus during normal system operation through said system bus interface.” In
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`my opinion, Levine does not disclose these elements of claim 7.
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`34. As illustrated in annotated FIG. 1 of Levine below, Petitioners
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`identify a set of signal paths individually connecting units 22, 26, 28, 30, and 32 to
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`sequencer unit 18 (signal paths 22-18, 26-18, 28-18, 30-18, and 32-18) as claim 7’s
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`“system bus.” Individual connections are not a bus. Busses are different from
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`individual connections because busses can interconnect multiple components and
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`permit those components to exchange data. In other words, a bus is a
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`communication path that can be shared. By contrast, the “signal paths” identified
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`by Petitioners are merely isolated, individual direct connections between internal
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`components of processor 10. The signal paths do not even connect with one
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`another. Therefore, these identified signal paths are not a bus.
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`35. Levine discloses a system bus labeled “system bus 11” in FIG. 1
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`below. However, this system bus cannot be the recited system bus of claim 7
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`because it is external to the processor 10 and the performance monitor 50 of
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`Levine (alleged to be the “service processor unit”) does not have an interface to it.
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`D.
`“Parallel I/O Port” and “Serial I/O Port”
`36. Levine does not explicitly disclose that processor 10 includes either a
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`“parallel I/O port” or a “serial I/O port.” Petitioners argue that serial or parallel
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`I/O ports are necessarily present in Levine stating “the reading and setting of the
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`user readable and user settable counters would be through a parallel or serial I/O.”
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`I disagree with Petitioners that serial or parallel I/O ports are necessarily present in
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`Levine.
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`37. As would be appreciated by a person of ordinary skill in the art, not
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`every interface to an integrated circuit is a port. The terms “serial I/O port” and
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`“parallel I/O port” have well-understand meanings to persons of ordinary skill in
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`the art. A “serial I/O port” is an interface between a processor and a peripheral in
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`which bits, characters, or data units are transferred sequentially. See Wiley, IV
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`2003, p. 696. A “parallel I/O port” is an interface between a processor and a
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`peripheral in which multiple bits, characters, or data units are transferred
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`simultaneously. See id. at 552.
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`38. For example, the counters of Levine can be accessed through a bus
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`interface unit (BIU) that is neither a serial or a parallel I/O port. Levine discloses
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`that the PMC and MMCR registers are accessed using special register instructions:
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`“These special purpose registers are accessible for read or write via mfspr (move
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`from special purpose register) and mtspr (move to special purpose register)
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`instructions.” (Levine, 9:45-47.) A person of ordinary skill in the art would
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`understand that the software (program) used to access the PMC and/or MMCR
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`registers is stored in a system memory such as system memory 39 of Levine. The
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`instructions stored in system memory are passed to a processor via a bus interface
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`unit (“BIU”) 12 of Levine.
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`39. A bus interface is not an I/O port. The bus interface unit 12 of Levine
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`is an interface between processor 10 and the system bus 11 of Levine. Bus
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`interface unit 12 is not an interface between processor 10 and a peripheral. FIG. 1
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`of Levine only shows a memory connected to system bus 11. FIG. 1 does not
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`show any peripherals connected to processor 10 or to the system bus 11.
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`40.
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`I disagree with the opinions provided by Petitioners’ expert Mr. Narad
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`in Paragraphs 53 and 54 of his declaration:
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`In order to set or read the PMC, the counter would have to be
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`accessible in some way to a user through a monitor and/or
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`keyboard, or any similar peripheral device. Data is transmitted
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`between a microprocessor and such peripheral devices through
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`serial or parallel ports. (Narad Decl., TOSH-1007, ¶53)
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`Therefore, since the PMC counters are user readable and settable,
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`that is, accessible externally to a user, the microprocessor must
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`have serial or parallel ports. (Id. ¶54.)
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`41. Mr. Narad fails to take into account that Levine discloses “a
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`performance monitor in a data processing system.” (Levine, 4:39-40.) That is, the
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`performance monitor of Levine is designed to operate in a complete computer
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`system. The fact that the computer system may have a serial or parallel I/O port to
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`exchange data with an external system does not necessarily mean that an integrated
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`circuit within the computer system has a serial or parallel I/O port.
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`42. Mr. Narad also fails to take into account the well-known fact that
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`software for setting registers in a system, such as the system of Levine, is often
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`loaded in memory of the system at time of manufacture. For example, instructions
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`for loading the PMC and/or MMCR registers may be loaded into a ROM before
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`the system is shipped to a user. Those instructions would then be executed when
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`certain system conditions occur (e.g., system boot). The registers of Levine can
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`therefore be set and read without any interaction with an external user.
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`E.
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`“External Diagnostics Console” Claim Elements
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`43. Claims 2 and 8 also recite that “data and instructions are to be sent
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`through at least one of said ports to said service processor unit from an external
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`diagnostics console, and wherein result data is to be sent through at least one of
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`said ports from said service processor unit to said external diagnostics console.”
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`As recognized by Petitioners, Levine does not disclose these claim elements.
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`44. However, I disagree with Petitioners that “one of ordinary skill would
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`understand that setting of user settable counters necessarily would be performed
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`through a port communicating with an external device, where the count, and
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`setting to trigger on the count, are designated by data and instructions supplied by
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`the external diagnostics console.” (Corrected Petition, p. 35.) As I discussed
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`above, various techniques exist for setting the values of the PMC and MMCR
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`registers, including techniques not involving the user or an external console (such
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`as setting the values of registers through software pre-loaded into the system).
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`45.
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`I also disagree with Petitioners’ expert Mr. Narad’s opinion that “one
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`of ordinary skill in the art would know that the ‘visualization’ in ‘graphical
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`performance visualization’ requires a human viewable display, which necessarily
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`would be external to processor 10; and that to be visualized, such data must be sent
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`outside of processor 10, converted and displayed, for example, by an external
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`device and display (external diagnostics console).” (Corrected Petition, p. 35
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`(citing ¶55 of the Narad Declaration, TOSH-1007).) Levine merely states that
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`visualization tools may be used, but not that a visualization tool must be used to
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`analyze collected data. (Levine, 11:49-52.) It is my opinion that a person of
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`ordinary skill in the art would recognize that a wide variety of tools may be used to
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`communicate results to a user. For example, the data processing system of Levine
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`may have a series of LEDs that light when a condition is encountered. In another
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`example, the data may be placed into a portion of the system memory that is
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`treated as a “frame buffer” by circuitry—external to the claimed integrated
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`circuit—that control a monitor or similar display device.
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`46. Further, even if an external display based visualization tool is used by
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`Levine, it is not necessarily the case that the results data is sent through a serial
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`I/O, parallel I/O or JTAG port on the processor 10. In fact, the results data could be
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`sent via the bus interface unit 12 from the performance monitor 50 of Levine. The
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`results data may then be transmitted to the visualization tool via a bus interface or
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`may be stored internally.
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`47. Further, a person of ordinary skill in the art would recognize that the
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`data processing system of Levine could include software or a program to process
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`the results data. For example, the software or program may aggregate results data,
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`compare results data with previous data, convert the results data, etc. before
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`sending data to an external visualization tool. Therefore, in these possible
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`scenarios, the actual results data from the performance monitor may never be
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`communicated to an external diagnostics tool.
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`VII. The combination of Levine and U.S. Patent No. 5,623,500 to Whetsel
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`48. As discussed below, in my opinion, the combination of Levine and
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`Whetsel does not disclose “wherein the selectable probes are selectable analog
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`probes,” as recited in claim 4. As I also discuss below, it is also my opinion that a
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`person having ordinary skill in the art would not have combined Levine and
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`Whetsel.
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`A.
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`“Selectable Analog Probes” Claim Element
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`49.
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`In the Petition, Petitioners allege that the analog signal monitor of
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`Whetsel can be incorporated into the performance monitor 50 of Levine.
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`(Corrected Petition, pp. 36-37.) I note that the Petition does not provide any details
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`regarding how the analog signal monitor of Whetsel can be incorporated into
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`Levine. Petitioners’ expert Mr. Narad suggests that the output of Whetsel’s
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`analog-to-digital converter (ADC) “can be attached to the ‘other events’ inputs of
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`Levine, TOSH-1004 at Fig. 7, in order to detect analog threshold events.” (Narad
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`Decl., ¶58.) Based on Mr. Narad’s statements, Petitioners appear to allege that a
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`portion of Whetsel’s analog signal monitor (the analog multiplexer and ADC) is
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`combined with the multiplexers 72 and 73 of Levine. However, such a
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`combination does not disclose “selectable analog probes.”
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`50. As I have described above, the multiplexers 72…73 of Levine are
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`always on and therefore are not “selectable probes.” And, the analog multiplexer
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`of Whetsel, like the multiplexers of Levine, is always on and is therefore also not
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`selectable. Combining multiplexers 72…73 with portions of the analog signal
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`monitor of Whetsel therefore would not result in the claimed “selectable analog
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`probes.”
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`B. No Reason to Combine Levine with Whetsel
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`51. Petitioners do not explain why the system of Levine would have any
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`use for analog signal monitoring, other than to state that Whetsel “is evidence that
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`the observability and sampling of analog signals is among the functions of
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`interest.” However, it is my opinion that the system of Levine would, in fact, not
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`have any interest in analog signals. Thus, I don’t believe that a person having
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`ordinary skill in the art would have combined Levine with Whetsel.
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`52.
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`In order to support their proposed combination, Petitioners state
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`broadly that integrated circuits can produce analog signals. However, Petitioners
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`do not identify any circuit in Levine’s processor that produces or even could
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`produce analog signals.
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`53. Petitioners also incorrectly equate the “circuit testing” of Whetsel
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`with the performance testing of Levine. Circuit testing, such as that disclosed by
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`Whetsel, seeks to determine if the circuit is operating properly, and thus may
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`benefit from the examination and analysis of analog signals, such as temperature,
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`ground bounce, etc. Levine’s performance monitoring, on the other hand, is
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`fundamentally different. Levine’s performance monitor 50 analyzes the
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`performance of software: “Performance monitor 50 is a software-accessible
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`mechanism intended to provide detailed information with significant granularity
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`concerning the utilization of PowerPC instruction execution and storage
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`control.” (Levine, 9:32-36 (emphasis added).) Analog signals such as those
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`described above do not provide useful information to improve the performance of
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`processor instruction execution and storage control. Consequently, a person of
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`ordinary skill in the art would not have been motivated to include such signals in
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`the performance monitor 50 of Levine.
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`I declare that all statements made herein of my own knowledge are true and
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`that all statements made on information and belief are believed to be true; and
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`further that these statements were made with the knowledge that willful false
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`statements and the like so made are punishable by fine or imprisonment, or both,
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`under Section 1001 of Title 18 of the United States Code, and that such willful
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`false statements may jeopardize the validity of the ’371 patent.
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`Executed this 30th day of September 2014 in Elkridge, Maryland.
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`Respectfully submitted,
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`Michael Barr
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