UNITED STATES PATENT AND TRADEMARK OFFICE
`
`___________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________
`
`TOSHIBA CORPORATION
`Petitioner
`v.
`INTELLECTUAL VENTURES II, LLC
`Patent Owner
`
`___________
`
`Case: IPR2014-00310
`
`Patent 7,836,371
`
`___________
`
`Before KEVIN F. TURNER, TREVOR M. JEFFERSON, AND DAVID C.
`MCKONE, Administrative Patent Judges
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`___________
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`
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`PETITIONER’S REPLY
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`-i-
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`___________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________
`
`TOSHIBA CORPORATION
`Petitioner
`v.
`INTELLECTUAL VENTURES II, LLC
`Patent Owner
`
`___________
`
`Case: IPR2014-00310
`
`Patent 7,836,371
`
`___________
`
`Before KEVIN F. TURNER, TREVOR M. JEFFERSON, AND DAVID C.
`MCKONE, Administrative Patent Judges
`
`___________
`
`
`
`PETITIONER’S REPLY
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`-i-
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`B.
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`ii.
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`TABLE OF CONTENTS
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`INTRODUCTION .......................................................................................... 1
`I.
`II. ARGUMENT .................................................................................................. 1
`A.
`Levine Anticipates Independent Claims of the ’371 Patent ................. 1
`i.
`Levine Discloses a Service Processor Unit Comprising A
`Buffer Memory .......................................................................... 1
`Levine Discloses a Multiplicity of Selectable Probes .......................... 6
`i.
`Patent Owner Does Not Use The Broadest Reasonable
`Interpretation for a “Multiplicity Of Selectable Probes” ........... 6
`Any Teaching Away in a Prior Art Reference Must be
`Explicit ....................................................................................... 8
`Patent Owner Fails To Apply A Broadest Reasonable
`Interpretation Of “system bus” ............................................................. 9
`Parallel or Serial I/O Is Inherently Disclosed in Levine .................... 12
`Levine Discloses an External Console ............................................... 15
`Patent Owner’s Challenge To The Combination Of Levine And
`Whetsel Should Be Rejected .............................................................. 18
`i.
`Levine in View of Whetsel Discloses “selectable analog
`probes” ..................................................................................... 21
`Patent Owner Does Not Present Separate Arguments For
`Patentability Of Claims 3, 6, 9 And 10 .............................................. 21
`III. CONCLUSION ............................................................................................. 21
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`C.
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`D.
`E.
`F.
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`G.
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`-ii-
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`CASES
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`TABLE OF AUTHORITIES
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`Page(s)
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`In re Bond,
`910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990) ................................................ 2
`
`In re Sernaker,
`702 F.2d 989, 217 USPQ 1 (Fed. Cir. 1983) ...................................................... 20
`
`In re Susi,
`440 F.2d 442, 169 USPQ 423 (CCPA 1971) ........................................................ 8
`
`Merck & Co. v. Biocraft Laboratories,
`874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975
`(1989) .................................................................................................................. 16
`
`
`
`OTHER AUTHORITIES
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`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756 (2012) ............................ 11
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`MPEP §2131 (2014)............................................................................................... 2, 4
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`-iii-
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`TOSH-1015
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`TOSH-1016
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`EXHIBIT LIST
`
`Ganssle and Barr, Embedded Systems Dictionary, CMP
`Books 2003
`
`The New IEEE Standards Dictionary of Electrical and
`Electronics Terms, 5th Ed., 1993
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`-iv-
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`I.
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`
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`INTRODUCTION
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`All of claims of U.S. Patent No. 7,836,371(TOSH-1001, “the ’371 Patent”)
`
`are challenged in this inter partes review. U.S. Patent No. 5,802,273 (TOSH-1004,
`
`“Levine”) anticipates claims 1-3 and 5-10. Claim 4 is obvious over Levine in view
`
`of U.S. Patent No. 5,623,500 (TOSH-1011, “Whetsel”). In its Response (Paper 19,
`
`“Patent Owner Resp.”), Patent Owner makes numerous, but meritless, arguments
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`attacking the cited prior art references, based on overly narrow claim constructions,
`
`and even contradicted by a publication of its own expert. Rather than seeking an
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`amendment of the claims, Patent Owner construes claimed limitations narrowly in
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`an attempt to distinguish the ’371 Patent claims from Levine and Whetsel.
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`However, Petitioner demonstrated in its Petition (Paper 6, “Pet.”), and further
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`confirms herein, why the claims of the ’371 Patent are invalid in view of the prior
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`art. Petitioner urges the Board to find claims 1 – 3 and 5 – 10 of the ’371 Patent
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`anticipated by Levine, and to find claim 4 obvious over Levine and Whetsel.
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`
`II. ARGUMENT
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`A. Levine Anticipates Independent Claims of the ’371 Patent
`i. Levine Discloses a Service Processor Unit Comprising A Buffer
`Memory
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`
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`Patent Owner does not dispute that Levine discloses memory components
`
`that store information as a part of the performance monitoring in Levine. Instead,
`
`1
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`
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`
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`Patent Owner challenges the existence of a “service processor unit” in Levine on
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`the basis that the boundary of the performance monitor block 50 in Figure 4 is not
`
`drawn to encompass the identified memory components. (Patent Owner Resp. 4-
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`7.) The crux of Patent Owner’s argument involves Levine’s Figures 4 and 7.
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`According to Patent Owner, Levine does not teach a “service processor unit”
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`because, allegedly, Figure 4 shows memory components separated from what is
`
`labeled “performance monitor 50.” Patent Owner’s argument is, in effect, that the
`
`“performance monitor 50” box in Levine is not drawn so that it encompasses the
`
`memory components that Petitioner has identified, therefore Levine does not
`
`disclose the “service processor unit” of the ’371 claims. (Patent Owner Resp. 4.)
`
`
`
`This line of reasoning is flawed because there is no requirement that a
`
`reference use the exact naming conventions as in the challenged patent, or that the
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`functional blocks in a reference be collectively designated in the same fashion as in
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`the challenged patent. Nor do the claims require that the components which
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`comprise the “service processor unit” be collectively referenced by a particular
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`name. Anticipation does not require that the prior art exactly lay out the
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`components as in the patent. See, MPEP §2131(The elements must be arranged as
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`required by the claim, but this is not an ipsissimis verbis test, i.e., identity of
`
`terminology is not required. Citing, In re Bond, 910 F.2d 831, 15 USPQ2d 1566
`
`(Fed. Cir. 1990).)
`
`2
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`
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`Levine describes Figure 4 as “a block diagram of a performance monitoring
`
`aspect of the present invention.” (Levine 5:5-6.) Levine describes Figure 7 as
`
`illustrating “a block diagram of a performance monitor configured in accordance
`
`with the present invention.” (Levine 5:13-15.) Both Figure 4 and Figure 7 set
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`forth the memory components (e.g. special purpose registers 40 and/or system
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`memory 58) that Petitioner has identified as corresponding to the “buffer memory”
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`of the “service processor unit” of claims 1 and 7. (Pet. 27-28, 38-39.) Thus,
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`included in what Levine describes as the “performance monitor(ing)” in Figures 4
`
`and 7 are memory components which correspond to the “buffer memory” of the
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`“service processor unit” of claims 1 and 7 of the ’371 Patent. Figures 4 and 7,
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`therefore, illustrate that Levine’s performance monitor(ing) includes control
`
`aspects as well as buffer memory aspects, just as claims 1 and 7 of the ’371 Patent
`
`recite the “service processor unit . . . comprising a control unit . . . a buffer
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`memory. . . .” (See, Levine 11:7-29 (“performance monitoring is implemented . . .
`
`through configuration of the performance monitor counters by the monitor mode
`
`control registers and performance monitoring data is collected . . .”); id. 10:60-65
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`(performance monitor recording “sample data (machine state data) is placed in
`
`SPRs 40”); id. 10:35-39, 9:54-57, 12:16-60, 13:30-35 (describing the selectable
`
`probes).)
`
`3
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`
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`Patent Owner argues that the particular address space location of the
`
`memory, and the depiction of a dashed line connection from the performance
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`monitor 50 to the memory, means that such memory is not a part of the
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`performance monitor (Patent Owner Resp. 6-7). However, nothing in the claims
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`requires that the “buffer memory” reside within or apart from any particular
`
`“address space,” or that the components which comprise the “service processor
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`unit” be collectively referenced by a particular name. The pertinent elements of
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`the “service processor unit” in claims 1 and 7 are simply recited as: “a control
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`unit” and “a buffer memory.” (See, ’371 Patent 15:1-5 (claim 1, service processor
`
`unit elements), 16:6-10 (claim 7, service processor unit elements); MPEP §2131.)
`
`
`
`Furthermore, Patent Owner and its expert argue that the memory
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`components (e.g. special purpose registers 40 and/or system memory 58) which
`
`Petitioner has identified as corresponding to the “buffer memory” cannot be a part
`
`of the performance monitor 50 because, according to Patent Owner and its expert,
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`Levine discloses that such components are “suitably provided as registers or
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`addresses in I/O space” and components “that exist in I/O space would be external
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`to the performance monitor 50 of the processor 10 in Levine.” (Response at 6-7.)
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`This argument is incorrect because, according to Levine, components that exist in
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`I/O space can alternatively also exist in the performance monitor: “Further
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`included in performance monitor 50 are monitor mode control registers (MMCRn)
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`4
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`
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`that establish the function of the counters PMCn, with each MMCR usually
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`controlling some number of counters. Counters PMCn and registers MMCRn are
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`typically special purpose registers physically residing on the processor 10, e.g., a
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`PowerPC,” (Levine at 9:39-45) and “[i]n a different embodiment, these registers
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`may be accessible by other mean such as addresses in I/O space.” (Id. at 9:51-53.)
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`Therefore, registers that are in I/O space can be in the performance monitor and
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`vice versa. It is well known in the art that registers are devices “capable of
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`retaining information,” i.e., memory devices. See, The New IEEE Standards
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`Dictionary of Electrical and Electronics Terms, 1993 (TOSH-1016, “IEEE
`
`Dictionary”) 1103. The disclosure of MMCRs in the performance monitor shows
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`that memory components can exist in the performance monitor. Hence, Patent
`
`Owner and its expert are wrong in saying that memory components that Petitioner
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`has identified as corresponding to the “buffer memory” cannot be a part of the
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`performance monitor.
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`
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`Consequently, Levine does disclose the control unit and buffer memory
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`required for the service processor unit of the claims. Patent Owner’s arguments,
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`based solely on a narrow view that the performance monitor 50 does not
`
`encompass the identified memory, is contrary to what the claims require and
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`therefore should be rejected.
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`
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`5
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`
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`B. Levine Discloses a Multiplicity of Selectable Probes
`i. Patent Owner Does Not Use The Broadest Reasonable
`Interpretation for a “Multiplicity Of Selectable Probes”
`
`Claim 1 recites that the service processor unit comprises “a multiplicity of
`
`selectable probes.” (’371 Patent 15:5.) Levine anticipates “a multiplicity of
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`selectable probes” because the multiplexers disclosed each have a multiplicity of
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`signals/probes at their input terminals, and each multiplexer is controlled to select
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`one of the respective signals/probes received as inputs, and places the selected
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`signal/probe on its output terminal. (See, Levine 10:35-39 (performance monitor
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`“saves machine state values in special purpose registers”), 13:35-39(multiplexers
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`receiving signals from “other events”), 9:54-57(bits from MMCRn registers allow
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`event/signal selection to be recorded/counted), 12:16-60(describing event
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`selection), 13:30-35(selection by the multiplexers are controlled by bits of the
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`MMCRn registers).) Patent Owner and its expert argue that “Levine never
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`discloses that the multiplexers 72 … 73 themselves can be individually selected”
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`(Patent Owner Resp. 9) and that the multiplexers in Levine are always outputting a
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`signal and that this means “Levine does not have capability to “turn on” (select) or
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`“turn off” (deselect) individual multiplexers.” (Response at 9.) This assertion
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`should be rejected. Patent Owner and its expert provide no support or reasoning
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`requiring the capability to select and deselect individual multiplexers. The claim is
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`for selectable probes and the multiplexers achieve that by being controlled (by bits
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`6
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`
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`from the MMCRn registers) to select for output one input from a multiplicity of
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`inputs being received. Each input to a multiplexer is a “probe”, therefore, the
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`selection for output of one of the multiplicity of inputs to a multiplexer, is the
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`selection of one of the probes – i.e., “a multiplicity of selectable probes”. In fact,
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`as illustrated in Figure 7 of Levine, there are shown at least two multiplexers (72,
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`73), each of which allows selection of a multiplicity of probes. (Pet. 28.)
`
`
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`Furthermore, Patent Owner’s construction of “multiplicity of selectable
`
`probes” which Patent Owner claims excludes the multiplexing functionality of
`
`Levine, is inconsistent with the disclosure of the ’371 patent. The same
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`multiplexing function used in Levine to select probes is disclosed in the ’371
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`patent. Figure 9a and its corresponding description in the ’371 patent describe a
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`multiplexing functionality: the SPU 101 sets the scan flip flops “so that . . . an
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`internal point connection of the target block 106 is selected for probing,
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`respectively. Next, all flip-flops along the same probe string 402 are programmed
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`(by the SPU 101) so that only signals from the selected probe point are allowed to
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`flow through the probe string 402 and arrive at the test bus connector 401.” (’371
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`Patent 10:25-34.) Levine discloses this same multiplexing functionality, as
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`discussed in the previous paragraph. Patent Owner’s narrow construction is thus in
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`conflict with the disclosure of its own ’371 patent.
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`7
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`In view of the above, and even more so under the broadest reasonable
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`interpretation standard, the multiplexers disclosed in Levine anticipate the
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`“multiplicity of selectable probes” recited in claim 1.
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`ii. Any Teaching Away in a Prior Art Reference Must be Explicit
`Patent Owner argues that Levine teaches against using probes because
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`
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`Levine states that probes are “prohibitively expensive.” (Patent Owner Resp. 8.)
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`This argument is misleading. Any teaching away in the prior art must be explicit
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`and Levine does not explicitly prohibit the use of probes. “Disclosed examples
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`and preferred embodiments do not constitute a teaching away from a broader
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`disclosure or nonpreferred embodiments.” In re Susi, 440 F.2d 442, 169 USPQ
`
`423 (CCPA 1971). Levine’s purported statement about probes being expensive in
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`the “Background Information” section of Levine at most may be construed as a
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`non-preferred embodiment and non-preferred embodiments do not rise to the level
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`of a teaching away.
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`
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`In addition, Patent Owner’s argument further implicitly limits the “probes”
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`of claim 1 of the ’371 Patent to the types of “probes” mentioned in “Background
`
`Information” section of Levine. However, Patent Owner has not cited anything in
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`the ’371 Patent which would require such a restrictive construction of “probes.”
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`Furthermore, the section from Levine relied upon by Patent Owner (Levine at
`
`8
`
`
`
`
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`2:14-17) refers to “test instruments” in general being prohibitively expensive, not
`
`probes.
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`
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`Therefore, Patent Owner’s argument about Levine teaching against using
`
`probes should be rejected.
`
`C. Patent Owner Fails To Apply A Broadest Reasonable Interpretation
`Of “system bus”
`
`
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`Patent Owner and its expert argue that Levine does not disclose the “system
`
`bus” and “system bus interface.” This flawed assertion is based on a flawed
`
`interpretation of the term “bus.” As noted above, the broadest reasonable
`
`interpretation is to be used in an inter partes review.
`
`
`
`Patent Owner and its expert apply an overly narrow definition of bus by
`
`relying upon extrinsic evidence and arguing that “a bus is a communication path
`
`that can be shared” and that “busses are different from individual connections
`
`because busses can interconnect multiple components and permit those
`
`components to exchange data.” (Patent Owner Resp. 13.)
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`
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`The definitions offered by Patent Owner and its expert are inconsistent with
`
`other definitions of “bus” in the extrinsic evidence. For example, an IEEE
`
`dictionary defines bus as “a signal line or a set of lines used by an interface to
`
`connect a number of devices and to transfer data.” (See “IEEE Dictionary” 140-
`
`141.) Therefore, an individual connection can be a bus.
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`9
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`Second, to the extent that Patent Owner advances a construction in order to
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`limit “system bus” to mean only busses like the “system bus 105” disclosed in the
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`’371 patent, such a construction is inconsistent with the disclosure of the ’371
`
`patent. Claim 7 would make no sense with Patent Owner’s narrow definition of
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`system bus, since as described in the ’371 patent, the service processor unit does
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`not connect to the “system bus 105” during normal operation through the system
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`bus interface 214 to perform capture and analysis of system operation signals. As
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`pointed out by Petitioner in its Petition, the ’371 Patent does not teach that the
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`system bus interface 214 may be used to capture or analyze system operation
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`signals on the “system bus 105” during normal system operation. (Pet. 16-17,
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`citing Declaration of Charles Narad (TOSH-1007, “Narad Decl.”) ¶¶41-43.)
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`
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`In its decision to institute this IPR, the Board addressed the construction of
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`the phrase “system operation signals on said system bus” by referring to the
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`construction applied for “system operation signals . . . during normal system
`
`operation” – namely, “signals internal to the integrated circuit when the integrated
`
`circuit is in a normal operation mode”. (Institution Decis. 9.) This does not limit
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`the signal paths to any particular structure, much less to the structure being argued
`
`by Patent Owner.
`
`
`
`Lastly, in a publication co-authored by Patent Owner’s expert, “bus” is
`
`defined as “a set of electrical signals with a group function.” See, Ganssle and
`
`10
`
`
`
`
`
`Barr, Embedded Systems Dictionary, CMP Books 2003 (TOSH-1015) 36. Yet,
`
`Patent Owner and its expert now take an extremely narrow definition that “a bus is
`
`a communication path that can be shared” and that “busses are different from
`
`individual connections because busses can interconnect multiple components and
`
`permit those components to exchange data.” (Patent Owner Resp. 13.) This new
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`found definition, much more restrictive than Patent Owner’s expert’s own earlier
`
`published definition, is an obvious effort to overcome Levine’s disclosure. Patent
`
`Owner is essentially trying to alter the scope of the claims without actually
`
`amending the claims. This is improper and contrary to the PTAB rules and
`
`regulations which already provide a patent owner provisions for amending claims
`
`if desired. “Since patent owners have the opportunity to amend their claims during
`
`IPR, PGR, and CBM trials, unlike in district court proceedings, they are able to
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`resolve ambiguities and overbreadth through this interpretive approach, producing
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`clear and defensible patents at the lowest cost point in the system.” Office Patent
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`Trial Practice Guide, 77 Fed. Reg. 48,756 at 48,764. However here, Patent Owner
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`is seeking to alter claim scope without using the established process for amending
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`claims in an IPR trial.
`
`
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`Thus, under the proper Broadest Reasonable Construction for “system bus”
`
`as set forth by the Board in its decision to institute this IPR, Levine’s internal buses
`
`11
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`
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`over which signals internal to the integrated circuit are communicated are a
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`“system bus.”
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`D. Parallel or Serial I/O Is Inherently Disclosed in Levine
`Claims 2 and 8 recite that the integrated circuit comprises at least one port
`
`
`
`“selected from the group consisting of: a parallel I/O (PIO) port, a serial I/O (SIO)
`
`port, and a JTAG port.” (’371 Patent 15:11-1 and 16:15-19.) Patent Owner argues
`
`that Levine allegedly does not include a parallel I/O port or a serial I/O port. This
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`assertion is incorrect. Petitioner’s position is that such a port is inherent because
`
`signals to and from circuits are serial and/or parallel – there is no other format.
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`(Pet. 34.) This was confirmed by Petitioner’s expert Charles Narad in his
`
`deposition, taken by Patent Owner, in this matter.
`
`136:3 Q So you are saying every port is either serial
`136:4 or parallel?
`136:5 A Yes.
`136:6 Q So there's no other --
`136:7 A Or a combination of the two. We have
`136:8 parallel/serial ports.
`136:9 Q Okay.
`136:10 A It's very common.
`136:11 Q So you are saying it's impossible to have a
`136:12 port that's anything other than serial, parallel, or
`136:13 a combination of the two?
`136:14 * * *
`136:15 THE WITNESS: I believe I already said I
`136:16 can't conceive of any other form of port.
`136:17 MS. GORDON: Okay.
`136:18 THE WITNESS: I either have one wire doing
`136:19 information serially or multiple wires delivering
`136:20 information in parallel or delivering a bunch of
`
`12
`
`
`
`
`
`
`136:21 serial, and I don't see any other mechanism that
`136:22 could be used for -- for moving data in and out.
`
`(Deposition of Charles Eric Narad, August 18, 2014 (IV 2002 (“Narad Dep.
`Tr.”)) 136:3-22.)
`
`Therefore, any challenge to Levine based on its alleged lack of a parallel
`
`and/or serial port should be rejected.
`
`
`
`Patent Owner and its expert start off with a conclusory statement that “not
`
`every interface to an integrated circuit is a port.” No support is provided for this
`
`statement. Patent Owner provides definitions of serial I/O port and parallel I/O
`
`port as interfaces between a processor and a peripheral in which multiple bits,
`
`characters, or data units are transferred sequentially or simultaneously,
`
`respectively. Recognizing that the sequential transfer of “bits, characters, or data
`
`units,” or the simultaneous transfer of “multiple bits, characters, or data units” in
`
`such definitions would be met by Levine, Patent Owner focuses the discussion on
`
`the connection to a peripheral as being an important aspect of the definition – “the
`
`interface must be an I/O port (i.e., between the processor and a peripheral) that
`
`transfers data in a specific manner (either serially or in parallel).” (Patent Owner
`
`Resp. 17.) However, the scope of serial or parallel I/O ports is broader than Patent
`
`Owner’s limited definition. Nothing in the ’371 Patent limits the terms “serial I/O
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`(SIO)” and “parallel I/O (PIO)” to require transfers only between a processor and a
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`peripheral, nor are any definitions provided for these term, much less the restrictive
`
`13
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`
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`definitions being asserted by Patent Owner. Therefore, once again, Patent Owner
`
`seeks to overcome the prior art by importing limitations not found in the
`
`Specification or the Claims. As discussed above, during inter partes review the
`
`claims should be given the broadest reasonable interpretations and Patent Owner is
`
`not using that standard.
`
`
`
`Patent Owner further challenges Petitioners inherency argument by arguing
`
`that “inherency fails because the PMC and MMCR registers of processor 10 can be
`
`accessed through interfaces other than serial and parallel I/O ports.” (Patent
`
`Owner Resp. 17.) According to Patent Owner, a bus interface is used to
`
`communicate between these registers and the processor and such a “bus interface is
`
`not an I/O port.” (Patent Owner Resp. 18.) But, as acknowledged by Patent
`
`Owner, the PMC and MMCR registers are accessed using special register
`
`instructions. (Patent Owner Resp. 18.) This access is by means of a input/output
`
`interface. Hence, it is inherent that such registers have input and output interfaces
`
`which are inherently either serial or parallel. This was confirmed by Petitioner’s
`
`expert Charles Narad.
`
`128:8 Q So is it impossible to get data from the
`128:9 counters in any way other than through a monitor
`128:10 and/or keyboard or similar peripheral device?
`128:11 * * *
`128:12 THE WITNESS: As I mentioned earlier, it
`128:13 might be possible for the microprocessor within the
`128:14 chip to access those registers directly.
`128:15 MS. GORDON: Mm-hmm.
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`14
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`128:16 THE WITNESS: However, for the user to ask
`128:17 for that or for the user to receive the information,
`128:18 some sort of I/O is necessary to the processor chip.
`128:19 BY MS. GORDON:
`128:20 Q To the processor chip.
`128:21 A To – I’m sorry, to the PMC.
`128:22 Q Okay.
`128:23 A Yes, to the processor chip, because the idea
`128:24 is these are internal to the processor chip, and we
`128:25 are questioning whether one must be external in
`129:1 order to access it.
`129:2 So what – summary of what I said was: You
`129:3 can access it internally, but you can’t get it to a
`129:4 user internally. The user is somewhere outside the
`129:5 chip, and, therefore, I/O is required.
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`(Narad Dep. Tr. 128:8 – 129:5.)
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`Therefore, any challenge to Levine based on its alleged lack of a parallel
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`and/or serial port should be rejected.
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`E. Levine Discloses an External Console
`Claims 2 and 8 recite “an external diagnostic console” which is used to send
`
`
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`and receive instructions from the processor. Levine expressly describes using a
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`“profiling mechanism, such as a histogram” with the data that is monitored and
`
`captured by the performance monitor (Levine 11:40-44), and that “analysis of
`
`collected data may be facilitated using such tools as . . . a graphical performance
`
`visualization tool ‘pv’.” (Id., 11:44-52.) Yet, Patent Owner alleges that Levine
`
`neither explicitly or inherently discloses an external console which is used for
`
`communicating with the performance monitor.
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`15
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`
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`More puzzling is Patent Owner’s statement that Levine “merely states that
`
`visualization tools may be used, but not that a visualization tool must be used to
`
`analyze collected data." (Patent Owner Resp. 22.) Patent Owner itself
`
`acknowledges, that Levine discloses “visualization tools may be used” (Patent
`
`Owner Response at 22), there is no need to rely on inherency – the use of
`
`visualization tools is taught by Levine. Although Levine discloses that an
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`“analysis of collected data may be facilitated using such tools as . . . a graphical
`
`performance visualization tool ‘pv’” (id., 11:44-52), the claims do not require the
`
`external console to conduct an analysis. Therefore, the only issue is whether
`
`Levine teaches the use of an external console. “A reference may be relied upon for
`
`all that it would have reasonably suggested to one having ordinary skill in the art,
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`including nonpreferred embodiments.” Merck & Co. v. Biocraft Laboratories, 874
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`F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989). Here,
`
`Levine expressly states that visualization tools, which correspond to the claimed
`
`external console, may be used, and Patent Owner acknowledges this in its
`
`Response as described above. (See, Narad Dep. Tr.137:10-24; Narad Decl. ¶55.)
`
`Therefore Patent Owner’s argument that Levine does not disclose an external
`
`console should be rejected.
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`16
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`Further, the claims state "...wherein data and instructions are to be sent
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`through at least one of said ports to said service processor unit from an external
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`diagnostics console, and wherein result data is to be sent through at least one of
`
`said ports from said service processor unit to said external diagnostics console."
`
`(’371 Patent 15:16-21 and 16:20-25.) This limitation is inherent because the
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`visualization tool requests data and the performance monitor provides requested
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`data. This was confirmed by Petitioner’s expert Charles Narad in a deposition,
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`taken by Patent Owner, in this matter.
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`137:10 Q Okay. Okay. So in paragraph 55 of your
`137:11 declaration, you refer to a graphics visualization
`137:12 tool.
`137:13 Do you see that?
`137:14 A Yes.
`137:15 Q And is that graphics visualization tool what
`137:16 you are referring to as the external diagnostics
`137:17 console?
`137:18 A It could comprise a portion of an external
`137:19 diagnostics console. And I'm sure diagnostics
`137:20 console means output and input, so in the form of
`137:21 output from the microprocessor to the user, it may
`137:22 be text that shows up on a terminal or it could be
`137:23 stuff that shows up on a graphics-type screen, which
`137:24 we are all used to.
`137:25 Q Okay. And so you are saying that data
`138:1 delivered to a display from a microprocessor is
`138:2 always transmitted over either a serial or parallel
`138:3 port?
`138:4 A On the chip – on the microprocessor chip,
`138:5 yes.
`
`(Narad Dep. Tr. 137:10-138:5.)
`
`17
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`Mr. Narad also stated in his declaration that “it is well known to one of
`
`ordinary skill in the art that a graphical visualization tool is capable of displaying
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`information to a user through a screen” and that “such data would be transmitted
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`over a serial or parallel port.” (See Narad Decl. ¶55.) Furthermore, “a user will
`
`send commands to the processor e.g. from a keyboard, which is connected to the
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`processor via a serial or parallel port. An external diagnostics console would
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`comprise in part an input device such as a keyboard.” (See Narad Decl. ¶51.)
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`Therefore, Levine inherently discloses an external console that is used to send
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`commands to the processor and receive collected data from the processor.
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`
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`F. Patent Owner’s Challenge To The Combination Of Levine And
`Whetsel Should Be Rejected
`
`Claim 4 recites that the selectable probes of the integrated circuit are
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`selectable analog probes. (’371 Patent 15:25-26.) Petitioner has shown that such
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`limitation is obvious based on Levine in view of Whetsel. Patent Owner first
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`alleges that this combination does not render claim 4 obvious because neither
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`Levine or Whetsel discloses a selectable analog probe. Second, Patent Owner
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`argues that Petitioner did not provide proper reasoning for combining Levine and
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`Whetsel. Both of these arguments are wrong.
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`
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`First, Whetsel discloses selectable analog probes. Whetsel describes an
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`embodiment which provides an analog signal monitor (selectable analog probe)
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`18
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`
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`comprising “an analog-to-digital converter for converting an analog signal into a
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`digital representation thereof, circuitry for comparing the digital representation
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`with predetermined comparison data and for generating a match signal . . . .”
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`(Whetsel 2:34-42. See also Pet. 23.) Other than the unsupported conclusory
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`statement, Patent Owner offers no discussion as to why Whetsel’s analog signal
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`monitor fails to anticipate the claimed selectable analog probe.
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`
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`Second, the combination of Levine and Whetsel is proper and Petitioner
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`provided rational underpinnings for the combination. Both Levine and Whetsel are
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`analogous art as both are directed to circuits embedded in integrated circuits, which
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`capture and analyze system operation signals in the integrated circuit. Petitioner
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`and Mr. Narad have provided reasons for combining including counting analog
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`related events, determining ground balance, evaluating voltage sags, etc. (Narad
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`Decl. ¶58; Narad Dep. Tr. 146:1 – 149:22.) Patent Owner argues that Petitioner’s
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`expert does not detail why analog signals would be incorporated into the
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`performance monitor of Levine and that “temperature and voltage signals do not
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`provide any useful information to improve the performance of processor
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`instruction execution and storage control.” (Patent Owner Resp. 29.) Such
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`arguments are not sustainable with a proper reading of Mr. Narad’s testimony. Mr.
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`Narad clearly states that “knowing whether ground balance occurred because it
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`may tell you something that happened after that moment is incorrect.” (Narad
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`19
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`Dep. Tr. 147:14-17.) Knowing whether the processor is operating properly
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`provides useful informa
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