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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TOSHIBA CORPORATION
`Petitioner
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`v.
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`INTELLECTUAL VENTURES II LLC
`Patent Owner
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`CASE: IPR2014-00317
`Patent 5,687,132
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`DECLARATION OF WILLIAM R. HUBER, D.Sc., P.E. IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`IV 2002
`IPR2014-00317
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`Case IPR2014-00317
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`U.S. Patent 5,687,132
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`Atty. Dkt. No. 3059.705IPR0
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`I, William R. Huber, D.Sc., P.E., a resident of West End, North Carolina,
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`declare as follows:
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`1.
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`I have been retained on behalf of Intellectual Ventures II LLC, to
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`provide declaratory evidence in inter partes review of U.S. Patent 5,687,132
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`(“’132 patent”).
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`2.
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`I am being compensated for my work related to this inter partes
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`review proceeding. My compensation is not dependent on and in no way affects
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`the substance of my statements in this Declaration.
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`3.
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`I have reviewed and am familiar with the specification and the
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`claims of the ’132 patent. I will cite to the specification using the following format:
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`(’132 patent, C1, L1-10). This example citation points to the ’132 patent
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`specification at column 1, lines 1-10.
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`4.
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`Along with the petition for inter partes review of the ’132 patent
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`(Paper 1; “Petition”), I have reviewed and am familiar with following references:
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`• U.S. Patent 5,687,132 to Rao (Ex. 1001; “’132 patent” or “Rao”);
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`• Prosecution File History for U.S. Patent 5,687,132 (Ex. 1002);
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`• Ex Parte Reexamination File History for U.S. Patent 5,687,132 (Ex.
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`1003);
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`• U.S. Patent 6,170,036 to Konishi et al. (Ex. 1004; “Konishi”);
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`• U.S. Patent 5,353,427 to Fujishima et al. (Ex. 1005; “Fujishima”);
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`• U.S. Patent 5,305, 280 to Hayano (Ex. 1006; “Hayano”);
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`• U.S. Patent 5,343,437 to Johnson et al. (Ex. 1007; “Johnson”); and
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`• Declaration of Robert J. Murphy (Ex. 1008; “Murphy Dec.”).
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`5.
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`I have referred to the following technical literature for
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`documentation of contemporaneous information on memories:
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`• B. Prince, “Semiconductor Memories, Second Edition;” John Wiley &
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`Sons, 1991 (Ex. 2005; “Prince 1991”);
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`• B. Prince, “High Performance Memories, New Architecture DRAMs
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`and SRAMs;” John Wiley & Sons; 1996 (Ex. 2004; “Prince 1996”);
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`• Intel Memory Design Handbook, August 1973 (Ex. 2006); and
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`• T. Jackson, “Inside Intel,” Harper Collins Publishers, 1997 (Ex.
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`2007).
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`6.
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`I have also reviewed and refer to the Board’s Decision to Institute
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`Inter Partes Review in this proceeding (Paper 11; “Decision”), and the transcript
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`from the deposition of Robert J. Murphy, Toshiba’s declarant (Ex. 2003).
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`7.
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`I am familiar with the technology at issue and the state of the art at
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`the time the application leading to the ’132 patent was filed.
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`I have been asked to provide my technical review, analysis,
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`8.
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`insights, and opinions regarding the above-noted references, as well as various
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`semiconductor industry practices.
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`
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`Qualifications
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`9. My academic and professional pursuits are closely related to the
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`subject matter of the ’132 patent.
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`10.
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`I have more than 50 years of experience in the semiconductor field.
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`I have over 30 years of experience in the hands-on product development, research,
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`and management of complex semiconductor integrated circuit products. This
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`experience includes the design of memory devices. I also have over 20 years of
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`technical consulting experience in the field of semiconductor memory devices.
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`11.
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`I earned a Bachelor of Science degree in Electrical Engineering in
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`1962 from the University of Pittsburgh in Pittsburgh, Pennsylvania. One year later,
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`I earned a Master of Science degree in Electrical Engineering from The Ohio State
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`University in Columbus Ohio. In 1969, I earned a Doctor of Science degree in
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`Electrical Engineering from the University of Pittsburgh.
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`12.
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`I am currently the President of Electronics Consulting Engineers
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`(ECE). I founded ECE in 1993. ECE has locations in Melbourne, Florida and West
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`End, North Carolina and provides patent-related services such as licensing
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`evaluation, validity and infringement assessment, and litigation support. I have
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`provided litigation support to various integrated circuit companies in a wide array
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`of semiconductor memory technologies such as DRAM, SDRAM, and Flash
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`memory. In providing this support, I rely on my technical experiences in the field
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`of semiconductor memory: (1) over 30 years of hands-on and management
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`experience in the semiconductor field, including the design of semiconductor
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`memory devices; (2) my involvement with semiconductor standards committees,
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`including the Joint Electron Device Engineering Council (JEDEC) Committee on
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`semiconductor memory devices; and, (3) authoring continuing education courses
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`on semiconductor memory technologies.
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`13. My hands-on and management experience in the semiconductor
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`memory field started at Bell Telephone Laboratories in 1962, where I was a
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`Supervisor and Member of Technical Staff. While at Bell, along with my group, I
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`developed and applied the concept of redundancy to semiconductor memory chips.
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`This development had a significant impact on the semiconductor memory field
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`since it reduced the impact of manufacturing defects on production yield and
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`overall product cost. I co-authored and presented a paper on this memory
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`redundancy concept. The paper won the Best Paper Award at the International
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`Solid-State Circuits Conference in 1979. I also authored/co-authored three other
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`papers focusing on semiconductor memory devices during my time at Bell. I left
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`Bell in 1982.
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`14. From 1982 to 1989, I was Manager of Integrated Circuit
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`Development and Manager of Reliability and Quality Assurance at General
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`Electric Company Microelectronics Center in Research Triangle Park, North
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`Carolina. I planned and directed new product and technology development and
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`characterization. One of the products we developed during this time was a 64K
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`radiation-hardened SRAM.
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`15. From 1989 to 1994, I worked at Harris Corporation in Melbourne,
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`Florida as Senior Scientist and Director of Engineering—Military and Aerospace
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`Division. I planned and directed new product development and characterization.
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`This effort included the development of radiation-hardened field-programmable
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`gate array devices and also involved the design of a 256K radiation-hardened
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`SRAM.
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`16.
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`In addition to my engineering experiences described above, I
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`played an active role in various Joint Electron Device Engineering Council
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`(JEDEC) committees. I was an active member of the JEDEC JC-42 Committee on
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`Semiconductor Memory Devices from its early days in 1972 until 1984. As a
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`member, I met regularly with memory specialists from companies that designed or
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`bought memories to develop physical, electrical and performance standards for a
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`wide variety of semiconductor memories. For the last two years of my tenure at
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`JEDEC JC-42, I chaired the Task Group on IC Operating Voltage Standards. We
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`developed standards for low-voltage (3.3V) operation and interface requirements
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`for memory and logic devices.
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`17.
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`In addition to my semiconductor industry experience, I am an
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`inventor on three U.S. patents that relate to semiconductor devices. Two of the
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`patents directly relate to semiconductor memory devices—in particular, DRAM
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`devices. I am also a Senior Member of the Institute of Electrical and Electronics
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`Engineers (IEEE) and have been a member for over 50 years. I am currently
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`registered as a Professional Engineer in Florida and North Carolina.
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`18. Additional information on my education, technical experience and
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`professional associations can be found in my curriculum vitae (attached as
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`Appendix A).
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`Level of Skill in the Art
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`19.
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`I have been asked to consider the level of ordinary skill in the art
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`that someone would have had at the time the claimed invention was made. In
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`deciding the level of ordinary skill, I considered the following:
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`• the level of education and experience of persons working in the
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`field;
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`• the types of problems encountered in the field; and,
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`• the sophistication of the technology.
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`20. Based on the technologies disclosed in the ’132 patent, a person of
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`ordinary skill in the art would have a Master of Science degree in Electrical
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`Engineering or an equivalent field, as well as at least 2 years of industry experience
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`designing semiconductor memories. Less education could be compensated by more
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`direct experience.
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`
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`Anticipation Law
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`21.
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`I understand that the Board adopted the Petitioner’s arguments
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`challenging the patentability of certain ’132 patent claims based on Konishi and
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`Fujishima:
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`• Claims 1-14, 28, and 29 are anticipated by Konishi; and
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`• Claims 1-14, 28, and 29 are anticipated by Fujishima.
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`(See Decision, Paper 11, p. 29.)
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`22.
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`I understand that a claim is anticipated if every element as recited
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`in the claim is actually disclosed in a single reference as recited in the claim. The
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`disclosure may be explicit, implicit, or inherent. I understand that a reference is
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`read from the perspective of a person of ordinary skill in the art at the time of the
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`invention.
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`The ’132 Patent and Support for Subarrays Having Same Type of Memory
`Cells
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`23. The subject of the ’132 patent is semiconductor memories, and for
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`orientation purposes, it is appropriate to place that technology into a broader
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`context. A diagram from B. Prince, Semiconductor Memories, A Handbook of
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`Design, Manufacture, and Application, John Wiley & Sons, 2ed., 1991 (also
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`referred to herein as “Prince 1991”; Ex. 2005) will help to meet that objective:
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`Figure 3.1 from Prince 1991 (Ex. 2005, p. 49)
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`24. The essential task of a memory is to provide for storage and
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`retrieval of information. This tree diagram captures many, but certainly not all of
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`the media that can provide those functions of information storage and retrieval.
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`25.
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`Before analyzing the differences between the Konishi and
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`Fujishima references and the ’132 patent, I would like to provide insight on the
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`technical challenges addressed by the ’132 patent. This will help define certain
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`terms in the ’132 patent claims in view of its specification as well as what a person
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`of ordinary skill in the art would have understood during the 1995 timeframe (also
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`referred to herein as “the relevant timeframe”).
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`26.
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`The background of the ’132 patent specification discusses that
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`video display systems during the relevant timeframe suffered from an inefficient
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`block transfer of data between a central processing unit (CPU) and a display
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`controller. (See ’132 patent, Ex. 1001, C1, L52-67.) This is because,
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`[d]uring a block transfer, an entire block of data is either moved
`or copied from a source area in memory to a destination in
`memory. The transfer may be between the system memory and
`the frame buffer, within the system memory, or within the
`frame buffer. Block transfers operations can be performed by a
`“BLT (bit-block transfer) engine” within either the display
`controller or the CPU, or even by the CPU itself. Typically, the
`data is read from the source area of memory a word or a byte at
`a time, and then written into the destination block of memory a
`word or byte at a time. The use of two operations (a read and a
`write) results in substantial inefficiencies, especially when the
`transfer crosses chip boundaries; not only are the number of
`required clock cycles doubled, but the bandwidth of the device
`interfaces and the interconnecting bus are diverted from other
`critical operations.
`(Id., C1, L52-67.)
`The claimed inventions of the ’132 patent apply a “multi-bank” memory or
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`subarray memory configuration to address these inefficiencies. The ’132 patent
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`specification describes a scheme to efficiently transfer data between banks of
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`memory or subarrays of memory, with the banks or subarrays containing the same
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`type of memory.
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`In practice, memory systems (such as the ones disclosed in the
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`27.
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`’132 patent) are concerned with transferring data (e.g., large quantities of data).
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`Such systems often rely on parallel (or simultaneous) transfer of data rather than a
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`serial (or sequential) transfer. While the ’132 patent claims discuss “transferring at
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`least one bit of data,” in practice the invention can also be used to transfer a much
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`larger amount of data, for example, in parallel.
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`28.
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`Specifically, the claimed inventions provide circuitry to couple
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`bitlines of a first subarray to bitlines of a second subarray (with the same type of
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`memory cells as the first subarray).1 Using this circuitry, data is efficiently
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`transferred between the first and second subarrays. FIG. 2A of the ’132 patent
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`(reproduced below) provides an example illustration of bitlines 202 of a first
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`subarray 200a coupled to bitlines 202 of a second subarray 200b via gates 203. The
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`configuration in FIG. 2A “advantageously allows for the transfer of data from
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`subarray 200a to subarray 200b with only a single gate delay per bit. In the
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`preferred embodiment, gates 203 are field effect transistors having a source-drain
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`1 In view of the description in the ’132 patent specification and technical
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`literature published during the timeframe of the claimed invention, the memory
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`cells in each of the first and second subarrays are the same type. This is described
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`in further detail below.
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`path coupling the respective bitlines 202 and a gate coupled to control circuitry
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`206.” (’132 patent, Ex. 1001, C8, L49-54.)
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`FIG. 2A of the ’132 Patent (Ex. 1001)
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`29.
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`For efficient data transfer, the banks of memory or subarrays of
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`memory described in the ’132 patent specification (e.g., subarrays 200a and 200b
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`in FIG. 2A above) have the same type of memory cells. For example, the
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`specification states that to ensure smooth operation between banks of memory or
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`between subarrays of memory, “the physical structure of subarrays 200 [or
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`memory banks] should be substantially identical.” (Id., C11, L24-25, emphasis
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`added.)
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`30.
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`The ’132 patent specification describes only a memory or
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`memory system with subarrays (or banks) that have the same type of memory
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`cells. For example, the specification describes a memory device partitioned into
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`banks or subarrays, where the banks or subarrays include the same type of memory
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`cells.
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`In general, the principles of the present invention provide for
`the construction and operation of multiple bank memories. . . .
`Generally, each memory includes multiple subarrays of
`columns of memory cells, the bitlines of which may be
`selectively coupled together by gating circuitry. This allows,
`among other things, for a bit of data to be transferred from one
`column of memory cells to another with only one gate delay.
`Further, the principles of the present invention allow for the two
`banks of memory
`to be operated asynchronously and
`independently.
`(Id., C3, L3-15, emphasis added.)
`
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`Memory 20 includes an array of n number of rows and m
`number of columns of memory cells partition[ed] into an
`upper bank or subarray 200a and a lower bank or subarray
`200b. In the preferred embodiment, the memory cells are
`dynamic random access memory (DRAM) cells, although in
`alternate embodiments other memory devices, such as static
`random access memory (SRAM) cells, may be used.
`(Id., C7, L11-17, emphasis added.)
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`The above quotations refer to memory 20 in FIG. 2A of the ’132
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`31.
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`patent (reproduced above). The specification states that “memory 20 is fabricated
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`on [a] single integrated circuit chip, although the present invention is not limited to
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`single chip embodiments.” (Id., C7, L5-9.) Though the present invention is not
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`limited to a single chip embodiment, the memory banks or subarrays of memory 20
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`have the same type of memory cells to ensure efficient data transfer and smooth
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`operation.
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`32. Consistent with the description of the ’132 patent specification,
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`elements with the same notation—e.g., subarray 200—are the same across all
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`figures of the patent. From the notation “subarray 200,” subarray 200a and
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`subarray 200b refer to two instances of subarrays with the same type of memory
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`cells. This is consistent with the general description of subarray 200 (without the
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`notation “200a” or “200b”).
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`In the preferred embodiment, multiple pairs of bitlines
`BLAx/BLAx can be simultaneously coupled as a block to
`corresponding bitline pairs BLBx/BLBx. This reduces the
`number of external control signals Colselx and reduces the
`number of control lines 207 on-chip. For example, assume that
`data is to be exchanged between subarrays in 64-bit blocks (64
`bitline pairs or 128 bitlines) and that each subarray 200
`includes 512 column pairs. In this case, only eight control lines
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`207 are required, each coupled to a corresponding 128 gates
`203. The number of external control signals Colselx needed to
`select one of eight 64-bit block of columns correspondingly will
`be 3.
`(Id., C9, L24-35, emphasis added.)
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`In this example, each subarray 200 in FIG. 2A—i.e., subarray 200a and subarray
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`200b—has the same bitline arrangement of 64 bitline pairs or 128 bitlines.
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`33.
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`The ’132 patent specification also describes memory 20 as
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`having two subarrays, each referred to as “subarray 200.”
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`During a given RAS cycle, row and column addresses to a first
`subarray 200 are latched-in circuitry 208 with RAS and CAS
`through address pins Add0-AddQ and the desired access made
`through data pins DQ0-DQR. Subsequently, an access to a
`second subarray 200 would be made by latching in the
`appropriate row and column addresses with RAS and CAS
`through address pins Add0-AddQ and the access made through
`data pins DQ0-DQR.
`
`(Id., C9, L59-67, emphasis added.)
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`
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`Memory 20, and in particular those embodiments discussed
`above which allow independent accessing to each subarray
`200, is especially advantageous for use in systems employing
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`multiple asynchronous displays. In this case, one subarray
`200 services one display and the other subarray 200.
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`(Id., C12, L4-9, emphasis added.)
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`Here, consistent with the illustration in FIG. 2A, memory 20 has two subarrays,
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`each referred to as “subarray 200.” Again, the ’132 patent specification only
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`describes subarrays containing the same type of memory cells.
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`34.
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`In addition, the addressing circuitry for subarrays 200a and 200b
`
`in FIG. 2A are described in common as the addressing circuits for subarray 200.
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`During conventional accesses (reads, writes, read-modify-
`writes, refreshes) all gates 203 are turned off. Row and column
`addresses are input word (address)--serial from an external
`source with RAS and CAS (memory 20 may also be a
`synchronous DRAM operating to a master clock). In one
`embodiment of memory 20, row decoders 204 operate in
`response to separate sets of row addresses and column
`decoders 205 operate in response to separate sets of column
`addresses. In this embodiment, address pins Add0-AddQ and
`data pins DQ0-DQR can be organized in either of two ways.
`First, separate subsets of address pins Add0-AddQ and
`separate subsets of data pins DQ0-DQR can be dedicated to
`the row decoder 204 and column decoder 205 associated with
`each subarray 200.
`(Id., C9, L36-48, emphasis added.)
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`In a second embodiment, row decoders 204a and 204b lie in
`the same address space and respond to the same set of
`addresses received from an external source (e.g. core logic
`103) In this case, a bank select signal is used to select to which
`subarray 200a or 200b the desired access is to be made.
`Preferably, the column decoders 205a and 205b also lie within
`the same column address space and thus respond to the same
`set of column addresses, although this is not a requirement of
`the present invention.
`
`(Id., C10, L1-9, emphasis added.)
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`Here, row decoders 204 and column decoders 205 are used to access memory cells
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`in each subarray 200. In referring to FIG. 2A of the ’132 patent, row decoders 204a
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`and 204b correspond to row decoder 204 described above. Likewise, column
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`decoders 205a and 205b correspond to column decoder 205 described above. Since
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`these decoders are the same and operate in an identical manner when accessing
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`subarray 200, the addressing circuitry for subarrays 200a and 200b in FIG. 2A are
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`also identical.
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`35.
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`The above examples show that the ’132 patent specification only
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`contemplates the transfer of data between subarrays, where the subarrays include
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`the same type of memory cells. The ’132 patent specification does not disclose, nor
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`does it contemplate, the transfer of data between subarrays with different types of
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`memory cells.
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`36.
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`This conclusion is also supported by the understanding of the
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`term “multi-bank memory” and “bank” during the 1995 timeframe. The ’132
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`patent “relates in general to electronic memories and in particular to multiple-
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`bank memories and systems and methods using the same. (Id., C1, L7-9, emphasis
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`added.) Specifically, the ’132 patent specification describes memory 20 in FIG. 2A
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`in terms of a “bank” and a “subarray”: “[m]emory 20 includes an array of n
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`number of rows and m number of columns of memory cells partition[ed] into an
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`upper bank or subarray 200a and a lower bank or subarray 200b.” (Id., C7, L10-
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`12, emphasis added.) The specification also states that “the principles of the
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`present invention allow for the two banks of memory to be operated
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`asynchronously and independently.” (Id., 3:13-15, emphasis added.) Typically, a
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`memory bank is selected by one or more address bits, and the row and column
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`within that bank are selected by other address bits. A subarray includes memory
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`cells and can include any number of rows, columns and cells.
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`37.
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`During the 1995 timeframe, the term “bank” referred to a
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`partition of a memory array. Memory arrays were partitioned in multiple banks of
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`memory cells to increase speed and performance of the memory device.
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`An additional speed advantage sported by the JEDEC
`Standard Synchronous DRAM and the Rambus DRAM is
`multiple banks on a single RAM. The multiple banks permit
`faster random access by permitting one bank to precharge or
`be refreshed while the other bank is being accessed. Multiple
`rows on this part can be simultaneously open and accesses can
`be interleaved on the chip between the two banks.
`
`Multiple internal banks also help small fast systems with the
`memory granularity problem. Additional speed can be achieved
`by interleaving the banks on one chip rather than by
`interleaving multiple banks in the system which can add the
`cost of unneeded memory.
`
`(B. Prince, High Performance Memories, New Architecture
`DRAMs and SRAMs—Evolution and Function, John Wiley &
`Sons, 1996 (also referred to herein as “Prince 1996”), Ex. 2004,
`pp. 9-10, emphasis added.)
`
`Each bank in the multi-bank architecture includes the same type of memory cells.
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`In the above example, the memory cells are DRAM cells.
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`38.
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`This is in contrast to a memory architecture with a “mixed
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`memory” arrangement. The mixed memory arrangement does not comport to the
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`memory architecture described in the ’132 patent specification because the
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`physical structures of the SRAM cells and DRAM cells are different. (See ’132
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`patent, Ex. 1001, C11, L24-28.) For example, SRAMs have a larger physical
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`structure than DRAMs.
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`Since SRAMs have six devices per memory cell and DRAMs
`have effectively less than two, the SRAM cell area is about
`four times that of the DRAM cell in a similar technology. As a
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`result SRAMs tend to be at a quarter the density level of the
`corresponding DRAM generations so that the chips are of
`comparable size to improve the efficiency of manufacturing.
`
`(Prince 1991, Ex. 2005, p. 87, emphasis added.)
`
`39.
`
`A table in FIG. 3.2 of Prince 1991 further illustrates the
`
`differences among various semiconductor memory devices, including DRAM and
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`SRAM. The table shows that, in comparing relative sizes, SRAMs can be up to
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`four times larger than DRAMs.
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`FIG. 3.2 from Prince 1991 (Ex. 2005, p. 49)
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`In the 1995 timeframe, one of ordinary skill in the art would have
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`40.
`
`understood that a multi-bank memory system referred to a system with memory
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`banks having the same type of memory cells. For example, in FIG. 7.40(b) of
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`Prince 1991 (reproduced below), “an on-chip interleaved circuit . . . was used
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`which made it possible to read serial data continuously from two cell arrays
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`activated by two clocks. These arrays were selected alternately.” (Prince 1991, Ex.
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`2005, p. 363.) Each of the arrays illustrated in FIG. 7.40(b) is labeled as a “bank,”
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`which includes DRAM cells. (Id., pp. 362-363.)
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`FIG. 7.40(b) from Prince 1991 (Ex. 2005, p. 362)
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`
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`Here, storage of data in this multi-bank memory system is in memory banks with
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`the same type of memory cells (e.g., DRAM cells).
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`41.
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`In another example, in FIG. 7.23 from Prince 1996 (reproduced
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`below), “many small DRAM banks onto a single chip [are] all connected to a fast
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`common bus internal to the chip and controlled on chip for clock skew.” (Prince
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`1996, Ex. 2004, p. 210.)
`
`Speed is gained because a small DRAM is inherently faster
`than a larger DRAM in the same technology due to reduced
`wordline capacitance and shorter internal wiring. For example,
`the organization of the banks of the x 32 Mosys DRAM is 256
`x 32 x 32 compared with the organization of a 16M x 16
`DRAM which is 1024 x 1024 x 16. The 256 x 32 banks used in
`the Mosys DRAM in a 16M technology are individually faster
`than 2048 x 1024 bank of the 16M DRAM.
`
`(Id., emphasis added.)
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`FIG. 7.23 from Prince 1996 (Ex. 2004, p. 210)
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`Here, storage of data in this multi-bank memory system is in memory banks with
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`the same type of memory cells (e.g., DRAM cells).
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`42.
`
`Konishi confirms that, during the timeframe of the ’132 patent,
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`memory banks in a multibank system have the same type of memory cells. In
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`discussing prior art, Konishi states:
`
`In most MPU systems, the memories are adopted to have bank
`structure and interleaving is carried out on bank by bank
`basis in order to conceal the RAS precharge time (TRP)
`which is inevitable in the DRAM, in view of cost. By this
`method, the cycle time of the DRAM can be substantially one
`half that of specification value. The method of interleave is
`effective only when memories are sequentially accessed. When
`the same memory bank is to be continuously accessed, it is
`ineffective. Further, substantial improvement of the access time
`of the DRAM itself cannot be realized. The minimum unit of
`the memory must be at least 2 banks.
`
`When the high speed mode such as the page mode or the static
`column mode is used, the access time can be reduced
`effectively only when the MPU successively accesses a certain
`page (data of a designated one row). This method is effective to
`some extent when the number of banks is comparatively large,
`for example 2 to 4, since different rows can be accessed in
`different banks. When the data of the memory requested by the
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`MPU does not exist in the given page, it is called a “miss hit”.
`Normally, a group of data are stored in adjacent addresses or
`sequential addresses. In the high speed mode, a row address,
`which is one half of the addresses, has been already designated,
`and therefore possibility of “miss hit” is high. When the
`number of banks becomes as large as 30 to 40, data of
`different pages can be stored in different banks, and therefore
`the “miss hit” rate is remarkably reduced. However, it is not
`practical to provide 30 to 40 banks in a data processing system.
`In addition, if a “miss hit” occurs, the signal (/RAS) is raised
`and the DRAM must be returned to the precharge cycle in order
`to re-select the row address, which sacrifices the characteristic
`of the bank structure.
`(Konishi, Ex. 1004, 2:61-3:26, emphasis added.)
`
`In summary, Konishi describes a DRAM memory with multiple memory banks
`
`and how the memory banks can be used to minimize “miss hits.” These memory
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`banks, consistent with memory banks in other multibank memory systems
`
`described in the technical literature during the timeframe of the ’132 patent, also
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`had the same type of memory cells. In Konishi’s discussion above, these are
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`DRAM cells.
`
`43.
`
`It is revealing to note that, given Konishi’s disclosure of banks in
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`its background section, nowhere in his voluminous patent specification does he
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`refer to the terms “banks” (or “subarrays”) when describing his embodiments
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`such as, for example, Fig. 5. This is because the embodiments disclosed in the
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`Konishi references—e.g., SRAM array 2 and the DRAM array 1 in Fig. 5—are
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`not multibank systems. The terms “bank” and “subarray” are understood to refer
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`to groups of the same type of memory cells. The other reference cited by the
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`Board challenging the patentability of certain claims of the ’132 patent, the
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`Fujishima patent (Ex. 1005), never uses the term “bank” or the term “subarray.”
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`44.
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`Based on the above examples from the technical literature,
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`memory banks in a multibank system have the same type of memory cells. Also,
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`since subarray 200a and subarray 220b in FIG. 2A of the ’132 patent are associated
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`with an upper memory bank and a lower memory bank, respectively, these
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`subarrays also have the same type of memory cells. (See ’132 patent, Ex. 1001,
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`7:11-17.)
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`45.
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`Based on the description in the ’132 patent specification and
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`what was known to a person of ordinary skill in the art during the relevant
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`timeframe, the “banks” and “subarrays” described in the specification have the
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`same type of memory cells. To be more specific, in the context of the ’132 patent
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`specification, a multi-bank memory has multiple memory banks with the s
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