SEMICONDUCTOR
`MEMORIES
`
`A Handbook of Design, Manufacture, and Application
`Second Edition
`
`Betty Prince
`
`IV 2005
`IPR2014-00317
`
`

`
`Betty Prince is New Product Planning Manager for worldwide memory
`marketing at Texas Instruments. She previously worked for N V Philips
`as strategic memory marketing manager and as business manager for
`the static RAM part of the European Megaproject. She earlier worked at
`Motorola as memory strategic marketing and applications manager, as
`European memory marketing manager and as memory project
`engineering manager.
`
`Dr Prince has participated in the memory experts group of the European
`Electronic Components Association, has been on the Electronic
`Industry Association JEDEC memory committee for nine years, is
`chair'man ofthe JEDEC low voltage technical standards committee, and
`is a member of the IEEE. She holds several patents in the memory area.
`
`She has a BSc and MSc in physics from the University of New Mexico
`and California respectively, an MBA in international marketing and a
`PhD in economics from the University ofTexas.
`
`

`
`Semiconductor
`Memories
`Second Edition
`
`

`
`Semiconductor
`Memories
`A Handbook of Design,
`Manufacture and Application
`
`Second Edition
`
`Betty Prince
`Texas Instruments, USA
`
`JOHN WILEY & SONS
`Chichester
`• New York
`• Brisbane
`
`• Toronto
`
`• Singapore
`
`

`
`Second edition of the book Semiconductor Memories by B. Prince and G. Due-Gundersen
`
`Copyright © 1983, 1991 by John Wiley & Sons Ltd.
`Baffins Lane, Chichester
`West Sussex P019 IUD, England
`
`All rights reserved.
`
`No part of this book may be reproduced by any means,
`or transmitted, or translated into a machine language
`without the written permission of the publisher.
`
`Other Wiley Editorial Offices
`
`John Wiley & Sons, Inc., 605 Third Avenue,
`New York, NY 10158-0012, USA
`
`Jacaranda Wiley Ltd, G.P.O. Box 859, Brisbane,
`Queensland 4001, Australia
`
`John Wiley & Sons (Canada) Ltd, 22 Worcester Road,
`Rexdale, Ontario M9W Ill, Canada
`
`John Wiley & Sons (SEA) Pte Ltd, 37 Jalan Pemimpin #05-04,
`Block B, Union Industrial Building, Singapore 2057
`
`Library of Congress Cata/oging-in-Publication Data
`
`Prince, Betty.
`Semiconductor memories I Betty Prince. -
`p.
`cm.
`Includes bibliographical references and index.
`ISBN 0 471 92465 2
`1. Semiconductor storage devices.
`TK7895.M4P74 1991
`62I.39'732--dc20
`
`I. Title.
`
`2nd ed.
`
`91-6943
`ClP
`
`British Library Cataloguing-in-Publication Data
`
`Prince, Betty
`Semiconductor memories. -
`I. Title
`621.3815
`
`ISBN 0 471 92465 2
`
`2nd ed.
`
`Typeset by Techset Composition Limited, Salisbury, Wiltshire
`Printed in Great Britain by Courier InternationaL East Kilbride
`
`

`
`3 TRENDS IN MEMORY
`APPLICATIONS
`
`3.1 VARIETIES OF DATA STORAGE DEVICES BY MEDIA
`
`Over the years many different media have been tried for the basic data storage
`function as shown in Figure 3.1. Logical bits have been stored in mechanical devices
`such as paper tape and cards, in magnetic moving media such as bubbles, hard disks,
`floppy disks and core, in optical moving media such as magneto-optical disk and
`holographic devices, and in solid state media which include semiconductors and
`ferroelectrics. Semiconductors divide by technology into MaS, bipolar and charge
`coupled devices, and by function into RAM, ROM, and SAM. MaS and bipolar are
`available in all three functions, while charge coupled devices are available only as SAM.
`
`3.2 FUNCTIONAL CHARACTERISTICS OF VARIOUS SEMICONDUCTOR
`MEMORIES
`
`The basic differences in function in semiconductor memories have come about as a
`result of specific requirements of the differing systems applications in which they are
`used. No single set of memory characteristics is optimal for all systems, nor has any
`single memory yet been made which has all of the optimum characteristics.
`Functional characteristics that are significant for the systems environment include
`performance (speed), power dissipation (heat), memory density (number of storage
`bits per chip), chip size (memory cost), size of package (system cost), external
`organization of the memory, reprogrammability (endurance of the memory to repeated
`write-erase cycles), long term reliability characteristics, ability to retain data when
`the power is off (volatility), length of time the data is retained when dc power is
`on without an active refresh of the data (data retention), interface voltage levels into
`the system (TTL, ECL, CMOS), optimal power supply voltage levels, moisture
`resistance (hermeticity) of the package, and the amount of logic integrated on the
`memory rather than used separately in the system.
`There are several major product types of semiconductor memories differing by
`various sets of these characteristics. This was determined historically by the basic
`
`

`
`FUNCTIONAL CHARACTERISTICS OF VARIOUS SEMICONDUCTOR MEMORIES
`
`49
`
`~ala'IO"g'med~
`
`Mechanical
`
`Moving media
`
`Solid state
`
`/\
`/ \
`lape /1 /1 If\ 1\
`
`Paper Punch
`
`Magnetic
`
`Optical
`
`Semiconductor
`
`Ferroelectric
`
`Bubble Hard
`disk
`
`Floppy Compact Holographic MOS Bipolar CCD FE-MOS Core
`disk
`disk
`
`Figure 3.1
`Various catagories of data storage devices.
`
`Characteristic
`
`DRAM
`
`SRAM
`
`EPROM
`
`ROM
`
`EEPROM
`
`NVRAM
`
`Number of devices
`in cell
`Relative cell size
`Density (1990)
`Overhead cost
`
`Volatile
`(power off)
`Data retention
`(d.c. power on)
`In system
`reprogram mabie
`Number of
`reprogram times
`(endurance)
`Typical write
`(Reprogram) speed
`Typical read
`speed (ns)
`Number of
`read cycles
`
`1.5
`
`4-6
`
`"1.5
`
`1.0
`
`2.5
`
`8-9
`
`1.5
`4Mb
`yes
`refresh
`logic
`yes
`
`4-6
`1Mb
`no
`
`yes
`
`"1.5
`4Mb
`
`1.0
`4Mb
`yes
`yes
`mask
`UVerase
`programmer charges
`no
`no
`
`4ms
`
`Cf)
`
`10 years
`
`yes
`
`yes
`
`no
`
`Cf)
`
`Cf)
`
`100
`PROM(1)
`
`Cf)
`
`no
`
`0
`
`~ 9-10
`1Mb
`16k
`no
`no
`
`no
`
`no
`
`10 years
`
`10 years
`
`yes
`
`yes
`
`10000
`-1000000
`
`10000
`XJ (write)
`
`100 ns
`
`25 ns
`
`30 min
`
`2.5 s
`
`100
`
`25
`
`100
`
`100
`
`200
`
`200
`
`Cf)
`
`Cf)
`
`.X)
`
`Cf)
`
`Cf)
`
`Cf)
`
`Figure 3.2
`Characteristics of MOS memory product types.
`
`

`
`50
`
`TRENDS IN MEMORY APPLICATIONS
`
`memory cell. Semiconductor memories are split by major cell type into DRAMs,
`SRAMs, SAMs, EPROMs, EEPROMs, and ROMs. General characteristics of the basic
`MOS memory types are shown in Figure 3.2. Minor variations include the NVRAM
`and the CAM.
`The structure of the memory array and periphery determines the input and output
`organization. The logic in the periphery also determines functional subcategories of
`memories such as video and multi-port DRAMs, synchronous and asynchronous
`SRAMs.
`A further subset is defined by the Input and Output (I/O) levels and configuration
`of the memory. I/O levels can be TTL, ECL, or CMOS. Inputs, outputs, and addresses
`can be multiplexed or non-multiplexed, serial or parallel.
`
`3.2.1 MOS memory selection by system requirement
`
`Different systems require different MOS memory characteristics. For example, a
`memory system requiring an infinitely reprogrammable memory would use an SRAM
`or a DRAM. If it is a large memory system with commercial cost pressure then it
`will use the highest density, lowest cost option-the DRAM. If it is a large very fast
`system requiring a random read access memory, then it will either use SRAM for the
`main memory or have a small SRAM cache which can make a lower cost but slower
`DRAM memory appear faster in the system. If it is important that the main memory
`not lose its data when the power fails,
`there are again several options. Either
`SRAM can be used for the main memory due to its low standby power dissipation
`and backed up by a battery, or the main memory can be backed up by an EEPROM.
`As another example a system which needs a small quantity of fast infinitely writable
`non-volatile memory will use an NVRAM, bearing in mind that its non-volatile
`reprogrammability is the same as the EEPROM-about 10 000 reprogram cycles.
`In general DRAMs and EPROMs tend to be optimized for high density and low
`cost and used in large systems where many parts need to be assembled in a small
`space. The large quantity of parts used mean that the per-unit overhead costs are low.
`DRAMs have the lowest cost of any RAM and the highest density because they
`have the smallest memory cell, consisting of one transistor and a capacitor. The
`capacitor stores the charge when the memory is in the' l' state. The capacitor occupies
`a large percentage of the room in the memory cell. In high density DRAMs it is
`usually either stacked on top of the transistor or lowered into a narrow trench in the
`silicon. A DRAM, therefore, effectively has a one plus transistor cell area.
`The penalty that is paid for this small cell size and consequent high density is the
`need for the memory system to provide a periodic refresh to the cell to restore the
`charge to the capacitor as it leaks away. During the time that the memory cell is being
`'refreshed' no other operation can take place in that area of the array. This' dead
`time' slows down the effective speed of the DRAM in the system. While the
`percentage of the operating time that is occupied with refresh is decreasing as higher
`quality capacitors are constructed, refresh is still a significant factor in the timing of
`the system.
`All of the capacitors in the memory array must be periodically refreshed. This is
`done by accessing each row in the array, one row at a time. When a row is accessed,
`
`

`
`FUNCTIONAL CHARACTERISTICS OF VARIOUS SEMICONDUCTOR MEMORIES
`
`51
`
`it is turned on and voltage is applied to the row. This recharges each capacitor on
`the row to its initial value. For example, on a 1Mb DRAM refresh can be performed
`as either a single burst of 512 consecutive refresh cycles (one cycle per row) every
`8 ms, or it can be distributed over time, that is, one 200 ns refresh cycle every 15.6 fls
`(8 ms per 512 rows = 15.6 fls per row). A combination of these two methods is also
`permitted as long as each row is refreshed at least every 8 ms. Details of refreshing
`the DRAM will be considered in Chapter 6. The requirement for refresh does, however,
`add to the complexity of the system and hence to the overhead cost of a system
`using DRAMs.
`EPROMs also have an overhead cost. They are erasable, but must be removed
`from the system and placed in an ultraviolet light which erases the memory through
`a transparent window in the EPROM package. They must then be reprogrammed in
`a separate programmer before being returned to the system. This makes EPROMs
`cumbersome to use.
`SRAMs and EEPROMs, on the other hand, are easy to use from the system
`sophistication viewpoint and do not have the overhead costs, but are more expensive
`per unit. In a small system where the cost of system overhead is a relatively
`higher part of the system cost, the total cost of the SRAMs and EEPROMs moves
`closer to that of the DRAMs and EPROMs, and the determining factor becomes the
`ease of use.
`Where in-system reprogrammability is required, neither EPROMs, nor ROMs
`can be used: however systems requiring data to be retained when the power goes off
`must use one of the non-volatile memories~ROMs, EPROMs, EEPROMs, non(cid:173)
`volatile RAMs, or CMOS SRAMs with battery back-up. If the high performance
`of the semiconductor memory is not required these applications can also use one of
`the slower non-volatile moving media or mechanical memory types.
`ROMs and EPROMs are used primarily to hold software which will not be changed.
`In lower densities and speeds, they were used mainly for holding setup and
`configuration data for peripheral or bootstrap programs. As higher speeds and densities
`appeared they were used to hold entire operating systems, real-time kernels and canned
`applications programs, and in consumer toys and games.
`Battery backed up SRAMs (BRAMs) are used for applications in peripherals
`requiring high speed random access combined with non-volatility. The parts, devel(cid:173)
`oped first by Mostek, contain lithium batteries in a compartment of the SRAM
`package. They also contain various types of voltage sensing circuits that switch over
`to the batteries when external power is removed.
`With relatively small numbers of setup parameters needing to be sorted and changed
`only occasionally, non-volatile SRAMs, which are also called shadow RAMs, can be
`used. These combine RAM and EEPROM on one chip. BRAMs can also be used.
`Shadow RAMs (developed by Xicor) combine a normal static RAM array with an
`EEPROM array. When the chip is powered up, the contents of the EEPROM are
`written into the RAM, providing default configuration parameters. These parameters
`can be changed while the system is on, and the EEPROM can be reprogrammed to
`change the default setting.
`Other characteristics are common choices to all the memory types but differ in
`various system applications, such as organization of the memory, common or separate
`
`

`
`52
`
`TRENDS IN MEMORY APPLICATIONS
`
`inputs and outputs, and whether the memory is synchronous or asynchronous. Depth
`of memory required in the system affects the required organization of the memory
`and also the width of memory word, or number of inputs and outputs. Considerations
`of bus width and error correction are often important determiners of desired memory
`width. Whether a memory is required to be synchronous or can be asynchronous can
`be determined by the presence or absence of a system clock, the desired speed
`of the system, and the required retention of the last accessed data while new
`data are incoming.
`
`3.3 MEMORY USAGE IN COMPUTER APPLICATIONS
`
`To see how differing systems applications require these differing characteristics, a few
`typical systems using memories from various end system market segments are
`considered now.
`Figure 3.3 divides the total memory usage for DRAMs and SRAMs in major
`applications segments for 1988 and forecast for 1992.
`
`1988
`$6.256 billion
`
`PCsond
`office
`automation
`53%
`
`(a)
`
`Other
`computer
`24%
`
`Telecom
`8.8%
`
`1992
`$8.972 billion
`
`PCs ond
`office
`
`Telecom
`--\!!!-- 10. 3 %
`
`Industrial/
`other
`7.1%
`Consumer
`8.6%
`
`Consumer
`5%
`
`Military
`3.5%
`
`1988
`$1.712 billion
`
`1992
`$2.644 billion
`
`PCs and
`office
`
`PCs and
`office
`Other com~uter automation
`22.8:b
`39%
`
`(b)
`
`Consumer
`5%
`
`Industrial/
`other
`15%
`
`Industriall
`
`Telecom
`7.5%
`
`Consumer
`10%
`
`Figure 3.3
`(a) DRAM and (b) SRAM usage by user market segment for 1988 and 1992. (From HTE
`Research Inc.)
`
`

`
`MAINFRAME STORAGE HIERARCHIES
`
`53
`
`Computer application is both the largest of the electronic systems market and also
`uses the highest average value of memory per system. As a result 73% of all memories
`go into some type of computer system. These include mainframes, supercomputers,
`parallel processing systems and graphics workstations.
`
`3.4 COMPUTER STORAGE HIERARCHIES
`
`Throughout the 1980s there was an increasing mismatch between the speed of the
`DRAMs, which are used for main memory, and the speed of the microprocessors,
`used as computing elements in all but the largest computers. Figure 3.4 illustrates this
`for the RISC (reduced instruction set computers), CISC (complex instruction set
`computer), MPU (microprocessor units), and for four generations of DRAM. Fast
`SRAM speeds increased at the same rate as that of the processors. A hierarchy of
`storage layers divided by speed developed.
`A typical computer storage hierarchy is shown in simplified form in Figure 3.5.
`Indications are given of memory types frequently used at each level. Memory is
`organized in several layers of decreasing speed going from fast cache to slow archival
`memory. Progress in mass storage technology continues to add layers to the traditional
`system storage hierarchy.
`If infinite amounts of low cost, random access, non-volatile memory bits were
`available at the speed required by the processors with no wait states, there would be
`little reason to use differing types of memory. Since this is not the case, memory
`hierarchies are used to provide a reasonable facsimile of the ideal memory in the
`system.
`
`100
`
`50
`
`20
`
`10
`
`5
`
`2
`
`N
`I
`::2
`
`w
`....J
`<.J
`>-
`<.J
`
`o Rise
`• else
`• DRAM
`
`20
`
`50
`
`'" c
`
`100
`
`200
`
`300
`
`82 83 84 85 86 87 88 89 90
`YEAR
`
`Figure 3.4
`Speed trends of MPUs and DRAMs. (From Kushiyama [29], Toshiba 1991, with permission
`of IEEE.)
`
`

`
`54
`
`TRENDS IN MEMORY APPLICATIONS
`
`First
`level
`cache
`
`SRAM
`
`Main memory
`
`DRAM
`
`Archive I
`
`Mognetic disk/
`magnetic tope
`
`Archive II
`
`Optical disk
`
`Figure 3.5
`Typical computer system data storage hierarchy.
`
`3.4.1 Main memory
`
`The storage hierarchy exists to support the main memory. The storage device used
`most frequently as main memory in large computers is the dynamic RAM. This
`is because the DRAM is optimized for low cost and high density, which are the major
`needs when fitting very large quantities of memories into a system. What is traded
`off is a higher cost in system overhead needed to refresh these dynamic RAMs,
`volatility, and a speed penalty.
`When it is necessary to interface a fast processor with a slower memory, the
`processor is slowed down since its cycle time is faster than the memory address access
`time. One of the ways to handle this interface situation is to use a cache to decrease
`the effective time to access the main memory.
`
`3.4.2 Overview of cache
`
`Cache memories are buffers that hold selected information from larger and usually
`slower main memory so that processors can reach this information more rapidly.
`The cache is based on the principle that certain information has a higher probability
`at any given time of being selected next by the processor than other information. If
`these higher probability data are stored in a cache with a faster access time then the
`average speed of access of the data will be increased.
`There is a trade off between memory performance, size, and cost, which encourages
`
`

`
`MAINFRAME STORAGE HIERARCHIES
`
`55
`
`system designers to find ways to use memory more efficiently. System designers have
`historically had two choices available in RAM memory devices: fast and expensive
`SRAMs or slow and cheap DRAMs. While SRAMs with 25-35 ns access times can
`keep pace with a 10 MHz processor, a DRAM with even 80 ns access time will force
`this same processor to wait. Given the large size requirement in current memory
`arrays, the importance of finding an optimum trade-off between size and performance
`is, however, of increased importance.
`Caching schemes are common which mix a large amount of slower less expensive
`DRAM with a small amount of faster more expensive SRAM. A variety of such
`schemes can be constructed to allow the processor to operate at maximum speed, and
`are a way to ensure that the data a processor needs will be available when the
`processor needs it without having to wait for the data to be read from their normal
`location in main DRAM memory.
`In general most caches are designed on the assumption that a processor is likely
`in the near future to need the information it is currently working on, plus other data
`which are stored near it in the main memory. Cache performance depends on two
`factors: access time and hit ratio.
`The hit ratio is defined as the probability of finding the needed information in the
`cache, which is a hit, divided by the probability of having to go to the main memory,
`which is a miss. This hit ratio, which is the ratio of the number of hits divided by
`the number of tries, is dependent on the size of the cache and on the number of bytes
`that are brought in on any given fetch from main memory.
`The access time for the cache is the mean time it takes to access the cache on a
`hit. The access time for the main memory must include the initial attempt to find the
`data in the cache. The overall performance of the memory system will then be a
`function of the cache access time, the cache hit ratio and the access time of the main
`memory for references that are not found in the cache.
`There are two general types of caches: a direct mapped cache and an associative
`or tag cache.
`
`3.4.3 Direct mapped cache
`
`The contents of a direct mapped cache correspond exactly to the data that were
`obtained from main memory and are addressed by the same addressing scheme as
`the main memory. The latest data obtained are normally retained by the cache along
`with adjacent data from the main memory. The least used data in cache at the time
`are replaced by the latest data.
`Direct mapped caches are used primarily with smaller main memory having
`direct address mapping schemes. Most direct mapped caches consist of small amounts
`of SRAMs embedded in microprocessors.
`
`3.4.4 Associative cache
`
`An associative cache, also called a cache tag comparator, is more useful with large
`memory systems which include large main memory and perhaps even lower levels
`of archival storage.
`
`

`
`56
`
`TRENDS IN MEMORY APPLICATIONS
`
`Frequently these large memory systems are organized as demand paged virtual
`memory in which memory is organized in pages of a fixed size that have a given
`virtual address. Pages beyond the range of existing physical RAM can be stored in
`large, slower archival memory, usually disk. and swapped into physical RAM when
`needed and where space is freed by another page being swapped back to disk. (In
`this case the main memory also acts as a cache for the disk.) When pages reside in
`physical memory, they also have a physical address which is different from their
`virtual address.
`There is a trade-off in page size between the frequency with which one must swap
`pages from the disk and the time it takes to make such a swap. A memory management
`unit (MMU) is used to translate between virtual and physical addresses. Addresses
`are organized in terms of a page address, called a 'TAG', and an 'offset' which locates
`the data within that page.
`An associative cache, upon receiving an address from the processor, associates or
`compares the TAG with the page address to see if that page address is in cache. If
`so, the offset address is checked and if there is a 'hit'. that is, if the data are in the
`cache, they are immediately transferred from the cache to the processor.
`An example of a single set associative cache is shown in Figure 3.6. This cache
`includes a TAG indicating the page address of data stored in the cache, the offset
`address which locates the data within the page, and the actual data. When a request
`is received from the processor, the TAG field in the address requested is compared
`to the TAG field of data held in the cache. If the TAG field is valid and the page
`offset is present then the data in the cache are returned to the processor.
`
`Processor
`
`r----------------
`I
`I
`I
`No I Comparator J
`
`Address
`I
`
`I
`
`Yes t
`Offset
`
`Tog
`
`Data
`
`l-
`
`I
`I
`I L __________________
`_.J
`
`Main memory
`
`I
`
`Figure 3.6
`Single set associative cache.
`
`

`
`MAINFRAME STORAGE HIERARCHIES
`
`57
`
`A two-way set associate cache would allow the same offset from two different
`pages to be cached. A fully associative cache would allow any number of pages to
`be cached. A fully associative cache is, however, more complex and hence more
`expensive than a simpler cache.
`Cache hierarchies historically included a processor, main memory, and a cache to
`buffer the speed of the main memory for input to the processor. Now cache hierarchies
`can be multilevel with fast processor, cache 1, virtual main memory, cache 2, and
`archive memory. Speeds range down from a few tens of nanoseconds for the first-level
`cache to a few milliseconds for the archive.
`
`3.4.5 Application-specific cache chips
`
`A cache can be constructed of logic and RAM chips or it can be bought as an SRAM
`with the logic integrated on the chip. A number of applications specific SRAMs are
`available as caches for memory systems, although there is always a trade-off for the
`system designer between using a more expensive cache chip, or buying less expensive
`standard SRAM and implementing the cache logic off-chip.
`Many levels of sophistication are possible in cache design, usually determined by
`the speed requirements and cost constraints of the system.
`
`3.4.6 Dual-port SRAMs as cache buffers
`
`An ideal cache could be accessed simultaneously by both a processor and another
`processor or a peripheral. This could result in bus contention unless the cache had
`two ports and the stem had two independent buses.
`Even with two ports, an ideal cache buffer would need to be able to handle both
`external processors accessing the same address simultaneously without resulting in
`indeterminate data in the cache if one processor was attempting to read when another
`was writing to the same location. In reality, this situation is frequently handled by
`having a wait state for one of the processors or by allowing the possibility of having
`information incorrect. Contention arbitration logic can be provided to eliminate
`overlapping operations to the same memory location. It can either allow contention
`to be ignored and both operations to proceed, or it can arbitrate and delay one port
`until the other port's operation is completed. When this occurs, a busy flag is sent
`to the side delayed. A priority port can be specified. Another problem that arises is
`having different width buses on the processor and the peripherals side of the dual port.
`
`3.4.7
`
`Interleaving memory to gain system speed
`
`An additional option for the fast processor and slow memory combination is
`interleaving the memory to increase the data rate. The most basic type of interleaving
`scheme is the two-way interleave in which odd addresses are stored in one memory
`
`

`
`58
`
`TRENDS IN MEMORY APPLICATIONS
`
`array and even addresses are stored in another. The first access will be at the speed
`of the memory array, but consecutive accesses from separate blocks will be at about
`twice the speed of the memory arrays.
`This works best in the case of consecutive addressing from the processor where
`there is a high level of interleaving. This scheme works since consecutive fetches are
`directed at alternate memory banks so there is a time penalty only on the first access.
`For example, two 100 ns memory arrays could be interleaved to give an average
`access time close to 50 ns, rather than using a more expensive 50 ns memory.
`The simple two-way interleaving scheme totally fails if, for example, complex
`numbers are being used where the real and imaginary parts are accessed consecutively
`but stored separately. Since each address access involves both memory arrays, the
`time advantage of alternating slower arrays disappears, leading to a failure of the
`interleaving scheme. A four-way interleave solves this problem. The interleaving
`scheme helps to speed up both instruction and data fetches from memory.
`Caches and interleaving can also be combined, for example, to speed up instruction
`fetches in time to be executed when needed. Ideally, the fetching would occur on
`machine cycles where no other task is using main memory. The cache memory acts
`as a buffer between the main memory and the control unit, greatly reducing the
`memory bandwidth consumed by instruction fetches.
`
`3.4.8 Archive or mass storage
`
`In addition to main memory and cache, system requirements for more memory and
`for higher capacity peripherals have resulted in the use of a variety of storage devices
`whose main requirements are very high density, very low cost, and non-volatility.
`These include magnetic disk, floppy disk, optical disk, and magnetic tape. Optical
`disks are available in three forms which include optical read-only-memory (ROM),
`optical write-once-read-many (WORM), which is a PROM, and most recently optical
`multiwrite, which is a form of EEPROM.
`Reel-to-reel has mostly been replaced by tape cartridges. Hard disks are not being
`displaced because their capacities continue to increase and their size to shrink. For
`example, the 5 ~ inch hard disks have increased from the 10 to 20M byte capacities
`common in the mid 1980s to 200Mbyte and higher in 1989, while 14 inch hard disks
`now have capacities in the gigabyte range.
`Interface standards for optimizing the speed and transparency of links between
`computers and peripherals have developed, such as SCSI (Small Computer System
`Interface) which is used primarily for small systems and IPI which was developed for
`larger systems. These interface standards allow designers to optimize the storage
`capacities of their devices.
`To accommodate these additional options the system I/O interface must become
`more flexible and supply faster data transfers.
`Solid state memory is still too expensive to be a major contender for most mass
`storage applications. It is, however, used in special applications whose reliability
`requirements preclude the use of mechanical storage systems. Since the cost per bit
`
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`MEMORIES FOR VIDEO PROCESSING
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`59
`
`of MOS memory continues to drop faster than that of the older media, an increasing
`number of applications could potentially be filled with MOS memory in the future.
`The low cost DRAM and flash memories are the main contenders among the MOS
`memories for a share of the archive memory market.
`
`3.5 SUPERCOMPUTERS AND PARALLEL PROCESSORS
`
`Performance in today's supercomputers is determined in part by the high performance
`communications networks connecting the various processors in the total computer
`system. Supercomputers run in parallel processing type clusters linked by these high
`speed networks.
`Applications where parallel processing makes sense include those where a massive
`amount of data must be processed, for example, image processing. The quantity of
`information represented by a typical digital image means that the total processing
`time is likely to be minutes or hours for a single image when a Single micro- or
`miniprocessor is used. The use of parallel processing can Significantly reduce the time
`for such computations.
`Parallel processors also require parallel input-output capabilities and mass storage
`arrays that bring enough I/O and disk performance to match the required levels of
`computational performance.
`Since speed is critical in these super fast systems, circuit elements need to be as
`close as possible to shorten the length of interconnects. Some supercomputer systems
`use high density cassettes of SRAM memory chips without packages to create the
`high density memory arrays needed. Other systems embed the data storage and data
`acquisition subsystems modules in the array of processors. In either case significantly
`enhanced computational power results so that complex processing of analog data
`becomes possible at very high speeds. Image and signal processing are among the
`possible applications.
`
`3.6 MEMORIES FOR VIDEO PROCESSING AND GRAPHICS WORKSTATIONS
`
`The advent of the microprocessor in the 1980s increased the demand for memories
`in small systems such as personal computers, word processors, computer terminals,
`work stations and CAD-CAM systems. The applications of RAMs in small systems
`can largely be divided into main memory and display memory.
`The ratio of number of RAMs used in display memories for storing character data
`and processing graphic data to the number used in the main memory is much larger
`in small systems than in mainframe systems, and in fact in small systems the number
`of display memories is on a par with the number of memories used in the main
`memory of the small system.
`The size of display memories per system ranges from several tens of kilobytes to
`as many as several megabytes. It is expected that during the 1990s a significant
`percentage of DRAMs will be used for display purposes. Display memories use
`
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`60
`
`TRENDS IN MEMORY APPLICATIONS
`
`standard DRAMs integrated into the system with stand-alone logic chips and also
`include several applications specific DRAMs such as frame buffers and video DRAMs
`for bit-mapped displays.
`The basic function of a frame buffer is to send display data to the video display
`monitor at a designated speed. The performance level of a system is determined by
`the efficiency with which the processor can refresh the display data while continuing
`this basic function. A frame buffer works best with two access ports. One port intakes
`new data from the CPU and the other sends display data to the CRT.
`There are two ways to use a standard single port DRAM in this application. One
`is to permit the CPU access to the DRAM only during the blanking phase of the
`display as illustrated in Figure 3.7(a). CPU access during the data display phase is
`restricted to sending display data to the CRT. This r