==-= =;!)
`~ ~fTI, Technical .... sclosure BulletinVol. 32 No. BA
`
`January 1990
`
`METHOD TO INCORPORATE THREE SETS OF PATTERN INFOR}~TION IN TWO PHOTO(cid:173)
`MASKING STEPS
`
`F . 9 .
`
`1
`
`F. 9. 2
`
`F . 9 . 3
`
`By hardening a first image in a first photoresist (PR) layer and just
`developing a second
`image in· a
`thicker second PR layer, coincident
`openings in the
`two PR layers provide a first pattern. Oxygen ion
`etching is then used to remove portions of the first layer of photo(cid:173)
`resist which are unprotected by
`the second photoresist layer,
`thus
`
`©IBM Corp. 1990
`
`218
`
`SAMSUNG-1003.001
`
`

`
`METHOD TO INCORPORATE THREE SETS OF PATTERN INFORMATION IN TWO PHOTO-
`MASKING STEPS
`Continued
`
`providing a second pattern. Blanket exposing and developing away all
`of the remaining second photoresist provides a third pattern. Thus,
`three patterns are created having an overlay tolerance of a single
`alignment. Useful applications
`include creating
`three different
`thicknesses of metallized patterns within one
`level of dielectric
`material.
`
`Referring to Fig. 1, a first photoresist layer 2 is deposited on
`substrate 4. Openings having width A and width B are formed in photo(cid:173)
`resist 2 by exposure
`to a first mask and development. Remaining
`photoresist 2
`is
`then hardened, e.g., by a heat
`treatment. Next,
`photoresist 6 is applied and exposed
`to a second mask whereupon an
`opening having width C is created by exposure and development. A
`pattern defined by coincidence of openings having width A and C (D)
`can then be etched in substrate 4. The pattern having width D could
`be a via hole in a dielectric substrate 4 for a
`level-to-level in(cid:173)
`terconnection.
`
`Referring to Fig. 2, a reactive oxygen ion etching process is
`used to remove all of photoresist 2 which is not covered by photore(cid:173)
`sist 6 while an inconsequential amount of photoresist 6 is also re(cid:173)
`moved. There is then an unprotected pattern of substrate 4 having
`width C which can be etched to define a part of an upper level of
`wiring connecting
`to an interlevel connector in the region having
`width D.
`
`Referring to Fig. 3, all rema~n~ng photoresist 6 is removed by a
`blanket exposure and development,. A pattern comprised of openings
`having width A + C ~ E and B in photoresist 2 may now be etched into
`substrate 4. Remaining photoresist is removed to complete the cross
`section shown in Fig. 3. The pattern having width B could be used to
`construct a
`thin fuse link which can be electrically blown. Another
`application of the pattern having width B is for monitoring planariz(cid:173)
`ing processes. Either planarization end point or planarization uni(cid:173)
`formity may be detected by appropriate design of the shape of the
`region having width B.
`
`Conformal deposition of a conductor and planarization complete
`the applications described.
`
`219
`
`Vol. 32 No. SA
`
`January 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.002
`
`

`
`::=::=:::::.=1)
`J. ===-,r~ Technical uisclosure Bulletin
`
`Vol. 33 No. 2 July 1990
`
`DUAL-IMAGE RESIST FOR SINGLE-EXPOSURE SELF-ALIGNED PROCESSING
`
`FIG. 1
`
`5
`
`FIG. 2
`
`FIG. 3
`
`5
`
`9
`
`9
`
`3
`
`3
`
`4
`
`4
`
`This article describes a resist system having a wet developable first
`image and a dry developable second image (based on silicon incorpor(cid:173)
`ation through a silylation step). A novel material/process approach is
`described which simplifies device
`fabrication
`through self-aligned
`dual-image lithography.
`
`©IBM Corp. 1990
`
`447
`
`SAMSUNG-1003.003
`
`

`
`DUAL-IMAGE RESIST FOR SINGLE-EXPOSURE SELF-ALIGNED PROCESSING -
`Continued
`
`5
`
`FIG. 4
`
`FIG. 5
`
`4
`
`3
`
`4
`
`Dual-tone resists (positive or negative working depending upon the
`choice of wavelength and developer) are useful to a degree for self(cid:173)
`aligned processes where elements of
`two separate patterns are
`to be
`placed on a substrate in a single masking step and developed out sepa(cid:173)
`rately. They are limited in use, however, since the resist must sur(cid:173)
`vive
`the first process unaffected in order
`to allow the subsequent
`development of
`the second latent image and completion of
`the second
`process. Where
`the first process is a harsh one, such as metal RIE
`(reactive ion etch), the effects of ion and electron bombardment, UV
`radiation, heat, polymer deposition, etc., act to prevent proper de(cid:173)
`lineation of the second image, i.e., development of the second latent
`image.
`The
`technique here disclosed is capable of high resolution
`imaging, successfully overcoming
`the prior noted difficulties while
`achieving the objective of sequentially delineating, on a wafer,
`two
`separate self-aligned patterns from a single mask exposure.
`
`The material used for resist is one which, when exposed to radi(cid:173)
`ation of wavelength :U, acts as a positive working, wet developing
`resist and, when exposed to radiation of wavelength \2, acts as a posi(cid:173)
`tive working, dry developing (developed by oxygen plasma) resist. One
`mask containing the elements of
`two patterns is used, where a first
`pattern (p1) is defined by areas which transmit the wavelength \1, and
`the second,
`(p2), is defined by areas which transmit
`the wavelength
`2, or some combination of \1 and \2. The disclosed dual-imaging tech(cid:173)
`nique is illustrated by Figs. 1 - 5, where it is applied to a self(cid:173)
`aligned 1st metal and 1st to 2nd stud definition process.
`
`448
`
`Vol. 33 No. 2 July 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.004
`
`

`
`•
`
`DUAL-IMAGE RESIST FOR SINGLE-EXPOSURE SELF-ALIGNED PROCESSING -
`Continued
`
`Fig. 1 shows a mask 1, a dual-image resist layer 2, and Al-Cu
`metallization layers 3 and 4 (deposited 1 urn each), separated by an
`intermediate layer 5 of chromium or titanium/tungsten (200-300 ang(cid:173)
`stroms) as a metal RIE stop (optional). These three depositions can be
`done in sequence using a single metal deposition tool. The mask 1 will
`be noted to contain the elements of two patterns, the first 6 trans(cid:173)
`missive to wavelength A1, and the second 7 transmissive to wavelength
`>.2. A central section 8 is opaque to both Al and ).2,
`
`Following exposure
`in Fig. 2 is presented.
`of the remaining resist
`
`to >.1 and wet development, the structure shown
`Only silylites remain in the unexposed area 8
`9.
`
`One urn of metal is removed by RIE to obtain the structure shown in
`Fig. 3, the metal etch stop layer 5 acting to maintain a smooth surface
`on 4 during the etch process.
`
`A dry etch (oxygen plasma) is next performed to remove resist 9,
`resulting in the structure shown in Fig. 4. This is followed with an
`RIE to remove another urn of metal 3 in order to obtain the self-aligned
`1st metal and 1st to 2nd stud structure shown in Fig. 5.
`
`The process illustrated proves useful for the simultaneous defini(cid:173)
`tion of two levels of metallization, offering a capability for tighter
`ground rules and improved performance in a broad range of applications.
`Obvious modifications of the disclosed technique include the employment
`of a variable dose mask instead of the variable wavelengths of trans(cid:173)
`mission used. Multiple layer resist materials composed of layers sen(cid:173)
`sitive to differing wavelengths of transmission could also be used, as
`could resist layers containing silicon or capable of being silylated,
`to further simplify device fabrication.
`
`Vol. 33 No. 2 July 1990
`
`IBM Technical Disclosure Bulletin
`
`449
`
`SAMSUNG-1003.005
`
`

`
`-
`
`§~~=~(D
`===,= Technical LJisclosure Bulletin
`
`Vol. 33 No. 3A August 1990
`
`COMPLEMENTARY SELECTIVE WRITING BY DIRECT-WRITE E-BEAM/OPTICAL LITHO(cid:173)
`GRAPHY USING MIXED POSITIVE AND NEGATIVE RESIST
`
`FIG. I
`
`D
`
`c::=J DIRECT· WRITE
`
`E·BEAM
`
`DD OPTICAL WRITE
`
`COMPOSITE
`PATTERN
`
`By selectively writing complex patterns on semiconductor wafers utiliz(cid:173)
`ing both optical and E-beam technologies,
`line capacity can be in(cid:173)
`creased over that which is achievable with direct-write E-beam (DWEB)
`considering throughput restrictions without selective writing.
`
`lithography, while current
`11m
`tool is capable of 0. 25
`A Dh'EB
`excimer laser lithographic tools are limited to images larger than 0.5
`1Jrn. For this reason
`the DWEB
`is required for printing sub-0.5
`11m
`levels. Since the DWEB
`throughput is gated by pattern complexity and
`area to be written, it can be increased by writing only selected pat(cid:173)
`terns on each wafer level.
`
`By splitting the critical levels into two complementary patterns,
`the first consisting of sub-0. 5-micron images
`to be exposed by DI-.'EB
`and the second (less critical) to be exposed optically, a composite
`pattern can be generated, as shown in Fig. 1.
`
`tone of resist to be
`The process implementation depends 'on the
`used. For the majority of levels of interest, DWEB requires a negative
`resist and optical tools utilize a positive resist. Referring to Fig.
`2, the first resist is coated on the wafer, optically exposed, develop(cid:173)
`ed and hard-baked
`to prevent reflow or cracking during subsequent
`deposition of a barrier layer. (For the polysilicon level, a barrier
`layer of oxide is used.) Next, a layer of 1000-angstrom oxide or ni-
`
`©IBM Corp. 1990
`
`62
`
`SAMSUNG-1003.006
`
`

`
`COMPLEMENTARY SELECTIVE ~~ITING BY DIRECr-WRITE E-BEAM/OPTICAL LITHO-
`GRAPHY USING HIXED POSITIVE AND NEGATIVE RESIST
`Continued
`
`Jlllillll
`
`JJJJllllllm
`
`l!Wl!WlUU!Jll - OPTICAL EXPOSURE
`~POSITIVE RESIST
`\
`,_! - - - - - - - - - - - - - - - - \ NITRIDE
`POLYSILICON
`
`FIG. 2
`
`I
`
`,--..LD___j'------'r--?S---L_--'[3?-"----,. LsI Ll c 0 N NITRIDE
`f
`POLYSILICON
`
`is de(cid:173)
`the previous and subsequent processing,
`tride, depending on
`posited. The second resist is applied, DWEB exposed, developed and the
`pattern is etched into the barrier layer, simultaneously removing the
`barrier layer from
`the previously patterned positive resist, leaving
`resist pedestals and barrier layer pedestals. Next,
`the nitride is
`etched followed by the stripping of resist and oxide utilizing normal
`processing techniques. If adhesion of the first resist is not a prob(cid:173)
`lem while developing the second resist, the barrier layer may be omit(cid:173)
`ted.
`
`Although either exposure can be made first, there is an advantage
`to printing
`the optical pattern first. The D\~EB has more accurate
`image placement than the optical tools and will therefore align to the
`optical exposure more accurately.
`
`63
`
`Vol. 33 No. 3A August 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.007
`
`

`
`=:=::=.:::.:=1!)
`~ ===-:r-:ft Technical Disclosure Bulletin
`
`Vol. 33 No. 4 September 1990
`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY
`
`FfG.l
`
`41
`3/tr----~------~----~L-------~
`
`f Y~J \
`
`FIG. 2
`
`7
`
`ROX AREA
`
`8
`
`9
`
`PROTECTION BY OFFSET.
`
`FfG.4
`
`By means of processes documented in this article the well-known CMOS
`technology is implemented to obtain sub-micron channel length c~o.3 urn)
`CMOS devices with an excellent control of break-down and punch-through.
`
`Two separate bu~·~~lated process descriptions are provided in this
`disclosure, one for a conventional semi-recessed oxide (semi-ROX) iso(cid:173)
`lation structure and
`the other for a full ROX
`isolation structure.
`
`©IBM Corp. 1990
`
`227
`
`SAMSUNG-1003.008
`
`

`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY - Continued
`
`\-...,.--
`'-----.,---;---;--j/
`~ B
`\ ~ NOTE EXTRA
`'--'---
`'1--------------'>'------- PROTECTION AFFORDED
`H
`BY THE BLOCK FIELD MASK.
`
`FIG.5
`
`;----- s 2 02----------.....
`F==2 =====I
`l=====l 2=====1
`---------------------------
`
`- - - - ' p- epl
`P+ Si SUBSTRATE
`
`p-epi
`
`' - - - - - - -
`
`FIG.6
`
`FIG. 7
`
`Either process starts with a p+ Si substrate 1 with a p-epi Si layer 2
`on top, as shown in Fig. 1. The epi layer is ~3 ohm-em resistivity and
`2.5-3.0 urn
`thick at
`the process start. The relative shallowness of
`this layer makes it easier to
`implement a
`trench or other ROX
`type
`isolation because the trench depth is relatively small for this thick(cid:173)
`ness of epi. At this point the isolation/N-well formation sequence can
`employ either the conventional semi-ROX or full ROX isolation struc(cid:173)
`ture. We will begin with the semi-ROX method, as follows:
`
`With semi-ROX, a relatively thin (~150 angs.) pad oxide of Si0
`3
`is first grown on epi layer 2 over which ~1500 angs. of Si
`
`N
`2 4 are
`4
`3
`to reduce "bird' s beaking"
`deposited. These
`thicknesses are chosen
`to pattern
`effects. A ROX
`level resist
`(mask) 5 is then used
`the
`Si1N4/Si02 , as shown in Fig. 2. The ROX level pattern is transferred
`into the Si3N4/Si02 by RIE (Reactive Ion Etch). The resist 5, however,
`is left in place. The "block field" mask layer 6, which is made thick(cid:173)
`er, is then directly superimposed on 5, which has been prehardened
`two resist levels, 5 and 6, are shown in
`purposely by UV, etc. The
`
`228
`
`Vol. 33 No. 4 September 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.009
`
`

`
`........................................
`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY - Continued
`
`6
`
`3
`Cn CHANNEL)
`
`FIG. 8
`
`___ _,
`
`5_j] __ ~~-~~:l--5
`1----...l.--(_N_~_E_L_L_l --t.. ______
`I 3 I 10
`
`p+
`
`FIG. 9
`
`( 7
`
`p+
`
`I
`
`p CHANNEL DEVICE
`
`T\ CHANNEL DEVICE
`
`10
`
`I
`
`e
`
`I
`
`10
`
`p+
`
`FIG. 10
`n CHANNEL THRESHOLD IMPLANT
`Hll
`~
`~
`
`p+
`
`lg
`
`i
`
`'
`
`10
`
`p+ SUBSTRATE
`FIG. II
`
`10
`
`I
`
`l@l
`
`1 10 I_~ I
`
`10
`
`FIG.12
`
`I~ I
`
`I p
`
`15
`p+
`
`p I
`
`10
`
`I
`
`Fig. 3, where the "block-field" mask 6 acts to offset the boron field
`implant 7 (used for channel stopping) away from the p-c::hannel device
`region 8 (the "N-well"). This offset acts to avoid shorts that could
`form at the edge of the ROX should the "N-well" phosphorus not be able
`to diffuse far enough under the field oxide. Masks 5 and 6 are then
`stripped and ROX oxidation is performed, following which the Si1 N4 4 is
`stripped and the N-well resist level 9 mask is put on the wa'fer, as
`shown in Fig. 4.
`(It should be noted that an offset is not necessary
`here 10 because a later n+ source/drain implant will provide contact to
`theN-well 8.) This implant is done at a high enough energy, i.e., 360
`KeV,
`to place the N-well junction sufficiently close to the p+ sub(cid:173)
`strate 1/epi 2 interface (see Fig. 1), and can be implemented by using
`doubly ionized phosphorus at 180 KeV if necessary. The p+ substrate
`
`Vol. 33 No. 4 September 1990
`
`IBM Technical Disclosure Bulletin
`
`229
`
`SAMSUNG-1003.010
`
`

`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY - Continued
`
`N WELL
`CONTACT
`
`1? N BLOCK
`MASK
`
`10
`
`FIG.13
`
`V OUT
`
`207
`
`10
`(Si02 J
`
`FIG. 14
`
`GROUND
`
`CIRCUIT
`
`edge will move during the hot processing steps. A drive-in step is
`used to spread the N-well 8 as shown in Fig. 5. The extra pro tee tion
`afforded by the block-field mask 6 (see Fig. 3) should also be noted
`(Fig. 5). Ann+ source/drain implant, designed to enter where shown by
`11
`in Fig. 5, will provide contact to the N-well later! making other
`offset protection unnecessary.
`
`) ~2000
`With the full-ROX approach, we begin by growing oxide (Si0
`7
`angstroms thick on the p+ Si substrate/p- epi wafer (see Fig. r struc(cid:173)
`ture), with a mask used to pattern this oxide. The patterned oxide is
`left in the device areas and only removed where a fully recessed Si0
`2
`(full ROX) is desired (the "field region"). The Sio
`can be made thin(cid:173)
`2
`ner if a better selectivity than 10:1 Si to Si0
`is available for RIE.
`7
`The Si (p- epi) is then etched (~2 urn) by RIE
`to develop those low
`areas to be later filled with Si02 . Referring to Fig. 6, it should be
`noted that because the p- epi is relatively thin, the depth of Si re(cid:173)
`moved is not nearly as great as in other technologies, making process(cid:173)
`ing simpler. An Si02 oxide 4 of "vlQOO angstroms thick is next grown
`thermally on the Fig. 6 structure, followed by the deposition of ~4000
`
`230
`
`Vol. 33 No. 4 September 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.011
`
`

`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY - Continued
`
`angstroms of borosilicate glass (BSG) 5. RIE is then used to direc(cid:173)
`tionally etch the BSG, leaving sidewall spacers on the edges of the Si
`mesas 2 (p channel) and 3
`(n channel), as shown in Fig. 7. The BSG
`spacers 5 left on the edge of each Si mesa will act as a source of p
`type dopant. By using a drive-in, it is possible to dope the walls of
`the Si mesa 3 that will become the n channel device; this p type doping
`is used as a channel stop to cut the leakage at that point, just as the
`boron field implant was used in the semi-ROX process. Since the p type
`doping is required only around the n channel device, a mask 6 is used
`to cover the n channel device mesa region 3, as shown in Fig. 8. A wet
`etch (7:1 BHF, e.g.) will remove the spacers 4 and 5 (dotted) on the p
`channel mesa 2. The mask 6 also provides an opportune time to do an
`N-well implant, since only the p channel device areas 2 are exposed.
`The doping that goes to the sides of the p channel mesa has no untoward
`effects as p+ substrate doping will compensate for the lighter N-well
`doping during subsequent hot process steps. After resist 6 removal, a
`drive-in cycle,
`to move the p doping 7 from the BSG spacer into the n
`channel mesa, will act to spread theN-well 8, as shown in Fig. 9. The
`BSG spacer 5 can either be removed or left. A thin (<v500 angstroms)
`protective thermal Si01 coating 9 is grown, after which a thick planar(cid:173)
`izing medium (e.g., TEOS SiO,) 10, is deposited to fill the recessed
`field area. Planarization by-chemical-mechanical polishing then yields
`a flat surface, as shown in Fig. 10.
`
`(<v140 angstroms thick), after using
`A gate oxide is next grown
`either the semi-ROX or full-ROX process to this point, and masked N(cid:173)
`channel threshold implant performed (to adjust the N-channel threshold
`voltage). Then, poly-Si (-v4500 angstroms) for the gate electrode, Si0
`2
`N
`(-v1000 angstroms) and Si
`(<v500 angstroms) for sidewall image trans(cid:173)
`3
`4
`£ er are deposited
`[ *]
`to produce submicron and larger size poly-Si
`structures. Referring to Fig. 11, after the poly-Si gate electrodes 11
`are formed,
`the source/drains are put in place. A p block mask 12 is
`used to cover the n channel devices 3 and a p+ source/drain implant
`performed for the p channel device 8.
`
`then phosphorus and
`After the resist 12 is stripped, boron, and
`arsenic, are implanted to form the DI-LDD structure 15 on the n channel
`device. This implant is allowed to enter the p channel device as well
`because it is of a sufficiently low dosage that it does not affect the
`p+ source/drain (see Fig. 12). A layer of Si02 is next deposited and
`directional etching is employed
`to leave a spacer 16 (Fig. 13) along
`the edge of the poly-Si. After this, an N block mask 17 is used to
`cover the p channel device 14 and an N+ implant 18 forms the n channel
`source/drain. A drive-in is used to bring the source/drain junctions
`to the proper depth. A Pt wiring process is then used
`to form self(cid:173)
`aligned PtSi 19 over the gate and source/drain regions of the device
`and a Pt wire local interconnection 20 for Vout, as illustrated :i.n
`Fig. 14 for the case of CMOS inverter.
`It should also be ~oted that by
`use of Pt wiring the N+ junction area can be reduced, since there is no
`need for a contact hole over the junction as it can be done over the
`
`Vol. 33 No. 4 September 1990
`
`IBM Technical Disclosure Bulletin
`
`231
`
`SAMSUNG-1003.012
`
`

`
`SUB-MICRON CHANNEL LENGTH CMOS TECHNOLOGY - Continued
`
`adjacent Si0 2 . The passivation and final metallurgy steps employed for
`completion can use whatever process methodology
`is desired for
`the
`appropriate device level.
`
`Reference
`
`[*)
`
`"Method for Making Submicron Dimensions in Structures using Side(cid:173)
`wall Image Transfer Technique," IBM Technical Disclosure Bulletin
`26, 4587-4589 (February 1984).
`
`232
`
`Vol. 33 No. 4 September 1990
`
`IBM Technical Disclosure Bulletin
`
`SAMSUNG-1003.013
`
`

`
`:::.=-:-:. == = ®
`~ ===-:§'f§: Technical Disclosure Bulletin
`
`Vol. 36 No. 10 October 1993
`
`Multilayer Circuit Fabrication using Double Exposure of Positive Resist
`
`3
`
`pr---~' ---412'
`
`J"'
`
`..-:JD
`
`5
`
`)
`
`I
`
`I
`
`,
`
`Disclosed is a fabrication method for a build-up type multilayer printed circuit board with pillar
`connections. Positive resist is utilized twice for patter plating and pillar formation.
`
`The process is performed in the following manner:
`
`Positive resist 2 is applied on thin metal layer I and patterned by selective exposure and
`development such that openings 3 are formed at the regions where pillars or studs arc to be
`formed.
`
`Pillars 4 are formed by electroplating.
`
`0 IBM Corp. 1993
`
`423
`
`SAMSUNG-1003.014
`
`

`
`Multilayer Circuit Fabrication using Double Exposure of Positive Resist - Continued
`
`The resist 2 is again selectively exposed and developed to define the regions where wiring
`pattern is to be formed.
`
`Electroplating is performed to form wiring conductors 5. During the plating, the height of the
`pillar 4 increases.
`
`The remaining resist is stripped.
`
`Fluch etching is performed to remove those portions of the metal layer I at which the plated
`conductors 5 do not exist.
`
`Resin insulator 6 is applied and polished to provide a flattened top surface 7.
`
`1bi.n metal layer 8 is applied and the above steps are repeated, if required.
`
`424
`
`IBM Technical Disclosure Bulletin
`
`Vol. 36 No. 10 October 1993
`
`SAMSUNG-1003.015