Trials@uspto.gov
`Tel: 571-272-7822
`
`
`Paper 52
`Entered: June 21, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., AMAZON.COM, INC.,
`SONY CORP., SONY ELECTRONICS INC.,
`SONY MOBILE COMMUNICATIONS AB,
`SONY MOBILE COMMUNICATIONS (USA) INC.,
`LG ELECTRONICS, INC., LG ELECTRONICS USA, INC., and
`LG ELECTRONICS MOBILECOMM USA, INC.,1
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`
`
`Case IPR2015-00163
`Patent 7,296,121 B2
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and
`KERRY BEGLEY, Administrative Patent Judges.
`
`BISK, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`1 Petitioners from IPR2015-01353 were joined with this proceeding. Paper
`34.
`
`
`
`
`
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`Case IPR2015-00163
`Patent 7,296,121 B2
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`
`INTRODUCTION
`
`A. Background
`Apple Inc., HTC Corporation, HTC America, Inc. Samsung
`Electronics Col, Ltd., Samsung Electronics America, Inc., 2 and
`Amazon.com, Inc. (“Initial Petitioner”), filed a Petition requesting inter
`partes review of claims 1–6, 8–12, and 15–25 of U.S. Patent No. 7,296,121
`B2 (Ex. 1001, “the ’121 patent”). Paper 1 (“Pet.”). On May 8, 2015, we
`instituted a review (Paper 18, “Institution Decision” or “Inst. Dec.”) based
`upon Petitioner’s assertion that claims 4–6, 11, and 19–24 are unpatentable
`under 35 U.S.C. §§ 102 and 103. Inst. Dec. 28. On July 1, 2015, in
`response to Petitioner’s request for rehearing, we added claim 12 to the
`review. Paper 22, 6.
`On June 8, 2015, Sony Corp., Sony Electronics Inc., Sony Mobile
`Communications AB, Sony Mobile Communications (USA) Inc., LG
`Electronics, Inc., LG Electronics USA, Inc., and LG Electronics
`Mobilecomm USA, Inc. (collectively, “Subsequent Petitioner”), filed a
`Petition requesting inter partes review of the same claims of the ’121 patent
`and based on the same grounds as those instituted in IPR2015-00163. Case
`IPR2015-01353 (Paper 1, “Second Pet.”). The Subsequent Petitioner
`simultaneously filed a Motion for Joinder of its newly filed case with the
`Initial Petitioner’s previously instituted case. IPR2015-01353 (Paper 4,
`
`
`2 The Petition also lists Samsung Telecommunications America, LLC
`(“STA”) as a petitioner. Paper 6 (“Pet.”), 1. After the filing of the Petition,
`however, STA merged with and into Samsung Electronics America, Inc.
`Paper 12. Thus, STA no longer exists as a separate corporate entity. Id.
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`“Mot. for Joinder”). On October 5, 2015, we granted the Motion for Joinder
`and joined Subsequent Petitioners as petitioners in the instant proceeding.3
`Paper 34; Case IPR2015-01353 (PTAB Oct. 5, 2015) (Paper 11).
`This is a Final Written Decision under 35 U.S.C. § 318(a) and
`37 C.F.R. § 42.73. For the reasons set forth below, Petitioner has shown by
`a preponderance of the evidence that claims 4–6 and 19–24 are unpatentable.
`Petitioner has not shown by a preponderance of the evidence that claims 11
`and 12 are unpatentable.
`
`B. Related Matters
`The parties indicate that the ’121 patent is the subject of several
`proceedings in the United States District Court for the District of Delaware.
`Pet. 1–2; Paper 11, 1–2. Initial Petitioners also filed three other petitions
`seeking inter partes review of the ’121 patent—IPR2015-00159, IPR2015-
`00161, and IPR2015-00172. In addition, another petition was filed seeking
`inter partes review of the ’121 patent—IPR2015-00158. See Paper 11, 4.
`Of these proceedings at the Office, only IPR2015-001594 is ongoing and a
`final written decision in IPR2015-00159 is being issued concurrently with
`this Decision.
`
`
`3 For purposes of this decision, we will cite only to Initial Petitioner’s
`Petition.
`4 Subsequent Petitioners, who filed a petition and motion for joinder in
`IPR2015-01376, were also joined to IPR2015-00159. IPR2015-00159,
`Paper 29.
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`
`C. The Asserted Grounds of Unpatentability
`Petitioner contends that claims 4–6, 11, 12, and 19–24 (“the
`challenged claims”) of the ’121 patent are unpatentable under 35 U.S.C.
`§102 or 103 based on the following grounds (Pet. 3):
`Ground
`References
`Challenged Claims
`§ 102
`4–6, 11, and 12
`§ 103
`19–24
`
`Petitioner supports its challenge with Declarations executed by
`Dr. Robert Horst on October 28, 2014 (Ex. 1014) and on December 1, 2015
`(Ex. 1025). Patent Owner relies on a Declaration executed by Dr. Vojin
`Oklobdzija on August 11, 2015 (Ex. 2016).
`
`Koster5
`Koster and Smith6
`
`D. The ’121 Patent
`The ’121 patent relates to accessing data in computer systems that
`include more than one processor. Ex. 1001, 1:23–24. Specifically, the
`’121 patent discusses multiple processor systems with a point-to-point
`architecture—a cluster of individual processors (also referred to as
`processing nodes) that are directly connected to each other through point-to-
`point links, each with an associated cache memory. Id. at 4:38–40. To
`increase the number of available processors, multiple clusters may be
`connected. Id. at 4:50–53. Figure 1A is reproduced below.
`
`
`5 U.S. Patent No. 7,698,509 B1 (Ex. 1009) (“Koster”).
`6 MICHAEL JOHN SEBASTIAN SMITH, APPLICATION-SPECIFIC INTEGRATED
`CIRCUITS, Addison-Wesley (1997) (Ex. 1008, “Smith”).
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`Figure 1A shows an example of a multiple cluster, multiple processor
`system described by the ’121 patent. Id. at 6:10–12. Figure 1A includes
`four processing clusters: 101, 103, 105, and 107, each of which can, in turn,
`include multiple processors. Id. at 6:12–14. The clusters are connected
`through point-to-point links 111a–f. Id. at 6:14–16.
`The ’121 patent explains that cache coherency problems can arise in
`such a system, because it may contain multiple copies of the same data. Id.
`at 1:26–38. For example, if the caches of two different processors have a
`copy of the same data block and both processors “attempt to write new
`values into the data block at the same time,” then the two caches may have
`different data values and the system may be “unable to determine what value
`to write through to system memory.” Id. at 1:37–45. Solutions to cache
`coherency problems often involve an increase in communication traffic and
`a resulting decrease in efficiency. Id. at 1:23–26, 2:46–48. The ’121 patent
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`discloses “techniques . . . for increasing data access efficiency in a multiple
`processor system,” while also addressing cache coherency. Id. at 4:36–38.
`The system disclosed by the ’121 patent includes a probe filtering
`unit. Id. at 2:52–65. A probe is defined as “[a] mechanism for eliciting a
`response from a node to maintain cache coherency in a system.” Id. at 5:45–
`47. As opposed to a traditional approach of broadcasting probes to all
`nodes, the probe filtering unit reduces traffic by intercepting the probes and
`transmitting them only to those nodes that require the information based on
`probe filtering information, i.e., “[a]ny criterion that can be used to reduce
`the number of clusters or nodes probed.” Id. at 2:52–3:5, 14:50–52; see id.
`at 28:29–58, 29:43–46. The probe filtering unit may also accumulate
`responses from those nodes selected to receive the probes and respond to the
`node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
`Figure 18 of the ’121 patent is reproduced below.
`
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`Figure 18 shows a multiple processor system with a probe filtering
`unit. Id. at 3:61–63, 26:58–27:20, Fig. 18. Specifically, Figure 18 depicts
`multiple processor system 1800 with processing nodes 1802a–d
`interconnected by point-to-point communication links 1808a–e. Id. at
`26:58–27:1. System 1800 also includes probe filtering unit 1830 as well as
`I/O switch 1810, one or more Basic I/O systems (“BIOS”) 1804, I/O
`adapters 1816, 1820, and a memory subsystem with memory banks 1806a–d.
`Id. at 3:61–63, 26:58–27:20, Fig. 18.
`
`E. Challenged Claims
`The challenged claims are all dependent and depend either directly or
`indirectly from independent claims 1 and 16. Claims 1, 4, 16, and 19 are
`representative of the challenged subject matter and recite as follows:
`1.
` A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated
`therewith,
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`
`The computer system of claim 1 wherein the plurality of
`4.
`processing nodes comprises a first cluster of processors, the
`computer system comprising a plurality of clusters of processors
`including the first cluster, the plurality of clusters being
`interconnected via a second point-to-point architecture.
`
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`16. A probe filtering unit for use in a computer system
`comprising a plurality of processing nodes interconnected by a
`first point-to-point architecture, each processing node having a
`cache memory associated therewith, the probe filtering unit
`being operable to receive probes corresponding to memory lines
`from the processing nodes and to transmit the probes only to
`selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories
`
`19. At least one computer-readable medium having data
`structures stored therein representative of the probe filtering unit
`of claim 16.
`Ex. 1001, 30:65–31:7, 31:17–24, 32:7–15, 32:21–23 (line breaks added).
`
`ANALYSIS
`A. Level of Ordinary Skill in the Art
`We begin our analysis by addressing the level of ordinary skill in the
`art. Dr. Horst and Dr. Oklobdzija agree that a person of ordinary skill in the
`art would have had at least a “bachelor’s degree in electrical engineering,
`computer engineering, or computer science” and “two years of experience in
`the design of multiprocessor systems.” Ex. 1014 ¶ 8; Ex. 2016 ¶ 8. We
`adopt this proposal as the level of ordinary skill in the art, based on the
`testimony of the parties’ experts as well as our review of the ’121 patent and
`the prior art involved in this proceeding.
`
`B. Claim Construction
`We interpret claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. 37 C.F.R. § 42.100(b) ); see Cuozzo Speed Techs., LLC v. Lee,
`No. 15–446, slip op. at 12–20 (S.C. June 20, 2016) (holding that 37 C.F.R.
`§ 42.100(b) “represents a reasonable exercise of the rulemaking authority
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`that Congress delegated to the . . . Office”). We presume a claim term
`carries its “ordinary and customary meaning,” which is “the meaning that
`the term would have to a person of ordinary skill in the art in question” at
`the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`(Fed. Cir. 2007) (citation and quotations omitted). This presumption,
`however, is rebutted when the patentee acts as his own lexicographer by
`giving the term a particular meaning in the specification with “reasonable
`clarity, deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994).
`Petitioner and Patent Owner each proffer proposed constructions of
`several claim terms. Pet 4–14; PO Resp. 1–20; Reply 2–8. In the Institution
`Decision, we construed several terms, including “states associated with
`selected ones of the cache memories.” Inst. Dec. 7–15. We address below
`the parties’ post-institution arguments regarding the construction of “states”
`and otherwise maintain our constructions from the Institution Decision. We
`also address the parties’ post-institution arguments regarding the term
`“programmed.”
`
`1. “states”
`Claims 1 and 16 recite “probe filtering information representative of
`states associated with selected ones of the cache memories.” Ex. 1001,
`31:5–7, 32:14–15 (emphasis added). Before our Institution Decision, each
`party proposed a construction of the term “states associated with selected
`ones of the cache memories.” Pet. 9–10; Paper 13 (“Prelim. Resp.”) 11–22.
`Petitioner argued that the term is “broad enough to encompass ‘any modes
`or conditions of selected ones of the cache memories.’” Pet. 10. Patent
`Owner proposed that the term means “cache coherence protocol states
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`associated with data blocks stored in selected ones of the cache memories”
`and that a “’cache coherence protocol state’ means ‘the current state of a
`data block in a protocol used to maintain the coherency of caches, in which a
`data block can only be in one current state at a time, and in which the current
`state can transition to a different state upon one or more triggering events or
`conditions.’” Prelim. Resp. 11–12. In the Institution Decision, we did not
`adopt either party’s proposed construction, but found that “the term is not
`limited to cache coherence protocol states and is broad enough to include the
`condition of presence—i.e., what is stored in cache memory.” Inst. Dec. 12.
`In its Response, Patent Owner continues to argue that “the appropriate
`construction of states is limited to cache coherence states, and does not
`include mere presence.” PO Resp. 2. Petitioner does not agree that the term
`should be so limited. Paper 42 (“Reply”), 2–5. In particular, Petitioner
`asserts that the broadest reasonable construction of the term “states” is not
`limited to the context of cache coherency (id. at 3–4) and is “broad enough
`to encompass the condition of presence” (id. at 5).
`
`a. Cache Coherence States
`The language of the challenged claims “states associated with selected
`ones of the cache memories” plainly link the “states” to “cache memories.”
`In addition, in the challenged claims, the term “representative of states
`associated with selected ones of the cache memories” modifies “probe
`filtering information” (Ex. 1001, 31:5–7, 32:14–15, 32:52–55 (emphasis
`added)), which the patent defines as “[a]ny criterion that can be used to
`reduce the number of clusters or nodes probed” (id. at 14:50–52). Thus, the
`recited “states” relate not just to any aspect of the cache memory, but to the
`contents of that memory. See Inst. Dec. 8–10.
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`For the reasons discussed below, however, despite the arguments and
`evidence in Patent Owner’s Response, we remain unpersuaded that the
`’121 patent supports limiting the broadest reasonable construction of “states”
`solely to cache coherence protocol states. A claim term will be interpreted
`more narrowly than its ordinary and customary meaning only under two
`circumstances: (1) the “patentee sets out a definition and acts as [its] own
`lexicographer,” or (2) the “patentee disavows the full scope of a claim term
`either in the specification or during prosecution.” Aventis Pharma S.A. v.
`Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012). To disavow claim
`scope, the specification or prosecution history must “make[] clear that the
`invention does not include a particular feature” and the feature is then
`“deemed to be outside the reach of the claims of the patent, even though the
`language of the claims, read without reference to the specification” or
`prosecution history, “might be considered broad enough to encompass the
`feature in question.” SciMed Life Sys., Inc. v. Advanced Cardiovascular
`Sys., Inc., 242 F.3d 1337, 1341 (Fed. Cir. 2001); see Aventis, 675 F.3d at
`1330. To disavow claim scope, the patentee may “include[e] in the
`specification expressions of manifest exclusion or restriction, representing a
`clear disavowal of claim scope.” Aventis, 675 F.3d at 1330 (internal
`quotations omitted). In this context, it is not sufficient “that the only
`embodiments, or all of the embodiments, contain a particular limitation.” Id.
`Here, beginning with the claims, the relevant language in the
`independent claims, “states associated with selected ones of the cache
`memories,” expressly recites “states” alone—not cache coherency states, to
`which Patent Owner seeks to limit the term. As Petitioner points out, Patent
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`Owner’s proposed construction seeks to add additional narrowing
`descriptive language to the term “states.” See Reply 2.
`Moreover, the claims do not recite “cache coherence states” or “cache
`coherence protocol states.” Dependent claim 3, which depends indirectly
`from claim 1, however, recites “a cache coherence controller” and “a cache
`coherence directory.” Ex. 1001, 31:12–14. Similarly, claim 5, another
`claim that depends indirectly from claim 1, requires a “cache coherence
`controller.” Id. at 31:24. Thus, had the patentees intended to limit “states,”
`as recited in the independent claims of the ’121 patent, to cache coherence
`states, they demonstratively could have done so by explicitly modifying the
`disputed term with “cache coherence”—but did not.7 See Reply 3–4.
`Turning to the written description, we do not find persuasive Patent
`Owner’s arguments that the remainder of the specification supports limiting
`“states” to cache coherency states. Rather, we agree with Petitioner that the
`
`
`7 Patent Owner notes that our Institution Decision “preliminarily determined
`that ‘states’ in the claims of the ’121 Patent are not limited to ‘cache
`coherence protocol states,” “despite the fact that the Board determined that
`the term ‘probe’ in the claims should be construed as a ‘mechanism for
`eliciting a response from a node to maintain cache coherency in a system.’”
`PO Resp. 2. We do not agree with Patent Owner’s implication that our
`construction of “probe” conflicts in any way with our construction of
`“states.” The two words recite different parts of the claimed invention.
`Moreover, the ’121 patent expressly defines the term “probe” consistent with
`our construction (see Ex. 1001, 5:45–47; Inst. Dec. 8), but provides no
`definition for “state” or “states.” If “states” were intended to be limited to
`cache coherency protocol states, the ’121 patent could have provided an
`express definition for “state” or “states,” as it does for “probes.” Patent
`Owner does not provide evidence or reasoning persuading us that a person
`of ordinary skill in the art would find the express definition of “probes” as
`somehow limiting the term “states.”
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`’121 patent uses broad language in describing “states,” explaining that
`“particular implementations may use a different set of states” and “[t]he
`techniques of the present invention can be used with a variety of different
`possible memory line states.” Ex. 1001, 14:30–36; see Inst. Dec. 11; Pet. 9;
`Reply 2–3.
`Patent Owner asserts that the teachings of the ’121 patent make it
`clear that its inventions are directed to the specific field of cache coherency
`and the term “state” has “a specific meaning in the field of cache
`coherency—a cache coherency state.” PO Resp. 3–4; see Paper 51 (“Tr.”),
`63:13–64:2. As to the field of the ’121 patent, we find that it is directed,
`generally, to “data access and cache coherency in systems having multiple
`processors.” E.g., Ex. 1001, 2:39–42. The ’121 patent explains that data
`access, and the disclosed invention, involve techniques for reducing probe
`traffic as well as cache coherency techniques. See, e.g., id. at 1:21–27 (“The
`present invention relates to accessing data in a multiple processor system.
`More specifically, the present invention provides techniques for reducing
`memory transaction traffic in a multiple processor system. Data access in
`multiple processor systems can raise issues relating to cache coherency.”);
`see also, e.g., id. at [54] (title) (“Reducing Probe Traffic in Multiprocessor
`Systems”); id. at 2:45–48 (“According to the present invention, various
`techniques are provided for reducing traffic relating to memory transactions
`in multi-processor systems”). Although we agree with Patent Owner that the
`field of the ’121 patent includes cache coherency, we are not persuaded that
`this fact, alone, limits the term “state” to “cache coherence states.”
`Patent Owner, in fact, concedes that the term “state” “may have many
`broad and different meanings . . . in the general field of computers.” PO
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`Resp. 4 (citing Ex. 2016 ¶ 15). Indeed, in our Institution Decision, we relied
`on a dictionary definition of “state” from the MICROSOFT COMPUTER
`DICTIONARY: “[t]he condition at a particular time of any of numerous
`elements of computing—a device, a communications channel, a network
`station, a program, a bit, or other element—used to report on or to control
`computer operations.” Ex. 3001 (MICROSOFT COMPUTER DICTIONARY (5th
`ed. 2002)), 497–98. Patent Owner agrees that this dictionary is directed “to
`the entire field of computing.” PO Resp. 4; Reply 4. And as Petitioner
`points out, Patent Owner relies on this same dictionary when proposing a
`construction for another term in the ’121 patent—“programmed.” See PO
`Resp. 15. Patent Owner has not persuaded us that a person of ordinary skill
`in the art would not base its definition of the term “states” on the field of
`computers generally, but instead would rely on a meaning specific to the
`“field of cache coherency.”
`To begin with, as discussed above, Patent Owner agrees that a person
`of ordinary skill in the art would have a degree in electrical engineering,
`computer engineering, or computer science and at least two years of
`experience in the design of multiprocessor systems. Ex. 1014 ¶ 8; Ex. 2016
`¶ 8. Nothing in this definition points to a specific field, known as cache
`coherency, with its own terminology displacing the more general
`terminology used by those in the field of computing.
`Moreover, Patent Owner, itself, admits that in the context of a patent
`describing data access and cache coherence in multiprocessor systems, the
`term “state,” used on its own, does not necessarily refer to a cache coherency
`state. Specifically, when discussing Koster, titled “Snooping-based Cache-
`Coherence Filter for a Point-to-Point Connected Multiprocessing Node,”
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`Patent Owner argues that “the mere fact that Koster refers to his shadow tag
`memory as ‘local state memory’ does not mean that it contains ‘information
`representative of states associated with selected ones of the cache memories’
`as that phrase is used in the ’121 patent.” PO Resp. 23. Instead, according
`to Patent Owner, to determine the meaning of “local state memory,” “it is
`necessary to consider what information Koster stores in the shadow tag
`memory and whether such information satisfies the properly construed
`limitation.” Id. Patent Owner concludes that because tags only indicate the
`address of data, “despite Koster’s reference to such tags as ‘state’
`information,” the tags “are not representative of cache coherency states as
`required by the properly construed limitations of the ’121 patent.” Id.
`Essentially, Patent Owner attempts to argue, in the claim construction
`section of its Response, that a person of ordinary skill in the art would
`understand that, in the context of the ’121 patent, the term “state” on its own,
`means “cache coherency state,” where the actual cache coherency states
`encompass an open set of states used by any cache coherency protocol. See
`Prelim. Resp. 11–12; PO Resp. 2–7. However, when analyzing the prior art,
`which involves the same field as the ’121 patent, Patent Owner asserts that
`the same person of ordinary skill would understand the term “state” on its
`own does not mean cache coherency state, but instead means something
`more broad, as, for example, the term is defined in the general field of
`computers. Patent Owner does not explain sufficiently why the term state
`would mean one thing in the ’121 patent and another in Koster when both
`involve the same field of art.
`Patent Owner relies, for its assertions, on a few excerpts of the
`’121 patent, which allegedly “demonstrate that the use of the term ‘state’ in
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`the patent is directed to cache coherence protocol states.” PO Resp. 5–6.
`For example, Patent Owner points to the following passage of the
`Specification as “mak[ing] it clear that the relevant state is a cache
`coherence protocol state”:
`It should be noted that a coherence protocol can contain several
`types of messages. In one example, a coherence protocol
`includes four types of messages; data or cache access requests,
`probes, responses, or probe responses, and data packets. Data or
`cache access requests usually target the home node memory
`controller. Probes are used to query each cache in the system.
`The probe packet can carry information that allows the caches to
`properly transition the cache state for a specified line.
`
`Id. at 6 (quoting Ex. 1001, 9:21–29) (emphases added by Patent Owner).
`Similarly, Patent Owner points to the Specification’s statement that “[b]y
`using a coherence directory, global memory line state information (with
`respect to each cluster) can be maintained and accessed by a memory
`controller or a cache coherence controller in a particular cluster,” asserting
`that this statement only makes sense if the coherence directory concerns
`solely cache coherence states. PO Resp. 6–7 (quoting Ex. 1001, 13:4–7)
`(emphases added by Patent Owner).
`We are not persuaded that these passages of the ’121 patent limit the
`term “states” as asserted by Patent Owner. Neither of the passages relied
`upon by Patent Owner actually uses the term “state” as recited in the
`challenged claims. Instead, the first passage Patent Owner relies on for a
`narrower construction uses the term “cache state” and the second uses the
`term “global memory line state information.” Thus, even if the passages
`describe a concept narrower than “states associated with selected ones of the
`cache memories,” as recited in the challenged claims, this difference can be
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`attributed to the fact that different terms are used. More importantly, these
`passages do not expressly disclaim or disavow the broader scope of the
`claim language, particularly given the expansive language used elsewhere in
`the Specification allowing states to include “a variety of different possible
`memory line states.” Ex. 1001, 14:30–36.
`Patent Owner also points to Figures 7 and 8 of the ’121 patent as
`allegedly “strongly illustrative that the ’121 Patent uses ‘state’ to mean
`cache coherence protocol states.” PO Resp. 7. According to Patent Owner,
`the Specification equates the word “state” with cache coherence states by
`describing Figure 7 as “the coherence directory 701 includes state
`information 713” and by stating “[i]n some embodiments, the memory line
`states are modified, owned, shared, and invalid.” Id. (quoting Ex. 1001,
`13:55–59) (emphases added by Patent Owner). In other words, Patent
`Owner argues that because Figure 7 shows a column labeled “state,” and
`describes this column as including in some embodiments the states used in
`common cache coherence protocols such as MOESI and MOSI, the term
`“state” must be equivalent to cache coherence protocol. See Tr. 77:20–
`78:18.
`Figures 7 and 8, however, also are not persuasive as defining the term
`state because they are clearly described as exemplary embodiments. See,
`e.g., Ex. 1001, 3:15–18, 4:11–35 (“[I]t is not intended to limit the invention
`to the described embodiments. On the contrary, it is intended to cover
`alternatives, modification, and equivalents as may be included within the
`spirit and scope of the invention as defined by the appended claims.”),
`13:44–59 (describing Figure 7 using the term “example” or “embodiment”
`no less than five times), 14:48–50, 30:57–64 (“[T]he scope of the invention
`
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`Case IPR2015-00163
`Patent 7,296,121 B2
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`should not be limited by reference to such advantages, aspects, and objects
`. . . the scope of the invention should be determined with reference to the
`appended claims.”). We are not persuaded that Figure 7 shows anything
`more than what it purports to show—one example with a column labeled
`“state,” that may refer to “memory line states” of “modified, owned, shared,
`and invalid.” Again, nothing in this example expressly disclaims or
`disavows the broad claim language, particularly in light of other statements
`in the Specification allowing states to include “a variety of different possible
`memory line states.” Ex. 1001, 14:30–36.
`Patent Owner further argues that the ’121 patent distinguishes
`between state information and tags in certain examples disclosed therein.
`PO Resp. 22–23. We also find this information unpersuasive, as Patent
`Owner’s citation of portions of the ’121 patent that discuss both tags and
`state information does not persuade us that tags and state information are
`mutually exclusive, as these portions of the ’121 patent are examples.
`See id. at 22–23 (citing Ex. 1001, 7:67–8:4; 13:44–14:47; Fig. 7). Patent
`Owner does not identify any portion of the ’121 patent that clearly disavows
`tags as mutually exclusive from state information.
`Patent Owner also proffers extrinsic evidence to support its proposed
`construction of the term “state.” Extrinsic evidence is “less significant than
`the intrinsic record in determining the legally operative meaning of claim
`language.” Phillips v. AWH Corp., 415 F.3d 1303, 1317 (Fed. Cir. 2005)
`(citations omitted) (internal quotations omitted). For example, Patent Owner
`points to “one of the treatises on cache coherency,” DANIEL J. SORIN ET AL.,
`A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE (2011)
`(Ex. 2010, “Sorin”), as equating the term “state” with cache coherence
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`Case IPR2015-00163
`Patent 7,296,121 B2
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`protocol states. PO Resp. 4 (citing Ex. 2010, 88–89; Ex. 2016 ¶ 15). We do
`not find this evidence persuasive. Evidence of the use of shorthand within
`one section in one publication does not indicate that that same shorthand will
`be recognized, by a person of ordinary skill, as necessarily having the same
`meaning in other contexts. Dr. Oklobdzija’s testimony referring to this
`treatise does not persuade us to the contrary. See Ex. 2016 ¶ 15.
`Patent Owner also points to another article, where the authors—three
`of whom are the authors of Sorin, discussed above—state that “[a]
`processor’s access to a cache block is determined by the state of that block
`in its cache, and this state is generally one of the five MOESI (Modified,
`Owned, Exclusive, Shared, Invalid) states.” PO Resp. 5 (citing Ex. 2003, 1)
`(emphasis added); see Reply 4. Again, this isolated use of a shorthand of
`“states” in a publication, with several of the same authors as the other cited
`publication, does not persuade us that this shorthand is universally accepted
`to have a particular meaning whenever a particular type of software is being
`discussed. Moreover, the use of the term “generally” in this statement
`shows that it is not limiting the term “states” to cache coherency states, or
`more specifically, MOESI states. Therefore, we are not persuaded that
`Patent Owner’s extrinsic evidence regarding ordinary meaning overcomes
`the intrinsic record of this case. See Phillips, 415 F.3d at 1318 (“[A] court
`should discount any expert testimony that is clearly at odds with the claim
`construction mandated by the claims themselves, the written description, and
`the prosecution history, in other words, with the written record of the
`patent.”) (citation