Service of Process
`Transmittal
`11/26/2013
`CT Log Number 523962807
`
`TO: (cid:9)
`
`Ami Gomez
`Apple Inc.
`1 Infinite Loop, M/S 36-3NYJ
`Cupertino, CA 95014-
`
`RE: (cid:9)
`
`Process Served in Texas
`
`FOR: (cid:9)
`
`Apple Inc. (Domestic State: CA)
`
`ENCLOSED ARE COPIES OF LEGAL PROCESS RECEIVED BY THE STATUTORY AGENT OF THE ABOVE COMPANY AS FOLLOWS:
`
`TITLE OF ACTION: (cid:9)
`
`Vantage Point Technology, Inc., Pltf. vs. Apple Inc., Dft.
`
`DOCUMENT(S) SERVED: (cid:9)
`
`Summons, Proof of Service, Complaint, Exhibit(s)
`
`COURT/AGENCY: (cid:9)
`
`NATURE OF ACTION: (cid:9)
`
`Eastern District of Texas - United States District Court - Marshall Division, TX
`Case # 213CV989
`
`Intellectual Property Litigation - Patent infringement - Defendant's infringement and
`wrongful sale of '750 Patent products patent by plaintiff
`
`ON WHOM PROCESS WAS SERVED: (cid:9)
`
`C T Corporation System, Dallas, TX
`
`DATE AND HOUR OF SERVICE: (cid:9)
`
`By Process Server on 11/26/2013 at 14:15
`
`JURISDICTION SERVED : (cid:9)
`
`Texas
`
`APPEARANCE OR ANSWER DUE: (cid:9)
`
`Within 21 Days after service of this summons (not counting the day you received it)
`
`ATTORNEY(S) / SENDER(S): (cid:9)
`
`ACTION ITEMS: (cid:9)
`
`Paul V. Storm
`Gardere Wynne Sewell LLP
`1601 Elm Street
`Suite 3000
`Dallas, TX 75201
`214-999-3000
`
`SOP Papers with Transmittal, via Fed Ex Priority Overnight , 797266512498
`Image SOP
`Email Notification, Adeline Yu ayu@apple.com
`Email Notification,Jeff Risher jrisher@apple.com
`Email Notification, Lisa Olle olle@apple.com
`Email Notification, Noreen Krall nkrall@apple.com
`Email Notification, David Melaugh melaugh@apple.com
`Email Notification, Iain Cunningham icunningham@apple.com
`Email Notification, Colleen Brown colleen_brown@apple.com
`Email Notification, Erica Tierney etierney@apple.com
`Email Notification, Diana Loop loop@apple.com
`Email Notification, Lara Eidemiller leidemiller@apple.com
`Email Notification, Wendy Anna Herby wherby@apple.com
`Email Notification, Sarita Venkat saritav@apple.com
`Email Notification, Tom Vigdal tvigdal@apple.com
`Email Notification,Cyndi Wheeler cwheeler@apple.com
`Email Notification, Heather Moser hmoser@apple.com
`Email Notification, Jackie Harlow jharlow@apple.com
`Email Notification, Ami Gomez ami_r_gomez@apple.com
`
`Page 1 of 2 / PS
`
`Information displayed on this transmittal is for CT Corporation's
`record keeping purposes only and is provided to the recipient for
`quick reference. This information does not constitute a legal
`opinion as to the nature of action, the amount of damages, the
`answer date, or any information contained in the documents
`themselves. Recipient is responsible for interpreting said
`documents and for taking appropriate action. Signatures on
`certified mail receipts confirm receipt of package only, not
`contents.
`
`1
`
`APPLE 1003
`
`

`

`Service of Process
`Transmittal
`11/26/2013
`CT Log Number 523962807
`
`TO: (cid:9)
`
`Ami Gomez
`Apple Inc.
`1 Infinite Loop, M/S 36-3NYJ
`Cupertino, CA 95014-
`
`RE: (cid:9)
`
`Process Served in Texas
`
`FOR: (cid:9)
`
`Apple Inc. (Domestic State: CA)
`
`Email Notification, Roslyn Quinn roslyn_quinn@apple.com
`Email Notification, Tim O'Neil toneil@apple.com
`Email Notification, Charstie Wheelock wheelock@apple.com
`Email Notification, Stan Flemister flemister@apple.com
`Email Notification, Maya Kumar maya_kumar@apple.com
`Email Notification, Erik Floyd efloyd@apple.com
`Email Notification, Beth Kellermann kellermann@apple.com
`Email Notification, Andrew Song asong@apple.com
`Email Notification, Darleen Morris darleen@apple.com
`Email Notification, Ryan Moran rmoran@apple.com
`Email Notification, David Weiskopf dweiskopf@apple.com
`Email Notification, Jennifer Brown jennifer_brown@apple.com
`Email Notification, Susan Guarino sguarino@apple.com
`Email Notification, Andrew Farthing afarthing@apple.com
`Email Notification, Ash Upreti aupreti@apple.com
`Email Notification, Jen Yokoyama jyokoyama@apple.com
`Email Notification, Scott Murray scott_murray@apple.com
`Email Notification, Pami Vyas pvyas@apple.com
`Email Notification, Kim Moore kim_moore@apple.com
`Email Notification, Shelli Platt rplatt@apple.com
`Email Notification, Jeannie Willis jeannie_willis@apple.com
`
`SIGNED: (cid:9)
`PER: (cid:9)
`ADDRESS: (cid:9)
`
`TELEPHONE: (cid:9)
`
`C T Corporation System
`Beatrice Casarez-Barrientez
`350 North St Paul Street
`Suite 2900
`Dallas, TX 75201
`214-932-3601
`
`Page 2 of 2 / PS
`
`Information displayed on this transmittal is for CT Corporation's
`record keeping purposes only and is provided to the recipient for
`quick reference. This information does not constitute a legal
`opinion as to the nature of action, the amount of damages, the
`answer date, or any information contained in the documents
`themselves. Recipient is responsible for interpreting said
`documents and for taking appropriate action. Signatures on
`certified mail receipts confirm receipt of package only, not
`contents.
`
`2
`
`

`

`1. (cid:9)
`
`AO 440 (Rev. 06/12) Summons in a Civil Action
`
`UNITED STATES DISTRICT COURT
`for the
`
`Eastern District of Texas
`
`Vantage Point Technology Inc.
`
`Plaintiff(s)
`V.
`
`Apple Inc.
`
`Defendant(s)
`
`Civil Action No. 2:13-cv-989
`
`SUMMONS IN A CIVIL ACTION
`
`To: (Defendant's name and address) Apple Inc.
`do CT Corp. System
`350 North St. Paul Street, Suite 2900
`Dallas, Texas 75201-4234
`
`A lawsuit has been filed against you.
`
`Within 21 days after service of this summons on you (not counting the day you received it) — or 60 days if you
`are the United States or a United States agency, or an officer or employee of the United States described in Fed. R. Civ.
`P. 12 (a)(2) or (3) — you must serve on the plaintiff an answer to the attached complaint or a motion under Rule 12 of
`the Federal Rules of Civil Procedure. The answer or motion must be served on the plaintiff or plaintiffs attorney,
`whose name and address are: Paul V. Storm
`Gardere Wynne Sewell LLP
`1601 Elm Street, Suite 3000
`Dallas, Texas 75201
`
`If you fail to respond, judgment by default will be entered against you for the relief demanded in the complaint.
`You also must file your answer or motion with the court.
`
`Date: (cid:9)
`
`11/22/13
`
`CLERK OF COURT
`
`Signature of Clerk or Deputy Clerk
`
`3
`
`

`

`AO 440 (Rev. 06/12) Summons in a Civil Action (Page 2)
`
`Civil Action No. 2:13-cv-989
`
`PROOF OF SERVICE
`(This section should not bellied with the court unless required by Fed. R. Civ. P. 4 (I))
`
`This summons for (name of individual and title, if any)
`
`was received by me on (date)
`
`O I personally served the summons on the individual at (place)
`
`on (date) (cid:9)
`
`; or
`
`0 I left the summons at the individual's residence or usual place of abode with (name)
`
`on (date) (cid:9)
`
`, and mailed a copy to the individual's last known address; or
`
`, a person of suitable age and discretion who resides there,
`
`O I served the summons on (name of individual)
`
`designated by law to accept service of process on behalf of (name of organization)
`
`on (date)
`
`; or
`
`O I returned the summons unexecuted because (cid:9)
`
`O Other (specify):
`
`, who is
`
`; or
`
`My fees are $
`
`for travel and $ (cid:9)
`
`for services, for a total of $
`
`0.00
`
`I declare under penalty of perjury that this information is true.
`
`Date:
`
`Server's signature
`
`Printed name and title
`
`Server's address
`
`Additional information regarding attempted service, etc:
`
`4
`
`(cid:9)
`(cid:9)
`

`

`Case 2:13-cv-00989-JRG Document 1 Filed 11/21/13 Page 1 of 4 PagelD #: 1
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`VANTAGE POINT TECHNOLOGY, INC.,
`
`V.
`
`APPLE INC.,
`
`Plaintiff,
`
`Defendant.
`
`Civil Action No.
`
`JURY TRIAL DEMANDED
`
`COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff Vantage Point Technology, Inc. ("Vantage Point") alleges the following for its
`
`complaint against Defendant Apple Inc.
`
`THE PARTIES
`
`1.
`
`Plaintiff is a corporation formed under the laws of the State of Texas having its
`
`principal place of business at 719 W. Front Street, Suite 244, Tyler, Texas 75702.
`
`2.
`
`Defendant is a corporation formed under the laws of the state of California with a
`
`principal place of business at 1 Infinite Loop, Cupertino, California 95014. Defendant may be
`
`served with process via its registered agent CT Corp. System, 350 North St. Paul Street, Suite
`
`2900, Dallas, Texas 75201-4234.
`
`JURISDICTION AND VENUE
`
`3.
`
`This is a patent infringement action. The Court has subject matter jurisdiction
`
`pursuant to 28 U.S.C. §§1331 and 1338.
`
`4.
`
`The Court has personal jurisdiction over Defendant because it has availed itself of
`
`the rights and benefits of this District by conducting business in this jurisdiction, including by
`
`promoting and selling products for sale via the internet, which is accessible to and accessed by
`
`COMPLAINT FOR PATENT INFRINGEMENT (cid:9)
`
`Page 1
`
`5
`
`

`

`Case 2:13-cv-00989-JRG Document 1 Filed 11/21/13 Page 2 of 4 PagelD #: 2
`
`residents of this District, and operating retail locations and knowingly selling products in stores
`
`throughout this District.
`
`5. (cid:9)
`
`Venue is proper in this District pursuant to 28 U.S.C. §§1391(b)-(d) and
`
`§1400(b), because substantial acts of infringement have occurred in this District.
`
`COUNT ONE
`INFRINGEMENT OF U.S. PATENT NO. 5,463,750
`
`6.
`
`On October 31, 1995, U.S. Patent No. 5,463,750 (the "750 Patent") entitled
`
`"Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having
`
`Multiple Instruction Pipelines and Separate TLB's for each Pipeline" was duly and legally issued
`
`by the United States Patent and Trademark Office. The application for the '750 Patent was filed
`
`on November 2, 1993 and originally assigned to Intergraph Corporation. A true and correct copy
`
`of the '750 Patent is attached as Exhibit A hereto.
`
`7.
`
`Plaintiff is the sole and exclusive owner of all right, title, and interest in the '750
`
`Patent and holds the exclusive right to take all actions, including the filing of this patent
`
`infringement lawsuit, necessary to enforce its rights to the '750 Patent. Plaintiff also has the
`
`right to recover all damages for past, present, and future infringement of the '750 Patent and to
`
`seek injunctive relief as appropriate under the law.
`
`8.
`
`Defendant has directly infringed, either literally or by equivalents, one or more
`
`claims of the '750 Patent by making, having made, using, selling, offering for sale and/or
`
`importing products that satisfy each and every limitation of one or more claims of the '750
`
`Patent, including at least Claim 1. Such products include, at least, any and all chipsets with an
`
`ARM based Swift, dual ARM Cortex A9s, or ARM Cortex A8 core processor design. Such
`
`products also include smart phones, tablets, and/or computers that incorporate those chipsets.
`
`Upon information and belief, the accused chipset products include at least the Apple A6, A6X,
`
`COMPLAINT FOR PATENT INFRINGEMENT (cid:9)
`
`Page 2
`
`6
`
`

`

`Case 2:13-cv-00989-JRG Document 1 Filed 11/21/13 Page 3 of 4 PagelD #: 3
`
`A5, A5X, and the A4. Upon information and belief, Defendant has incorporated those chipsets
`
`into at least the following accused electronic device products, which it makes, has made, sells,
`
`offers to sell, and/or imports: iPhone 5, iPhone 4s, iPhone 4, iPhone 3Gs, iPad (4th Gen), and
`
`iPad (3rd Gen).
`
`9.
`
`Defendant's manufacture, sales, offers to sell, and/or importation of the identified
`
`accused chipset products and additional electronic device products incorporating those chipsets
`
`was unauthorized, without the permission of Plaintiff; and constitutes infringement under 35
`
`U.S.C. §271 for which it is directly liable.
`
`10. As a result of Defendant's direct infringement, Plaintiff Vantage Point has been
`
`damaged monetarily and is entitled to adequate compensation of no less than a reasonable
`
`royalty pursuant to 35 U.S.C. § 284.
`
`JURY DEMAND
`
`Plaintiff requests a jury on all issues so triable.
`
`PRAYER
`
`WHEREFORE, Plaintiff respectfully requests that the Court:
`
`A. Enter judgment that Defendant has directly infringed, either literally or by
`
`equivalents, the '750 Patent;
`
`B. Award Plaintiff damages for Defendant's infringement in an amount to be
`
`determined at trial, including enhanced damages, costs, and pre and post-
`
`judgment interest; and
`
`C. Award any other relief deemed just and proper.
`
`COMPLAINT FOR PATENT INFRINGEMENT (cid:9)
`
`Page 3
`
`7
`
`

`

`Case 2:13-cv-00989-JRG Document 1 Filed 11/21/13 Page 4 of 4 Page ID #: 4
`
`November 21, 2013 (cid:9)
`
`Respectfully submitted,
`
`/s/ Paul V. Storm
`Paul V. Storm
`Texas State Bar No. 19325350
`Sarah M. Paxson
`Texas State Bar No. 24032826
`GARDERE WYNNE SE WELL LLP
`1601 Elm Street, Suite 3000
`Dallas, Texas 75201
`(214) 999-3000
`pvstorm@gardere.com
`spaxson@gardere.com
`
`Attorneys for Vantage Point Technology,
`Inc.
`
`COMPLAINT FOR PATENT INFRINGEMENT (cid:9)
`
`Page 4
`
`8
`
`

`

`Case 2:13-cv-00989-JRG Document 1-1 Filed 11/21/13 Page 1 of 11 PagelD #: 5
`
`Exhibit A
`
`9
`
`

`

`Case 2:13-cv-00989-JRG Document 14 11ii
`ilifkiUS005 463750 ifiliatifill
`
`United States Patent [19]
`Sachs (cid:9)
`
`[11] Patent Number: (cid:9)
`[45] Date of Patent: (cid:9)
`
`5,463,750
`Oct. 31, 1995
`
`(cid:9) (cid:9)
`
`[54] METHOD AND APPARATUS FOR
`TRANSLATING VIRTUAL ADDRESSES IN A
`DATA PROCESSING SYSTEM HAVING
`MULTIPLE INSTRUCTION PIPELINES AND
`SEPARATE TLB'S FOR EACH PIPELINE
`
`[75] Inventor: Howard G. Sachs, Belvedere, Calif.
`
`[73] Assignee: Intergraph Corporation, Huntsville,
`Ala.
`
`[21] Appl. No.: 146,818
`
`[22] Filed: (cid:9)
`
`Nov. 2, 1993
`
`[51] Int. C1.6 (cid:9)
` GO6F 12/10
` 395/496; 364/228; 364/255.7;
`[52] U.S. Cl.
`364/243.4; 364/DIG. 1; 364/964.343; 364/DIG. 2;
`364/955.5; 395/800; 395/421.03; 395/416
`[58] Field of Search (cid:9)
` 395/400, 425,
`395/800
`
`[56] (cid:9)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,758,951 7/1988 Sznyter, Ill (cid:9)
`4,980,816 12/1990 Fukuzawa at al. (cid:9)
`5,197,139 3/1993 Emma et al. (cid:9)
`5,226,133 7/1993 Taylor et at. (cid:9)
`5,247,629 9/1993 Lasamatta et al. (cid:9)
`5,293,612 3/1994 Shingai (cid:9)
`
`
`395/400
` 395/400
` 395/400
` 395/400
` 395/400
` 395/425
`
`5,305,444
`5,386,530
`5,404,476
`5,404,478
`5,412,787
`
` 395/400
` 395/400
` 395/400
` 395/400
` 395/400
`
`4/1994 Becker et al. (cid:9)
`1/1995 Hattori (cid:9)
`4/1995 Kadaira (cid:9)
`4/1995 Arai et al. (cid:9)
`5/1995 Forsyth et al. (cid:9)
`Primary Examiner—Ken S. Kim
`Attorney, Agent, or Finn—Townsend and Townsend and
`Crew
`[57] (cid:9)
`
`ABSTRACT
`
`A computing system has multiple instruction pipelines,
`wherein one or more pipelines require translating virtual
`addresses to real addresses. A TLB is provided for each
`pipeline requiring address translation services, and an adress
`translator is provided for each such pipeline for translating
`a virtual address recieved from its associated pipeline into
`corresponding real addresses. Each address translator com-
`prises a translation buffer accessing circuit for accessing the
`TLB, a translation indicating circuit for indicating whether
`translation data for the virtual address is stored in the
`translation buffer, and an update control circuit for activating
`the direct address translation circuit when the translation
`data for the virtual address is not stored in the TLB. The
`update control circuit also stores the translation data
`retrieved from the main memory into the TLB. If it is desired
`to have the same translation information available for all the
`pipelines in a group, then the update control circuit also
`updates all the other TLB's in the group.
`
`14 Claims, 4 Drawing Sheets
`
`,- 200
`
`210C\
`
`2104
`
`LOAD
`INSTRUCTION
`PIPELINE
`218.4-
`
`ADDRESS
`REGISTER
`
`2264
`P2PA
`
`2108-\
`
`LOAD
`INSTRUCTION
`PIPELINE*
`2188
`
`STORE
`INSTRUCTION
`PIPELINE
`218C
`2148
`
`ADDRESS
`REGISTER
`228A
`2266
`
`2228-\ (cid:9)
`
`
`
` ,-214C
`ADDRESS '
`RECISTER
` 228C
`--C
`
`(cid:9) 226C
`222C (cid:9)
`
`
`
`TLB
`
`TLB
`
`TLB
`
`23081 —2348
`
`230C-1 "-234C
`
`CMP
`
`23041
`
`248B-
`
`2384
`
`CMP
`
`CMP
`
`.„--2388
`
`".-248C
`
`248.4
`
`260j
`
`UPDATE
`CONTROL
`
`7- 240
`
`244
`
`TO MAIN
`MEMORY
`34
`
`DTU
`
`162]
`
`10
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Oct. 31, 1995 (cid:9)
`
`Sheet 1 of 4 (cid:9)
`
`5,463,750
`
`1O\
`
`REGISTER
`FILE
`
`72
`
`r 5°
`CACHE
`MEMORY
`
`14-\
`
`-22
`
`76
`
`-42 (cid:9)
`
`r 30
`
`INSTRUCTION
`ISSUING
`UNIT
`
`MAIN
`MEMORY
`
`MASS
`<:› STORAGE
`DEVICE
`
`A \34
`50
`
`f
`
`r 46
`DATA
`TRANSFER
`UNIT
`
`MA' L188
`
`184
`
`FIG. I
`
`VIRTUAL MEMORY
`
`REAL MEMORY
`
`16M BYTE
`224
`1 BYTES
`
`RM = 2 2 PAGES
`PAGE = 212 BYTES
`
`FIG. 23
`
`4G BYTE
`
`232
`BYTES
`
`FIG. 24
`
`11
`
`(cid:9)
`(cid:9)
`

`

`Case 2:13-cv-00989-JRG Document 1-1 Filed 11/21/13 Page 4 of 11 PagelD #: 8
`
`U.S. Patent (cid:9)
`
`Oct. 31, 1995 (cid:9)
`
`Sheet 2 of 4 (cid:9)
`
`5,463,750
`
`31
`VA DIRECTORY (10)
`
`22 21 (cid:9)
`PAGE (10) (cid:9)
`
`12 11
`
`DISP (12)
`
`PDO
`REGISTER Sb O (cid:9)
`108 (cid:9)
`
`(20)
`
`(2o)
`
`ZERO'S
`
`
`(12)
`
`VA (31:22 )
`710
`
`(10)
`
`00
`
`PAGE
`DIRECTORY
`ENTRY
`ADDRESS
`ACCUMULATOR
`.112
`
`PAGE DIRECTORY 0
`
`PAGE TABLE 0
`
`104
`
`32
`
`20 (cid:9)
`11 (cid:9)
`„------, .......,, (cid:9)
`PTE
`
`gi
`g
`
`PF
`
`34
`
`100
`
`TO
`TLB
`
`PAGE TABLE
`TABLE 1023
`
`31 (cid:9)
`
`PAGE TABLE
`
`0
`
`PAGE 0
`
`, 20 (cid:9)
`
`5 (cid:9)
`
`4
`
`RA
`
`ST PL D R PF
`
`PAGE 1023
`
`VA (11:0)
`
`12
`
`VA (21:12)
`
`PAGE
`TABLE
`ENTRY
`ADDRESS
`ACCUMULATOR
`( IN \
`DAT)
`
`(20)
`
`(10) 00
`
`32
`
`RA, FROM TLB
`
`"20
`
`/831
`
`(20)
`
`(12)
`
`32 BIT REAL ADDRESS
`
`PF = PAGE FAULT
`PL = ACCESS PROTECTION
`ST= SYSTEM TAGS
`D = DIRTY FLAG
`R = REFERENCED FLAG
`
`FIG. 3 (cid:9)
`
`1 (cid:9)
`
`REAL
`ADDRESS
`ACCUMULATOR
`
`12
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Oct. 31, 1995 (cid:9)
`
`Sheet 3 of 4 (cid:9)
`
`5,463,750
`
`150-\
`
`
`180
`127
`
`158-\ 182
`
`TLB
`
`VA<18:12>
`
`VAT RA
`178---
`
`CNTRL
`
`184
`
`162-\
`UPDATE
`DTU
`
`4
`1912TO DATA
`TRANSFER UNIT
`-TO MAIN
`MEMORY
`34
`
`166-- 0
`
`\-186
`170
` CMP
`175-\\\ I (cid:9)
`
`N-188 195
`MISS?
`
`\-190
`r174
`
`TO CACHE
`FOR. RA TAG
`COMPARISON
`TO DETERMINE
`CACHE HIT/MISS
`
`VA<31 19>
`VA<3112>
`VA<3112>
`
`VIRTUAL ADDRESS
`
`31 (cid:9)
`
`19 18 12 11 (cid:9)
`
`0
`
`VIRTUAL ADDRESSES
`FROM OTHER PIPELINES
`
`VAT = VIRTUAL ADDRESS TAG
`RA = REAL ADDRESS (BITS <3112>)
`VA = VIRTUAL ADDRESS
`
`FIG. 4
`
`13
`
`

`

`U.S. Patent (cid:9)
`
`Oct. 31, 1995 (cid:9)
`
`Sheet 4 of 4 (cid:9)
`
`5,463,750
`
`2104
`
`LOAD
`INSTRUCTION
`PIPELINE
`2184-N
`
`210B-\ (cid:9)
`
`LOAD
`INSTRUCTION
`PIPELINE
`2188
`
`210C-\ r- 200
`
`STORE
`INSTRUCTION
`PIPELINE
`
`ADDRESS
`REGISTER
`
`J
`
`
`TLB
`
`7-2144
`
`ADDRESS
`r 2284
`REGISTER
`(cid:9)
`2268
`2228 -\ (cid:9)
`
`TLB
`
`2264
`2224
`
`CMP
`
`(cid:9)
`
`1
`2308-
`Ri
`CMP
`
`< (cid:9)
`
`2.304-1
`
`2484
`
`2488
`
`2384
`
`260 17
`
`%I
`ADDRESS
`REGISTER
`
`/-214C
`
`r 228C
`
`7' 2148
`
`/- 2288
`(cid:9) 226C
`222C-
`
`TLB
`
`230C-
`
`\-234C
`
`CMP
`
`L.--2388
`
`N--248C
`
`/--238C
`
`UPDATE
`CONTROL
`
`244
`
`DTU
`
`162
`
`FIG. 5
`
`(cid:9) TO MAIN
`MEMORY
`34
`
`14
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`5,463,750
`
`1
`METHOD AND APPARATUS FOR
`TRANSLATING VIRTUAL ADDRESSES IN A
`DATA PROCESSING SYSTEM HAVING
`MULTIPLE INSTRUCTION PIPELINES AND
`SEPARATE TLB'S FOR EACH PIPELINE
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to computing systems and,
`more particularly, to a method and apparatus for translating
`virtual addresses in a computing system having multiple
`instruction pipelines.
`FIG. 1 is a block diagram of a typical computing system
`10 which employs virtual addressing of data. Computing
`system 10 includes an instruction issuing unit 14 which
`communicates instructions to a plurality of (e.g., eight)
`instruction pipelines 18A—H over a communication path 22.
`The data referred to by the instructions in a program are
`stored in a mass storage device 30 which may be, for
`example, a disk or tape drive. Since mass storage devices
`operate very slowly (e.g., a million or more clock cycles per
`access) compared to instruction issuing unit 14 and instruc-
`tion pipelines 18A—H, data currently being worked on by the
`program is stored in a main memory 34 which may be a
`random access memory (RAM) capable of providing data to
`the program at a much faster rate (e.g., 30 or so clock
`cycles). Data stored in main memory 34 is transferred to and
`from mass storage device 30 over a communication path 42.
`The communication of data between main memory 34 and
`mass storage device 30 is controlled by a data transfer unit
`46 which communicates with main memory 34 over a
`communication path 50 and with mass storage device 30
`over a communication path 54.
`Although main memory 34 operates much faster than
`mass storage device 30, it still does not operate as quickly
`as instruction issuing unit 14 or instruction pipelines
`18A—H. Consequently, computing system 10 includes a high
`speed cache memory 60 for storing a subset of data from
`main memory 34, and a very high speed register file 64 for
`storing a subset of data from cache memory 60. Cache
`memory 60 communicates with main memory 34 over a
`communication path 68 and with register file 64 over a
`communication path 72. Register file 64 communicates with
`instruction pipelines 18A—H over a communication path 76.
`Register file 64 operates at approximately the same speed as
`instruction issuing unit 14 and instruction pipelines 18A—H
`(e.g., a fraction of a clock cycle), whereas cache memory 60
`operates at a speed somewhere between register file 64 and
`main memory 34 (e.g., approximately two or three clock
`cycles).
`FIGS. 2A—B are block diagrams illustrating the concept
`of virtual addressing. Assume computing system 10 has 32
`bits available to address data. The addressable memory
`space is then 232 bytes, or four gigabytes (4 GB), as shown
`in FIG. 2A. However, the physical (real) memory available
`in main memory 34 typically is much less than that, e.g.,
`1-256 megabytes. Assuming a 16 megabyte (16 MB) real
`memory, as shown in FIG. 2B, only 24 address bits are
`needed to address the memory. Thus, multiple virtual
`addresses inevitably will be translated to the same real
`address used to address main memory 34. The same is true
`for cache memory 60, which typically stores only 1-36
`kilobytes of data. Register file 64 typically comprises, e.g.,
`32 32-bit registers, and it stores data from cache memory 60
`as needed. The registers are addressed by instruction pipe-
`lines 18A—H using a different addressing scheme.
`
`2
`To accommodate the difference between virtual addresses
`and real addresses and the mapping between them, the
`physical memory available in computing system 10 is
`divided into a set of uniform-size blocks, called pages. If a
`5 page contains 212 or 4 kilobytes (4 KB), then the full 32-bit
`address space contains 220 or 1 million (1M) pages (4
`ICBx1M=4 GB). Of course, if main memory 34 has 16
`megabytes of memory, only 212 or 4K of the 1 million
`potential pages actually could be in memory at the same time
`to (4Kx4 KB=16 MB).
`Computing system 10 keeps track of which pages of data
`from the 4 GB address space currently reside in main
`memory 34 (and exactly where each page of data is physi-
`cally located in main memory 34) by means of a set of page
`15 tables 100 (FIG. 3) typically stored in main memory 34.
`Assume computing system 10 specifies 4 KB pages and each
`page table 100 contains 1K entries for providing the location
`of 1K separate pages. Thus, each page table maps 4 MB of
`memory (1Kx4KB=4 MB), and 4 page tables suffice for a
`20 machine with 16 megabytes of physical main memory (16
`MB/4 MB=4).
`The set of potential page tables are tracked by a page
`directory 104 which may contain, for example, 1K entries
`(not all of which need to be used). The starting location of
`25 this directory (its origin) is stored in a page directory origin
`(PDO) register 108.
`To locate a page in main memory 34, the input virtual
`address is conceptually split into a 12-bit displacement
`30 address (VA<11:0›), a 10-bit page table address
`(VA<21:12>) for accessing page table 100, and a 10-bit
`directory address (<VA 31:22>) for accessing page directory
`104. The address stored in PDO register 108 is added to the
`directory address VA<31:22> of the input virtual address in
`a page directory entry address accumulator 112. The address
`in page directory entry address accumulator 112 is used to
`address page directory 104 to obtain the starting address of
`page table 100. The starting address of page table 100 is then
`added to the page table address VA<21:12> of the input
`40 virtual address in a page table entry address accumulator
`116, and the resulting address is used to address page table
`100. An address field in the addressed page table entry gives
`the starting location of the page in main memory 34 corre-
`sponding to the input virtual address, and a page fault field
`PF indicates whether the page is actually present in main
`memory 34. The location of data within each page is
`typically specified by the 12 lower-order displacement bits
`of the virtual address.
`When an instruction uses data that is not currently stored
`50 in main memory 34, a page fault occurs, and the faulting
`instruction abnormally terminates. Thereafter, data transfer
`unit 42 must find an unused 4 KB portion of memory in main
`memory 34, transfer the requested page from mass storage
`device 30 into main memory 34, and make the appropriate
`55 update to the page table (indicating both the presence and
`location of the page in memory). The program then may be
`restarted.
`FIG. 4 is a block diagram showing how virtual addresses
`are translated in the computing system shown in FIG. 1.
`60 Components which remain the same as FIGS. 1 and 3 retain
`their original numbering. An address register 154 receives
`an input virtual address which references data used by an
`instruction issued to one of instruction pipelines 14A—H, a
`translation memory (e.g., a translation lookaside buffer
`65 (TLB)) 158 and comparator 170 for initially determining
`whether data requested by the input virtual address resides
`in main memory 34, and a dynamic translation unit (DTU)
`
`45
`
`35
`
`15
`
`

`

`15
`
`The present invention is directed to a method and appa-
`ratus for translating virtual addresses in a computing system
`having multiple pipelines wherein a separate TLB is pro-
`vided for each pipeline requiring address translation ser-
`vices. Each TLB may operate independently so that it
`contains its own set of virtual-to-real address translations, or
`else each TLB in a selected group may be simultaneously
`updated with the same address translation information
`whenever the address translation tables in main memory are
`20 accessed to obtain address translation information for any
`other TLB in the group.
`In one embodiment of the present invention, a TLB is
`provided for each load/store pipeline in the system, and an
`address translator is provided for each such pipeline for
`translating a virtual address recievcd from its associated
`pipeline into corresponding real addresses. Each address
`translator comprises a translation buffer accessing circuit for
`accessing the TLB, a translation indicating circuit for indi-
`cating whether translation data for the virtual address is
`stored in the translation buffer, and an update control circuit
`for activating the direct address translation circuit when the
`translation data for the virtual address is not stored in the
`TLB. The update control circuit also stores the translation
`data retrieved from the main memory into the TLB. If it is
`desired to have the same translation information available
`for all the pipelines in a group, then the update control circuit
`also updates all the other TLB's in the group.
`
`35
`
`3
`162 for accessing page tables in main memory 34. Bits
`VA[18:12] of the input virtual address are communicated to
`TLB 158 over a communication path 166, bits VA[31:12] of
`the input virtual address are communicated to DTU 162 over
`a communication path 174, and bits VA[31:19] are commu-
`nicated to comparator 170 over a communication path 176.
`TLB 158 includes a plurality of addressable storage
`locations 178 that are addressed by bits VA[18:12] of the
`input virtual address. Each storage location stores a virtual
`address tag (VAT) 180, a real address (RA) 182 correspond- 10
`ing to the virtual address tag, and control information
`(CNTRL) 184. How much control information is included
`depends on the particular design and may include, for
`example, access protection flags, dirty flags, referenced
`flags, etc. (cid:9)
`The addressed virtual address tag is communicated to
`comparator 170 over a communication path 186, and the
`addressed real address is output on a communication path
`188. Comparator 170 compares the virtual address tag with
`bits VA[31:22] of the input virtual address. If they match (a
`TLB hit), then the real address output on communication
`path 188 is compared with a real address tag (not shown) of
`a selected line in cache memory 60 to determine if the
`requested data is in the cache memory (a cache hit). An
`example of this procedure is discussed in U.S. Pat. No. 25
`4,933,835 issued to Howard G. Sachs, et al. and incorpo-
`rated herein by reference. If there is a cache hit, then the
`pipelines may continue to run at their highest sustainable
`speed. If the requested data is not in cache memory 60, then
`the real address bits on communication path 188 are com- 30
`bined with bits [11:0] of the input virtual address and used
`to obtain the requested data from main memory 34.
`If the virtual address tag did not match bits VA[31:19] of
`the input virtual address, then comparator 170 provides a
`miss signal on a communication path 190 to DTU 162. The
`miss signal indicates that the requested data is not currently
`stored in main memory 34, or else the data is in fact present
`in main memory 34 but the corresponding entry in TLB 158
`has been deleted.
`When the miss signal is generated, DTU 162 accesses the
`page tables in main memory 34 to determine whether in fact
`the requested data is currently stored in main memory 34. If
`not, then DTU 162 instructs data transfer unit 42 through a
`communication path 194 to fetch the page containing the
`requested data from mass storage device 30. In any event,
`TLB 158 is updated through a communication path 196, and
`instruction issuing resumes.
`TLB 158 has multiple ports to accommodate the
`addresses from the pipelines needing address translation
`services. For example, if two load instruction pipelines and
`one store instruction pipeline are used in computing system
`10, then TLB 158 has three ports, and the single memory
`array in TLB 158 is used to service all address translation
`requests.
`As noted above, new virtual-to-real address translation
`information is stored in TLB 158 whenever a miss signal is
`generated by comparator 170. The new translation informa-
`tion typically replaces the oldest and least used entry pres-
`ently stored in TLB 158. While this mode of operation is 60
`ordinarily desirable, it may have disadvantages when a
`single memory array is used to service address translation
`requests from multiple pipelines. For example, if each
`pipeline refers to different areas of memory each time an
`address is to be translated, then the translation information 65
`stored in TLB 158 for one pipeline may not get very old
`before it is replaced by the translation information obtained
`
`5,463,750
`
`4
`by DTU 162 for the same or another pipeline at a later time.
`This increases the chance that DTU 162 will have to be
`activated more often, which degrades performance. The
`effect is particularly severe and counterproductive when a
`first pipeline repeatedly refers to the same general area of
`memory, but the translation information is replaced by the
`other pipelines between accesses by the first pipeline.
`
`SUMMARY OF THE INVENTION
`
`5
`
`ao
`
`45
`
`50
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a known computing system;
`FIGS. 2A and 2B are each diagrams illustrating virtual
`addressing;
`FIG. 3 is a diagram showing how page tables are accessed
`in the computing system shown in FIG. 1;
`FIG. 4 is a block diagram illustrating how virtual
`addresses are translated in the computing system shown in
`FIG. 1; and
`FIG. 5 is a block diagram of a particular embodiment of
`a multiple TLB apparatus for translating virtual addresses in
`a computing system according to the present invention.
`
`BRIEF DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIG. 5 is a block diagram of a particular embodiment of
`an apparatus 200 according to the present invention for
`translating virtual addresses in a computing system such as
`computing system 10 sho