throbber
(19)
`
`
`JAPANESE PATENT OFFICE (JP)
`
`(12) Official Gazette for Unexamined Patent
`
`Publications (A)
`
`5
`
`(11) Japanese Patent Application Publication No.:
`
`(43} Disclosure Date: December 4, 1998
`
`H10-320270
`
`
`(51)Int. c1.5:
`ID Symbols:
`Fl:
`
`G06F
`12/06
`515
`GOSF
`
`12/06
`
`515H
`
`10
`
`Request for Substantive Examination: Not yet submitted
`
`Number of Claims: 3 0L
`
`
`{Total of 5 pages [in the Japanese text])
`
`
`(21) Patent Application No.:
`H9—125328
`
`15
`
`(22) Filing Date:
`
`May 15, 1997
`
`(71} Applicant:
`
`
`Matsushita E'ectric "ndustrial Co. Ltd
`
`000005821
`
`.,
`
`1006 Oaza-
`
`Kadoma, Kadoma—shi, Osaka—fu
`
`20
`
`(72)
`
`Inventor:
`
`Kazuo TAKEDA
`
`
`c/o Matsushita Electric Industrial Co. Ltd., 1006 Oaza—
`
`Kadoma, Kadoma—shi, Osaka—Eu
`
`(74} Representative: Tomoyuki TAKIMOTO, Patent Attorney
`
`(and one other}
`
`25
`
`SanDisk
`Sanlfisk
`Ex. 1004
`EX.1004
`IPR of U.S. Pat. No. 8,081,536
`IPR of US. Pat. No. 8,081,536
`
`

`

`(54)
`
`[Title of the Invention] Memory module
`
`-2—
`
`(57)
`
`[Abstract]
`
`[Problem] The aim is to provide a memory module which
`
`achieves lower costs,
`
`reduced power consumption and low
`
`temperature rises using current—generation SDRAMs,
`
`if 'the
`
`resolving' a conventional. problenu namely that
`
`by
`
`capacity of an SDRAM memory module is increased,
`
`there
`
`is
`
`excessively
`
`large
`
`power
`
`consumption
`
`or
`
`an
`
`excessively large rise in temperature with current—
`
`configuration
`
`SDRAMs
`
`unless
`
`next—
`
`generation
`
`X1
`
`generation SDRAMs are present.
`
`
`[Means of Resolution]
`
`
`It
`
`is possible to reduce power
`
`conSumption and produce
`
`low temperature rises which
`
`cannot be achieved using only next—generation SDRAMs,
`
`
`by adopting a configuration composed o: a plurality of
`
`a plurality o:
`
`banks
`
`comprising
`
`current—generation
`
`SDRAMS,
`
`and a bank control unit
`
`for converting drive
`
`signals
`
`from outside the module, which are sent
`
`in
`
`order to control the plurality of banks,
`
`to signals for
`
`controlling the plurality of banks.
`
`
`
`10
`
`15
`
`20
`
`25
`
`

`

`[Patent Claims]
`
`[Claim 1] A memory module composed of:
`
`a plurality of
`
`banks
`
`comprising
`
`a plurality of
`
`current—generation
`
`SDRAMS
`
`for achieving increased. memory capacity with
`
`current—generation SDRAMs, which
`
`cannot
`
`be
`
`achieved
`
`using only next—generation SDRAMs;
`
`and a bank control
`
`unit
`
`for converting drive signals
`
`from outside the
`
`module, which
`
`are
`
`sent
`
`in
`
`order
`
`to
`
`control
`
`the
`
`plurality of banks,
`
`to signals
`
`for controlling the
`
`10
`
`plurality of banks.
`
`[Claim 2] The memory' module as
`
`claimed.
`
`in claim 1,
`
`composed of:
`
`a plurality of banks which are installed
`
`using an installation :method. enabling‘ a plurality of
`
`15
`
`current—generation SDRAMs
`
`to be installed in multiple
`
`stages, Such as TCP
`
`(tape carrier jpackaging);
`
`and. a
`
`bank control unit
`
`for converting' drive signals
`
`from
`
`outside the module, which are sent
`
`in order to control
`
`the plurality of banks,
`
`to signals for controlling the
`
`20
`
`plurality of banks.
`
`[Claim 3] The memory module as claimed in claim 1 or 2,
`
`in which the bank control unit is a one—chip unit.
`
`25
`
`
`[Detailed Description of the Invention]
`
`[000i]
`
`[Technical
`
`Field
`
`of
`
`the
`
`Invention]
`
`The
`
`present
`
`invention relates to a memory module which is used in a
`
`30
`
`35
`
`computer or the like.
`
`[0002]
`
`[Prior Art] Known configurations
`
`for memory modules
`
`which are used in computers
`
`and.
`
`the like have been
`
`disclosed.
`
`in JEDEC documents
`
`in the past. Figure
`
`4
`
`shows a conventional memory module structure, which is
`
`a 128 MB SDRAM module comprising sixteen 64 Mbit, X4
`
`configuration SDRAMs.
`
`[0003]
`
`

`

`-4—
`
`[Problem to be Resolved. by the Invention] However,
`
`there are problems with memory modules having the
`
`abovementioned conventional configuration in that it is
`
`necessary to use 64 Mbit
`
`SDRAMs
`
`(referred to here as
`
`“next—generation”
`
`components),
`
`and
`
`compared with
`
`configurations employing 16 Mbit
`
`SDRAMs
`
`(referred.
`
`to
`
`here
`
`as
`
`“current—generation"
`
`components),
`
`configurations employing next—generation components are
`
`more costly until
`
`the value of SDRAMs
`
`is bit crossed.
`
`10
`
`There are further problems in that when use is made of
`
`X1 bit configuration current—generation components,
`
`the
`
`number of SDRAMs driven at the same time increases so a
`
`
`
`greater
`
`
`amount or
`
`power
`
`is consumed,
`
`and the heat
`
`generated by DRAMs causes the temperature of the module
`
`15
`
`to rise.
`
`[0004] The aim of
`
`the present
`
`invention is to resolve
`
`these kinds of conventional problems by providing a
`
`20
`
`25
`
`30
`
`35
`
`large—capacity memory module which employs a multibit
`
`configuration of
`
`current—generation
`
`components,
`
`and
`
`therefore :makes
`
`it possible to reduce costs compared
`
`with using next—generation components,
`
`and also makes
`
`it possible to reduce the number of DRAMs driven at the
`
`same time compared with a system employing a current—
`
`generation Xl bit configuration,
`
`so power consumption
`
`is reduced and temperature rises are lowered.
`
`[0005]
`
`[Means
`
`for Resolving the Problem]
`
`In order to resolve
`
`the problem,
`
`the memory module according to the present
`
`invention
`
`is
`
`composed
`
`of:
`
`a plurality of
`
`banks
`
`comprising a plurality of current—generation SDRAMS for
`
`achieving
`
`increased memory
`
`capacity with
`
`current—
`
`generation SDRAMs, which cannot be achieved using only
`
`for
`
`and. a bank control unit
`
`next—generation SDRAMS;
`
`converting drive signals from outside the module, which
`
`are sent in order to control the plurality of banks,
`
`to
`
`signals for controlling the plurality of banks.
`
`

`

`[0006]
`
`By virtue of the configuration according to the present
`
`invention,
`
`it is possible to obtain a large capacity
`
`memory Inodule at
`
`lower cost
`
`than. a
`
`system. employing
`
`temperature next—generation components,
`
`and with lower
`
`
`
`temperature
`
`rises
`
`than
`
`a
`
`system employing
`
`a
`
`X1
`
`configuration with current-generation components,
`
`so it
`
`is a simple matter to install a large capacity memory
`
`in a set such as a computer, and an inexpensive memory
`
`10
`
`module can be obtained.
`
`[0007]
`
`Furthermore,
`
`it
`
`is
`
`problematic
`
`temperature
`
`rises
`
`also possible to reduce
`
`i:
`
`the
`
`DRAMs
`
`are
`
`15
`
`20
`
`installed.
`
`using
`
`an
`
`installation. method.
`
`enabling
`
`multiple stage installation,
`
`such as TCP
`
`(tape carrier
`
`packaging), and therefore the installation density can
`
`the size of
`
`the module can be reduced,
`
`be increased,
`
`and it is possible to obtain a compact,
`
`large—capacity
`
`memory module.
`
`[0008]
`
`[Mode of Embodiment of
`
`the Invention] The
`
`invention
`
`25
`
`30
`
`35
`
`disclosed.
`
`in clain1 l of
`
`the present
`
`invention is a
`
`memory module
`
`composed
`
`of:
`
`a plurality of
`
`banks
`
`comprising a plurality of current—generation SDRAMS for
`
`achieving
`
`increased memory
`
`capacity with
`
`current—
`
`generation SDRAMs, which cannot be achieved using only
`
`next—generation SDRAMs;
`
`and. a bank control unit
`
`for
`
`
`
`converting drive signals from outside the module, which
`
`are sent in order to control
`
`the plurality of banks,
`
`to
`
`signals for controlling the plurality of banks,
`
`action is afforded such that it is possible to obtain a
`
`so an
`
`large capacity memory module at
`
`lower cost
`
`than a
`
`system.
`
`employing
`
`temperature
`
`next—generation
`
`components,
`
`and. with lower
`
`temperature rises than a
`
`system employing
`
`a
`
`Xl
`
`configuration with
`
`current—
`
`generation components,
`
`so
`
`it
`
`is a
`
`simple matter
`
`to
`
`install
`
`a
`
`large capacity memory
`
`in a set
`
`such as
`
`a
`
`

`

`-6—
`
`computer,
`obtained.
`
`and
`
`an
`
`inexpensive memory module
`
`can be
`
`[0009] The invention disclosed in claim 2 is the memory
`
`module as claimed in claim 1, composed of: a plurality
`
`of banks which are installed. using an installation
`
`method enabling a plurality of current-generation DRAMs
`
`to be installed in multiple stages,
`
`such as TCP
`
`(tape
`
`carrier
`
`packaging);
`
`and
`
`a
`
`bank
`
`control unit
`
`for
`
`converting drive signals from outside the module, which
`
`are sent in order to control the plurality of banks,
`
`to
`
`signals for controlling the plurality of banks,
`
`
`
`
`action is a
`”orded such that
`
`the memory module can be
`
`so an
`
`made compact.
`
`5
`
`10
`
`15
`
`[0010]
`
`The
`
`invention disclosed.
`
`in claim 3
`
`is
`
`the
`
`memory module as claimed in claim 1 or 2,
`
`in which the
`
`bank control unit
`
`is a one—chip unit,
`
`so an action is
`
`afforded such that it is possible to obtain a compact
`
`20
`
`memory module.
`
`25
`
`30
`
`35
`
`[0011] A mode of embodiment of
`
`the present
`
`invention
`
`will be described below with the aid of Figures 1
`
`to 3.
`
`Figure 1
`
`is a block diagranl
`
`showing a plurality of
`
`banks
`
`composed
`
`of
`
`a plurality of multibit
`
`DRAMs
`
`according to a first mode of embodiment of the present
`
`invention; Figure 2
`
`is a block diagranl of
`
`the bank
`
`control unit for converting drive signals from outside
`
`the module into signals for controlling the plurality
`
`of banks; and Figure 3
`
`jj; a timing chart
`
`showing the
`
`In
`
`in Figure 2.
`
`operation of
`
`Figure 1, D0—D63
`
`are SDRAMs
`
`the bank control unit
`
`in four banks, where D0 —
`
`D15 form bank 0, D16 — D31 form bank 1, D32 — D47 form
`
`bank 2, and D48 — D63 form bank 3.
`
`[0012] The operation of this mode of embodiment will be
`
`described below with the aid of Figures 1,
`
`2 and 3.
`
`Drive signals /RE,
`
`/CE,
`
`/WE, A12, A13 etc.
`
`from outside
`
`the nodule are input
`
`to the memory module. The bank
`
`
`
`

`

`-7—
`
`control unit
`
`shown in Figure 2
`
`identifies SDRAM bank
`
`active commands
`
`(when /RE;
`
`“L”,
`
`/CE;
`
`“H”,
`
`/WE;
`
`“H")
`
`using the signals
`
`/RE,
`
`/CE,
`
`/WE,
`
`decodes A12, A13,
`
`performs bank selection,
`
`and sets
`
`/CS
`
`(chip select
`
`signal), which
`
`corresponds
`
`to a
`
`selected bank,
`
`to
`
`active (“L").
`
`[0013] Period (1)
`
`in Figure 3 involves active commands,
`
`as described above, and A12 is “L” and A13 is “L”,
`
`so
`
`two from among /CSO to 7, namely /C80 and /CS4 are set
`
`to “L" in order to select bank 0 which is composed of
`
`SDRAMs D0 — D15 shown in Figure l, but the other banks
`
`are in an inactive state.
`
`[0014] Period (2)
`
`in Figure 3
`
`involves write commands
`
`to the SDRAMs, but writing is performed only to the
`
`selected. bank.
`
`0
`
`and.
`
`the other banks
`
`1
`
`to 3 do not
`
`operate. Period
`
`(3)
`
`in Figure
`
`3
`
`involves precharge
`
`and precharging is performed
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`commands
`
`to the SDRAMs,
`
`only for the bank 0 and the other banks do not operate,
`
`in the same way as in period (2).
`
`[0015]
`
`In the same way subsequently,
`
`in period (4)
`
`in
`
`Figure 3, only bank.
`
`1
`
`is active,
`
`in period.
`
`(7)
`
`Figure 3,
`
`bank 2
`
`is active,
`
`and.
`
`in period.
`
`(10)
`
`in
`
`in
`
`Figure 3, bank 3 is active. As a result, it is possible
`
`to achieve equivalent operation to that of a system in
`
`which a 64 bit memory is made up of the conventional 64
`
`Mbit SDRAMs
`
`shown in Figure 4. Furthermore,
`
`the banks
`
`are active one at a time,
`
`so in other words the active
`
`SDRAMs constitute 1/4 of the total number of SDRAMs
`
`in
`
`the memory module. Power consumption for the inactive
`
`SDRAMs
`
`is close to the power consumed during standby
`
`and is very low compared with the power consumed during
`
`it
`
`operation.
`
`is therefore possible for
`
`the memory
`
`module
`
`to
`
`operate
`
`at
`
`approximately
`
`1/4
`
`power
`
`consumption.
`
`[0016]
`
`

`

`-8—
`
`
`
`[Advantage of the Invention] The memory module obtained
`
`in the manner described above produces an advantageous
`
`effect
`
`in that
`
`low power consumption (low temperature
`
`rises} which can be achieved by using 64 Mbit
`
`SDRAMs
`
`can be achieved using 16 Mbit SDRAMs,
`
`so costs can be
`
`reduced.
`
`[0017]
`
`It
`
`should be noted that
`
`in this mode
`
`of
`
`embodiment,
`
`the current—generation components were 16
`
`Mbit
`
`SDRAMs while the next—generation components were
`
`64 Mbit
`
`but
`
`the
`
`SDRAMs,
`
`achieved if the generations are advanced so that
`
`same effect
`
`can still be
`
`the
`
`[Figure 1]
`
`0:
`
`current-generation components are 64 Mbit SDRAMs while
`
`the next—generation components are 256 Mbit SDRAMs.
`
`[Detailed Description of the Invention]
`
`
`is a block diagram showing the configuration
`
`the plurality of banks composed of a plurality of
`
`multibit DRAMs,
`
`in accordance with a mode of embodiment
`
`of the present invention;
`
`[Figure 2]
`
`is a block diagram of the bank control unit
`
`for converting' drive signals from outside the :module
`
`into signals for controlling the plurality of banks,
`
`in
`
`accordance with a mode of
`
`embodiment of
`
`the present
`
`10
`
`15
`
`20
`
`25
`
`invention;
`
`[Figure 3]
`
`is a timing chart showing the operation of
`
`the bank control unit in Figure 2,
`
`in accordance with a
`
`mode of embodiment o: the present invention; and
`
`
`
`[Figure 4]
`
`is a block diagram of a memory module, which
`
`is
`
`a
`
`conventional
`
`128
`
`MB
`
`SDRAM module
`
`comprising
`
`sixteen 64 Mbit, X4 configuration SDRAMs.
`
`[Key to Symbols]
`
`DO — D63
`
`SDRAM (synchronous DRAM)
`
`30
`
`35
`
`

`

`[Figure 2]
`
`[Figure 3]
`
`
`
`[Figure 1]
`
`
`
`”IE—Mb magnum no— 53 IE? Fame-2
`{CEM museum no $3 $3 Fauna:
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`_ 8/me SBRAM so we:
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`Vs: i9 5mm 55-. neg
`CLKG'vi WCLKESOH‘M‘ Ila-£3
`
`

`

`_10_
`
`[Figure 4]
`
` .
`
`.-
`
`.
`.
`.
`£_
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`. 4'.
`mw—r-wm 59-”
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`5155n4_._.~<}cix:5flflfiflfiflif
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`

`

`~E
`
`d
`
`TRANSPERFECT
`
`City ofNew York, State of New York, County of New York
`
`1, Lindsay Young, hereby certify that the following document “Japanese refl6]” is, to the
`best of my knowledge and belief, a true and accurate translation from Japanese into
`English.
`
`
`
`Sworn to before me this
`
`Wednesday, March 25, ZOIS
`
`" 1m LEONG
`25 I
`t Notary Public — State of New York
`No. 01L86314554
`Qualified in Richmond County
`Qommissron Expires New 10. 201B
`
`
`
`
`
`

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