Trials@uspto.gov
`Tel: 571-272-7822
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`Paper 9
`Entered: October 13, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD, SAMSUNG ELECTRONICS
`AMERICA, INC., and SAMSUNG SEMICONDUCTOR, INC,
`Petitioner,
`
`v.
`
`NVIDIA CORPORATION,
`Patent Owner.
`
`Case IPR2015-01028
`Patent 6,198,488 B1
`
`Before KEVIN F. TURNER, BEVERLY M. BUNTING, and
`JON B. TORNQUIST, Administrative Patent Judges.
`
`BUNTING, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`Tel: 571-272-7822
`
`Paper 9
`Entered: October 13, 2015
`
`
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD, SAMSUNG ELECTRONICS
`AMERICA, INC., and SAMSUNG SEMICONDUCTOR, INC,
`Petitioner,
`
`v.
`
`NVIDIA CORPORATION,
`Patent Owner.
`
`Case IPR2015-01028
`Patent 6,198,488 B1
`
`Before KEVIN F. TURNER, BEVERLY M. BUNTING, and
`JON B. TORNQUIST, Administrative Patent Judges.
`
`BUNTING, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`IPR2015-01028
`Patent 6,198,488 B1
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`I. INTRODUCTION
`Samsung Electronics Co., Ltd., Samsung Electronics America, Inc.,
`and Samsung Semiconductor, Inc. (collectively, “Petitioner”) filed a Petition
`requesting inter partes review of claims 1 and 20 (the “challenged claims”)
`of U.S. Patent No. 6,198,488 B1 (Exhibit 1004, “the ’488 patent”) pursuant
`to 35 U.S.C. §§ 311–319. Paper 2 (“Pet.”). Patent Owner, NVIDIA
`Corporation (“Patent Owner”) timely filed a Preliminary Response to the
`Petition. Paper 8 (“Prelim. Resp.”). We have jurisdiction under 35 U.S.C.
`§ 314, which provides that an inter partes review may not be instituted
`“unless . . . there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.”
`Upon consideration of the information presented in the Petition and
`Preliminary Response, and for the reasons explained below, we determine
`that Petitioner has established a reasonable likelihood of prevailing on at
`least one ground with respect to claim 20, but not with respect to claim 1.
`Accordingly, we institute an inter partes review of claim 20.
`
`
`II. BACKGROUND
`A. Related Matters
`The parties indicate that the ’488 patent is the subject of the following
`
`judicial matters:
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`2
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`1. NVIDIA Corporation v. Samsung Electronics Co., Ltd., No.
`1:14-cv-01127 (D. Del. filed September 5, 2014); and
`2. Certain Consumer Electronics And Display Devices With
`Graphics Processing And Graphics Processing Units Therein,
`Investigation No. 337-TA-932 (USITC).
`Pet. 1; Paper 6, 2.1
`
`
`B. The ’488 Patent (Ex. 1004)
`The ’488 patent issued March 6, 2001, from U.S. Patent Application
`No. 09/454,516, filed on December 6, 1999. Ex. 1004, at [45], [21], [22].
`The ’488 patent is directed to a graphics hardware system and method for
`graphics processing. Id. at Abstract. The system includes a transform
`module for transforming graphics data, a lighting module for lighting the
`graphics data, and a rasterizer for rendering the graphics data. Id. at 3:4–11.
`These modules are positioned on a single semiconductor platform, as shown
`in Figure 1A, reproduced below.
`
`
`1 In IPR 2015-01029, Petitioner challenges a related patent, U.S. Patent No.
`6,992,667.
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`Figure 1A illustrates the single semiconductor platform.
`The single semiconductor platform is described as “a sole unitary semi-
`conductor-based integrated circuit or chip.” Id. at 6:50–51. In addition to
`converting object space vertex data into screen space and generating vectors
`for the lighting module, the transform module also performs processes
`skinning and texture coordinates. Id. at 10:44–45.
`
`Mode bits 202 associated with the vertex attribute buffer (VAB) 50
`are used to drive the sequencers of the transform module and lighting
`module “to execute a specifically tailored program sequence.” Id. at 9:62–
`10:3, 17:1–9; Fig. 3, Fig. 14. Figure 4a shows the execution of multiple
`threads in the transform module, i.e., processing three threads in parallel via
`interleaving. Id. at 10:49–53. Three commands can be processed in parallel,
`are independent of each other, “and can be any command since all vertices
`contain unique corresponding mode bits 202.” Id. at 10:53–59.
`
`The sequencer for the transform module is shown in Figure 12,
`reproduced below.
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`Fig. 12 is a schematic diagram of the transform module sequencer.
`“[S]equencer 1200 of transform module 52 includes a buffer 1202
`adapted for receiving the mode bits from VAB 50 that are indicative of the
`status of a plurality of modes of process operations.” Id. at 16:34–40. As
`further described in Fig. 16, the lighting module likewise includes a
`sequencer (id. at 25:31–33, Figure 23) that operates three threads in a
`manner similar to the transform module. Id. at 20:66–21:2.
`
`
`C. Illustrative Claim
`Challenged claims 1 and 20 of the ’488 patent are independent. Claim
`1 is illustrative of the challenged claims and is reproduced below:
`1. A graphics pipeline system for graphics processing,
`comprising:
`(a) a transform module adapted for being coupled to a
`buffer to receive vertex data therefrom, the transform
`module being positioned on a single semiconductor
`platform for transforming the vertex data from object
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`space to screen space;
`
`(b) a lighting module coupled to the transform module
`and positioned on the same single semiconductor platform
`as the transform module for performing lighting
`operations on the vertex data received from the transform
`module; and
`
` (
`
` c) a rasterizer coupled to the lighting module and positioned
`on the same single semiconductor platform as
`the transform module and lighting module for rendering
`the vertex data received from the lighting module;
`
`(d) wherein at least one of the transform module and the
`lighting module includes a sequencer for executing
`multiple threads of operation in parallel through a
`plurality of logic units thereof.
`
`Ex. 1004, 35:43–63.
`
`
`D. Evidence Relied Upon
`Petitioner relies on the following prior art references (Pet. 3):
`Reference
`Patent/Printed Publication
`Date
`Exhibit
`
`Deering et al.
`“Deering”
`TI Article
`
`TI Data
`Sheet
`
`
`
`U.S. Patent No. 6,424,343 B1
`
`M.B. Akhan et al., Faster Scan
`Conversion Using the
`TMS320C80
`[Literature Number SPRA330].
`Texas Instruments, TMS320C80
`Digital Signal Processor Data
`Sheet [Literature Number
`SPRS023B].
`
`July 23,
`2002
`1997
`
`1005
`
`1006
`
`1997
`
`1007
`
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`E. Asserted Grounds of Unpatentability
`Petitioner challenges claims 1 and 20 of the ’488 patent based on the
`asserted grounds of unpatentability set forth in the table below. Pet. 4. In
`support of the grounds of unpatentability referenced below, Petitioner relies
`on the Declaration of Dr. Dinesh Manocha. Ex. 1001.
`
`Reference
`
`Basis
`
`Claims
`Challenged
`
`Deering
`
`§ 102(e)
`
`1 and 20
`
`TI article and TI Data Sheet
`
`§ 103
`
`1 and 20
`
`
`
`III. ANALYSIS
`A. Claim Interpretation
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b); see also In re Cuozzo
`Speed Tech., LLC, 739 F.3d 1268, 1278–79 (Fed. Cir. 2015) (“Congress
`implicitly approved the broadest reasonable interpretation standard in
`enacting the [America Invents Act],” and “the standard was properly
`adopted by PTO regulation”). Under the broadest reasonable interpretation
`standard, and absent any special definitions, claims terms are given their
`ordinary and customary meaning, as would be understood by one of ordinary
`skill in the art in the context of the entire disclosure. In re Translogic Tech.,
`Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special definitions for
`claim terms or phrases must be set forth with reasonable clarity,
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`deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
`1994). In the absence of such a definition, limitations are not to be read
`from the specification into the claims. In re Van Geuns, 988 F.2d 1181,
`1184 (Fed. Cir. 1993). Only those terms that are in controversy need be
`construed, and only to the extent necessary to resolve the controversy. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Petitioner proposes a claim construction for each of the following
`claim terms: “single semiconductor platform,” “transforming,” and
`“lighting.” Pet. 5–6. In turn, Patent Owner contends that the claim term
`“single semiconductor platform” be afforded its plain and ordinary meaning,
`and agrees generally with Petitioner’s proffered claim construction for the
`claim terms “transforming” and “lighting.” Prelim. Resp. 6–8.
`Although the parties raise several claim limitations as needing or not
`needing specific construction, on this record and for purposes of this
`decision, we determine that no claim term requires express construction.
`
`
`B. Prior Art Relevance
`We initially address Patent Owner’s argument that trial should not be
`instituted because Deering, the TI Article, and the TI Data Sheet “are less
`pertinent than the art considered in the ’488 file history.” Prelim. Resp. 15
`(emphasis omitted). Specifically, Patent Owner asserts that because the
`Examiner cited WO 99/52040 (“Rubinstein”) during prosecution of the
`patent application that resulted in the ’488 patent (Ex. 2055), “Rubenstein is
`more pertinent prior art than Deering or TI.” Id. at 16. Patent Owner,
`however, does not offer adequate explanation or evidence as to how or why
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`Rubenstein would be more pertinent than either Deering, the TI Article, or
`the TI Data Sheet. Thus, on this record, Patent Owner’s argument in this
`regard is not persuasive.
`
`
`C. Anticipation by Deering
`We now turn to Petitioner’s asserted grounds of unpatentability and
`Patent Owner’s arguments in its Preliminary Response. Petitioner
`challenges claims 1 and 20 as anticipated under 35 U.S.C. § 102(e) by
`Deering. Pet. 13–30. Petitioner explains how Deering describes the claimed
`subject matter of the challenged claims and cites the Declaration of Dr.
`Manocha (Ex. 1001 ¶¶ 65–90) to support the analysis advocated in the
`Petition. Id. Patent Owner counters that Deering does not disclose the claim
`limitations “wherein at least one of the transform module and the lighting
`module includes a sequencer for executing multiple threads of operation in
`parallel through a plurality of logic units thereof” (Prelim. Resp. 23–25) and
`“a lighting module coupled to the transform module” (id. at 25–27).
`Having considered the explanations and supporting evidence
`presented, we are persuaded that Petitioner has presented evidence
`demonstrating sufficiently that Deering discloses the claim limitations as
`recited in claim 20, but not claim 1. A detailed analysis of our determination
`follows after a brief overview of Deering.
`
`1. Overview of Deering (Ex. 1005 )
`
`Deering issued July 23, 2002, from U.S. Patent Application No.
`09/251,453, filed on February 17, 1999. Ex. 1005, at [45], [21], [22].
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`Deering claims priority to U.S. Provisional Application No. 60/074,836
`(“Deering Provisional”) filed on February 17, 1998. Id. at [60].
`Deering is directed to a computer graphics system. Id. at 1:10–12.
`
`The computer system includes a central processing unit 102, also referred to
`as a host processor that is coupled to a system bus. Id. at 8:33–37. Also
`coupled to the bus is a graphics system 112 (id. at 8:51–53) and the host
`processor transfers information to and from the graphics system over the
`host bus (id. at 8:66–9:4). In one embodiment, the host processor transmits
`graphics data over the host bus to the graphics system 112. Id. at 9:13–15.
`The graphics system 122 may “be configured as a single chip device or as
`part of a system-on-a-chip or a multi-chip module.” Id. at 9:34–36. As
`shown in Figure 3 reproduced below, the graphics system may include one
`or more control units 140, one or more data memories 152 A-D, and one or
`more schedule units 154. Id. at 9:38–55.
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`Figure 3 is a block diagram of the graphics system.
`The control unit “operates as the interface between the graphics
`system 112 and computer system 80 by controlling the transfer of data
`between graphics system 112 and computer system 80.” Id. at 9:57–60. “In
`embodiments of graphics system 112 that comprise two or more rendering
`units 150A-D, control unit 140 may also divide the stream of data received
`from computer system 80 into a corresponding number of parallel streams
`that are routed to the individual rendering units 150A-D.” Id. at 9:60–65.
`These rendering units 150A–D, receive the graphics instructions and data
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`from control unit 140, and may be configured to perform decompression,
`transformation, clipping, lighting, texturing, depth cuing, transparency
`processing, set-up, and screen space rendering of various graphics primitives
`occurring within the graphics data. Id. at 10:17–26. Schedule unit 154 may
`be coupled between the rendering units and sample memories, and
`configured to sequence the completed samples (filtered pixels forming an
`output pixel) and store them in memories 160A–N. Id. at 11:45–48.
`
`2. Discussion
`Patent Owner asserts first that Deering is not prior art to the
`challenged claims of the ’488 patent under 35 U.S.C. §102(e), because the
`claimed invention was conceived before the February 17, 1999 filing date of
`Deering, as well as the February 17, 1998 filing date of the Deering
`Provisional, and diligently reduced to practice at least as early as May,
`1999.2 Prelim. Resp. 17–22. Further, Patent Owner asserts that Deering
`should not receive the benefit of the February 17, 1998 provisional
`application filing date “because Petitioners’ anticipation arguments rely on
`features of Deering that are not disclosed in the Deering Provisional.” Id. at
`16.
`Under 35 U.S.C. § 102(e)(2), “[a] person shall be entitled to a patent
`
`unless . . . (e) the invention was described in . . . (2) a patent granted on an
`application for patent by another filed in the United States before the
`
`
`2 Section 3(b) of the Leahy-Smith America Invents Act altered the §102
`conditions for patentability; novelty. Pub. L. No. 112-29, 125 Stat. 284,
`285–287 (2011). Because the ’488 patent has a filing date before September
`16, 2012 (effective date), we refer to the pre-AIA § 102(e) in this Decision.
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`invention by the applicant for patent.” Accordingly, to determine whether a
`patent application is prior art to a patentee’s claimed invention under
`§ 102(e)(2), it is necessary to determine the patentee’s date of invention. As
`defined by the Federal Circuit, “[t]he invention date is the date of
`conception.” Allergan, Inc. v. Apotex Inc., 754 F.3d 952, 967 (Fed. Cir.
`2014) (citing Invitrogen Corp. v. Clontech Labs., Inc., 429 F.3d 1052, 1063
`(Fed. Cir. 2005)). “Conception is the ‘formation in the mind of the inventor,
`of a definite and permanent idea of the complete and operative invention, as
`it is hereafter to be applied in practice.’” Hybritech Inc. v. Monoclonal
`Antibodies, Inc., 802 F.2d 1367, 1376 (Fed. Cir. 1986) (citations omitted).
`“An idea is definite and permanent when the inventor has a specific, settled
`idea, a particular solution to the problem at hand, not just a general goal or
`research plan he hopes to pursue.” Burroughs Wellcome Co. v. Barr Labs.,
`Inc., 40 F.3d 1223, 1228 (Fed. Cir. 1994). “A conception must encompass
`all limitations of the claimed invention.” Singh v. Brake, 317 F.3d 1334,
`1340 (Fed. Cir. 2003) (citations omitted). An inventor’s testimony regarding
`his own prior inventorship must be corroborated:
`It is well-established in our case law that a party claiming his
`own prior inventorship must proffer evidence corroborating his
`testimony. . . . “This rule addresses the concern that a party
`claiming inventorship might be tempted to describe his actions
`in an unjustifiably self-serving manner in order to obtain a
`patent or to maintain an existing patent.” . . . “[A] ‘rule of
`reason’ analysis is applied to determine whether an inventor’s
`testimony . . . has been corroborated.” . . . In applying the
`“rule of reason” test, “all pertinent evidence” is examined in
`order to determine whether the “inventor’s story” is credible.
`. . . “[E]ach corroboration case must be decided on its own
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`facts with a view to deciding whether the evidence as a whole is
`persuasive.”
`
`Sandt Tech., Ltd. v. Resco Metal & Plastics Corp., 264 F.3d 1344,
`1350 (Fed. Cir. 2001) (internal citations omitted).
`To support its contentions, Patent Owner proffers evidence allegedly
`describing certain features of the chip embodied in the claims of the ’488
`patent. This evidence, however, does not include testimonial evidence from
`the inventors of the ’488 patent tending to show formation in the inventors’
`minds of a definite and permanent idea of the complete and operative
`invention. Nor does Patent Owner explain why such evidence is
`unavailable.
`On the present record, and for purposes of this Decision, Patent
`Owner’s arguments and evidence are insufficient to show invention prior to
`either the February 17, 1998 filing date of the Deering Provisional, or the
`February 17, 1999 filing date of Deering. Because Patent Owner has not
`established conception and diligent reduction to practice, for purposes of this
`Decision, we need not address arguments advanced by Patent Owner as to
`whether Deering is entitled to the filing date of the Deering Provisional.
`
`a. Claim 1
`Having determined above that Deering is prior art, we next consider
`whether claim 1 is anticipated by Deering. To establish anticipation, “all of
`the elements and limitations of the claim must be shown in a single prior
`reference, arranged as in the claim” Karsten Mfg. Corp. v. Cleveland Golf
`Co., 242 F.3d 1376, 1383 (Fed. Cir. 2001); see also Kennametal, Inc. v.
`Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381 (Fed. Cir. 2015). “A claim
`
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`is anticipated only if each and every element as set forth in the claim is
`found, either expressly or inherently described, in a single prior art
`reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628,
`631 (Fed. Cir. 1987). We analyze this asserted ground based on anticipation
`with the principles identified above in mind.
`Independent claim 1 recites, in relevant part, “wherein at least one of
`the transform module and the lighting module includes a sequencer for
`executing multiple threads of operation in parallel through a plurality of
`logic units thereof.” Petitioner contends that the “transform module”
`limitation is met by both the control unit 140 and rendering units 150 A-D
`shown in Figure 3 of Deering. Pet. 20. To support its contentions,
`Petitioner directs our attention to the disclosure in Deering regarding the
`division, by the control unit 140, of “the stream of data received from
`computer system 80 into a corresponding number of parallel streams that are
`routed to the individual rendering units 150A–D.” Id. (citing Ex. 1005,
`9:61–65). Also relying on the testimony of its Declarant, Petitioner asserts
`that “control unit 140 forms the sequencer for rendering units 150A–D (i.e.
`the transform, lighting, and rasterizer modules).” Id. (citing Ex. 1001 ¶ 80).
`To further demonstrate which teachings in Deering satisfy the limitations of
`claim 1, the Petitioner includes a claim chart identifying quotations in the
`reference that correspond with claim elements. Id. at 23–29.
`In response, Patent Owner argues that the “transform module” or
`“lighting module” of Deering is not “capable of ‘executing multiple threads
`of operation in parallel through a plurality of logic units thereof.’” Prelim.
`Resp. 23. According to Patent Owner, claim 1 requires that the “plurality of
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`logic units” all be part of the same “transform module” or “lighting module.”
`Id. Thus, Patent Owner contends that “the execution of multiple threads of
`operation in parallel occurs through the plurality of logic units within a
`single processing module.” Id. (citing Ex. 1004, 10:28–12:12, 12:29–15:55,
`20:48–25:30). To support this contention, Patent Owner directs us to
`portions of the Specification of the ’488 patent “describing the plurality of
`functional logic units comprising the transform module” (id. (citing Ex.
`1004, 12:29–15:55)) and “describing the plurality of functional logic units
`within the lighting module” (id. (citing Ex. 1004, 20:48–25:30)).
`To the extent Patent Owner argues that the claim 1 requires that the
`“plurality of logic units” be part of the same “transform module” or “lighting
`module,” we agree. With respect to the transform module, Figure 5 of the
`Specification describes operation of “the functional units of transform
`module 52.” Ex. 1004, 12:30–31, Fig. 5. Similarly, for the lighting module,
`Figure 16 describes operation of “the functional units of lighting module
`54.” Id. at 21:4–5, Fig. 16. On this point Petitioner seemingly agrees
`because Petitioner relies on rendering blocks 150A–D of Deering to meet the
`“plurality of logic units” limitation as well as the “transform module” and
`“lighting module” limitations. Pet. 16–18; Ex. 1001 ¶¶ 67–73. Thus, on this
`record, Patent Owner argues persuasively that “it would be unreasonable to
`interpret claim 1 to allow for the execution of multiple threads of operation
`across separate independent processors when claim 1 clearly requires that
`the execution of multiple threads in parallel occur through a plurality of
`logic units within a single processing module.” Prelim. Resp. 23.
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`Along this vein, Patent Owner further challenges Petitioner’s reliance
`on the control unit and two or more rendering units of Deering to meet the
`“transformation module or lighting module” limitations, as well as the
`rendering units to meet the “plurality of logic units thereof” limitation. Id. at
`24. Patent Owner first directs our attention to Deering’s explanation of how
`the rendering units “may be any suitable type of high performance processor
`(e.g., specialized graphics processors or calculation units, multimedia
`processors, DSPs, or general purpose processors).” Id. (citing Ex. 1005,
`10:51–54). Patent Owner notes that Petitioner’s Declarant opined that each
`rendering unit “is an independent processor that can perform both transform
`and lighting operations.” Id. (citing Ex. 1001 ¶¶ 76, 80). Based on its
`understanding of claim 1, Patent Owner takes the position that each
`rendering unit cannot be “a logic unit within a processing module” if each
`rendering unit is also a processing module that can act as either “a transform
`module or lighting module.” Id. at 25.
`Neither Petitioner nor its Declarant explains sufficiently how the
`rendering units 150A–D of Deering can concurrently meet the “transform
`module or lighting module” and “plurality of logic unit” limitations. In this
`regard, Petitioner has not demonstrated sufficiently that each and every
`element of claim 1, arranged as is recited in the claim, may be found in
`Deering. Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed.
`Cir. 2008). Instead, we are more persuaded by Patent Owner’s argument
`that “Deering does not disclose that each rendering unit is capable of
`executing multiple threads of operation in parallel through a plurality of
`logic units.” Prelim. Resp. 25.
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`b. Claim 20
`Claim 20 is directed to a method for graphics processing, and includes
`in relevant part the limitation of “executing multiple threads of operation in
`parallel through a plurality of logic units while at least one of transforming
`and lighting the vertex data.” Ex. 1004, 37:43–53. Petitioner asserts that
`this limitation is satisfied by the description in Deering of how the control
`unit “can divide a data stream into a corresponding number of parallel
`streams that are routed to the rendering units for processing.” Pet. 22.
`Patent Owner counters that Deering discloses the execution of multiple
`threads of operation in parallel across multiple independent processors, and
`not “through the plurality of logic units within a single processing module.”
`Prelim. Resp. 28.
`We are not persuaded by Patent Owner’s arguments in this regard
`because its contentions are not commensurate in scope with the features of
`claim 20. Patent Owner’s arguments are predicated on the notion that claim
`20, like claim 1, recites specifically a “transform module” or “lighting
`module.” Instead, claim 20 recites the steps of “transforming vertex data”
`and “lighting the vertex data.” Nor does claim 20 recite specifically the
`execution of multiple threads of operation in parallel through a plurality of
`logic units within a single processing module, as Patent Owner suggests.
`Patent Owner does not direct us to, nor can we find, language in claim 20
`requiring that the logic units be within a single processing module.
`
`3. Summary
`Having considered fully the parties arguments and evidence
`concerning anticipation by Deering of the challenged claims, on the current
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`record, we are persuaded Petitioner has demonstrated a reasonable
`likelihood that it would prevail in showing anticipation of claim 20. We are
`not persuaded, on this record, that Petitioner has demonstrated a reasonable
`likelihood that it would prevail in showing anticipation of claim 1 by
`Deering. Accordingly, we institute an inter partes review of claim 20 as
`anticipated by Deering, and we do not institute an inter partes review of
`claim 1.
`
`
`D. Obviousness Based on TI Article (Ex. 1006) and
`TI Data Sheet (Ex. 1007)
`Petitioner next challenges the patentability of claims 1 and 20 under
`35 U.S.C. § 103(a) based on the TI Article and TI Data Sheet (collectively
`“TI References”). Pet. 30–55. Petitioner explains how these references
`describe the claimed subject matter of the challenged claims and cites the
`Declaration of Dr. Manocha (Ex. 1001 ¶¶ 91–122) to support the analysis
`advocated in the Petition. Id. Patent Owner counters that the TI References
`do not disclose a lighting module, nor the claim limitation “wherein at least
`one of the transform module and the lighting module includes a sequencer
`for executing multiple threads of operation in parallel through a plurality of
`logic units thereof.” Prelim. Resp. 32–37.
`Having considered the explanations and supporting evidence
`presented, we are not persuaded that Petitioner has presented evidence
`demonstrating sufficiently that the TI References disclose the claim
`limitation of a “lighting module” as recited in challenged claims 1 and 20. A
`
`19
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`detailed analysis of our determination follows after a brief overview of the
`TI References.
`
`1. Overview of the TI Article (Ex. 1006)
`The TI Article is a non-patent publication describing the process for
`parallizing the scan conversion stage of the Texas Instrument TMX320C80
`digital signal processor. Ex. 1006, 7. Figure 1, reproduced below, is
`representative of a graphics pipeline for converting 3D polygons to pixel
`information. Id. at 9.
`
`Figure 1 is a block diagram of a rendering pipeline.
`
`
`
`2. Overview of the TI Data Sheet (Ex. 1007)
`The TI Data Sheet is a non-Patent publication from Texas Instruments
`describing the features and specifications for the TMS320C80 DSP single
`chip multiple instruction/multiple data (MIMD) digital signal processor
`(DSP). Ex. 1007, 4. The chip includes a master processor, four parallel
`processors, a transfer controller, and video controller. Id.
`
`20
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`3. Discussion
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations, including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Against this backdrop, we analyze this asserted ground based on
`obviousness, with the principles identified above in mind.
`In its Petition, Petitioner urges that the single-chip graphics processor
`disclosed by The TI Data Sheet is a “a single chip, MIMD parallel processor
`capable of performing over two billion operations per second.” Pet. 30.
`Petitioner contends the single-chip graphics processor includes a master
`processor, and four parallel processors (“PPs”) that perform core graphics
`functions, “can execute in parallel: a multiply, ALU operation, and two
`memory accesses within a single instruction,” and perform “pixel-intensive
`processing.” Id. at 30–31 (citing Ex. 1007, 2, 34).
`Petitioner depends on the TI Article for the disclosure in Figure 1 of a
`graphics-processing method involving a rendering pipeline that includes
`“transformation” and “rasterization” operations. Id. at 31–32. The TI
`Article describes two ways of implementing parallel graphics processing
`
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`using the master processor and four parallel processors, according to
`Petitioner. Id. at 32 (citing Ex. 1006, 10). These include: 1) using each of
`the four parallel processors to run the same type of code; and 2) each parallel
`processor runs different code to execute different stages of the graphics
`pipeline. Id. at 32–34 (citing Ex. 1006, 16–18, Figures 6, 7). Petitioner
`points out that the “TI Article expressly notes that ‘hybrid combinations of
`both approaches are possible’ as well.” Id. at 34 (citing Ex. 1006, 18).
`Based on these teachings, Petitioner argues that one of ordinary skill would
`have been motivated to combine the TI References because both describe the
`same digital signal processor. Id. at 34–35 (citing Ex. 1001 ¶¶ 91–97; Ex.
`1006, 7).
`We address initially Patent Owner’s arguments challenging the
`sufficiency of the TI Article in describing the “lighting module” limitation of
`claim 1, as well as the “lighting the vertex data” limitation of claim 20.
`Prelim. Resp. 31–32. Petitioner, relying on the testimony of its Declarant,
`Dr. Manocha, argues that “the TI Article describes the use of ADSPs to
`implement a standard rendering pipeline. Included in this pipeline are
`lighting operations performed by the ADSPs.” Pet. 41 (citing Ex.
`1001 ¶ 104). As support for this position, both Petitioner and Dr. Manocha
`contend that “[a] paper from several TI authors explains that the TMS320
`family of chips implements both Gouraud and Phong shading. Ex. 1015 at
`56. Gouraud shading uses per-vertex lighting operations that are
`subsequently linearly interpolated across the polygon.” Pet. 42 (citing Ex.
`1016 at 736-768; Ex. 1001 ¶ 101).
`
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`As Patent Owner correctly points out, Petitioner depends on a
`combination of the TI Article and TI Data Sheet to support this proposed
`ground of unpatentability. Prelim. Resp. 33. Thus, Patent Owner argues
`persuasively that Petitioner’s and Dr. Manocha’s reliance on Foley and
`Guttag is misplaced because Petitioner fails to identify either Foley or
`Guttag as part of the combination of references. Id.
`Patent Owner also argues that Dr. Manocha mischaracterizes the
`statement in Guttag “that only teaches that ‘graphics applications require
`primitives such as… Gouraud- and Phong-shaded surfaces.’” Id. at 34
`(citing Ex. 1015, 56). According to Patent Owner, t
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