Paper No. 47
`
`Trials@uspto.gov
`Date Entered: October 27, 2016
`571-272-7822
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`AMERICAN MEGATRENDS, INC.,
`MICRO-STAR INTERNATIONAL CO., LTD,
`MSI COMPUTER CORP.,
`GIGA-BYTE TECHNOLOGY CO., LTD., and
`G.B.T., INC.,
`Petitioners,
`
`v.
`
`KINGLITE HOLDINGS, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01081
`Patent 5,987,604
` ____________
`
`
`
`Before GLENN J. PERRY, TREVOR M. JEFFERSON, and
`BRIAN J. McNAMARA, Administrative Patent Judges.
`
`
`
`McNAMARA, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and
` 37C.F.R. § 42.73
`
`
`

`
`IPR2015-01081
`Patent 5,987,604
`
`
`BACKGROUND
`On October, 29, 2015, we instituted an inter partes review of claims
`1–30 of U. S. Patent No. 5,987,604 ("the ’604 Patent"). Paper 18 (“Dec. to
`Inst.”). Patent Owner filed a Patent Owner Response (Paper 30, “PO
`Resp.”), Petitioner filed a Petitioner Reply (Paper 39, “Pet. Reply”). Patent
`Owner filed a Motion to Exclude (Paper 23, “Mot. To Exclude”), Petitioner
`filed an Opposition (Paper 43, “Opp. To Mot. To Exclude”), and Patent
`Owner filed a Reply (Paper 44 “Reply to Opp. to Mot. to Exclude”). A
`transcript of an oral hearing held on June 29, 2016 (Paper 46, “Hr’g Tr.”)
`has been entered into the record.
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. §318(a). We base our decision on
`the preponderance of the evidence. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d).
`Having reviewed the arguments of the parties and the supporting
`evidence, we conclude that Petitioner has demonstrated by a preponderance
`of the evidence that the challenged claims are unpatentable.
`
`THE ’604 PATENT
`The ’604 Patent discloses an x86 based system in which a system
`management interrupt (SMI) invokes an operating mode known as system
`management mode (SMM). Ex. 1001, col. 3, ll. 10–20. In SMM, system
`firmware is used to perform power management or control other system
`functions, e.g., controlling hardware specific features, in a manner that is
`transparent to the operating system and applications software. Id.
`The ’604 Patent discloses creating a virtual monitor that runs under
`SMM with memory paging to execute SMI code in virtual mode, thereby
`allowing SMM code written to run below the 1 MB boundary to execute
`
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`above the 1 MB boundary by mapping the entire SMI handler above the 1
`MB boundary and executing the code as a page enabled, protected mode,
`virtual task with SMM. Id. at col. 2, ll. 27–35. When an SMI is generated,
`the central processing unit (CPU) asserts an SMI activate (SMIACT) control
`signal to access system management random access memory (SMRAM) 20,
`which is a dedicated memory space not accessible to the operating system or
`application software. Id. at col. 3, ll. 21–27, col. 6, ll. 6–10. After storing
`the current operating location for return purposes in SMRAM 20, CPU 14
`jumps to a location in SMRAM 20 to execute the SMI handler code that
`performs the system management activity. Id. at col. 3, ll. 27–31. Upon
`completion of the system management activity, control is returned to the
`previously interrupted operating system. Id. at col 3, ll. 31–37.
`The ’604 Patent notes that conventional SMIs execute slowly because
`they operate below the 1 MB boundary in an uncached memory area, in
`order to avoid cache conflict with overlapping memory. Id. at col. 1, ll. 26–
`31. Such conventional SMMs operate in real mode with 4GB memory
`segments and 1 MB addressable program memory and are relatively slow.
`According to the ’604 Patent, a conventional alternative approach transfers
`SMI code and data from a region above the 1 MB boundary to a cacheable
`region below the 1 MB boundary, allowing standard execution of SMI code
`in real mode, but requiring transfer of the SMI code back to a cacheable area
`above the 1 MB area after completing the SMI. Id. at col. 1, ll. 37–45.
`In accordance with the invention in the ’604 Patent, the data and code
`in SMRAM 20 located in the physical memory is mapped to location 22,
`which is above the 1 MB region in system space 50. Id. at col. 6, ll. 10–14,
`col. 7, ll. 27–30. CPU 14 then jumps to a location in SMRAM 20 that is
`
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`above the 1 MB region in the system address space 50 to execute the SMI
`handler code. Id. at col. 6, l. 15–19, col. 7, ll. 32–37. The SMI handler then
`jumps to location 24, which must be within 64 K of location 22, where the
`CPU mode change takes place, configuring CPU 14 to operate in protected
`mode. Id. at col 6, ll. 20–28.
`The SMI handler then creates page tables and is configured to create a
`task state segment (TSS) and input/output (I/O) bit map, unless they were
`created during power on self-test (POST). Id. at col. 6, ll. 31– 39. The SMI
`handler then invokes the paging feature of CPU 14 and switches to virtual
`mode. Id. at col. 6, ll. 53–54.
`In virtual mode, CPU 14 determines logical operations the same way
`as in real mode and the physical address is determined using the page tables.
`Id. at col. 6, l. 66–col. 7, l. 1. The SMI handler begins the task required to
`perform system management activities. Id. at col. 7, ll. 1–3. During
`execution of system management activities, the software occasionally
`configures the processor to operate in protected mode to facilitate execution
`of specific tasks, such as cache flushes and accessing the floating point unit
`of the CPU. Id. at col. 7, ll. 3–6. Upon completion of the special task, the
`SMI handler configures the CPU to operate in virtual mode to resume
`system management activity. Id. at col. 7, ll. 12–14.
`Upon completion of system management activity, the SMI handler
`configures the CPU to exit the virtual mode, causing the CPU to operate in
`the protected mode. Id. at col. 7, ll. 14–19. Paging is then disabled and the
`SMI handler executes a resume instruction to return control to the previously
`interrupted operating system or application execution. Id. at col 7, ll. 18–22.
`
`
`
`
`4
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`

`
`ILLUSTRATIVE CLAIM
`Claims 1, 11 and 21 are independent. Claim 1 is drawn to an
`apparatus, claim 11 is drawn to a method, and claim 21 is drawn to a
`computer-executable process. Claim 1 is representative:
`1. An apparatus for executing instructions in a system
`management mode in a processor-based system, comprising:
`a memory for storing instruction sequences by which the
`processor-based system is processed;
`a processor having a system address space, the processor for
`executing the stored instruction sequences; and
`wherein the stored instruction sequences cause the processor to:
`(a) configure the processor to operate in a protected mode
`while in system management mode, the processor operating
`at an address greater than one megabyte; (b) invoke a paging
`feature of the processor; (c) configure the processor to operate
`in a virtual mode; and (d) process the instruction sequences
`stored, wherein the process steps occur upon the receipt of an
`instruction to process a system management request.
`
`Independent claims 11 and 21 recite as limitations parts (a)–(d) of the
`wherein clause of claim 1.
`ART CITED IN PETITIONER’S CHALLENGES
`Petitioner cited the following references in its challenges to patentability:
`Reference
`Designation
`Exhibit No.
`U.S. Patent No. 5,644,755,
`iss. July 1, 1997.
`U.S. Patent No. 6,093,213,
`iss. July 25, 2000.
`
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`5
`
`Wooten
`
`Favor
`
`Ex. 1002
`
`Ex. 1003
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`
`Advanced Micro Devices,
`Preliminary Enhanced
`AM686® Microprocessor
`Family Publication #19225
`Rev. B Amendment/0 (1995).
`3 Intel, Pentium® Processor
`Family Developer’s Manual
`(1995).
`Robert W. Collins, The
`Caveats of Pentium System
`management Mode (May 1,
`1997),
`http://www.drdobbs.com/the-
`caveats-of-petitum-system-
`management/184410199
`(last visited 8/11/2014).
`IBM, IBM 6x86
`Microprocessor Sixth
`Generation Superscalar
`Superpipelined x86-
`Compatible CPU (1996).
`3 Intel, Intel Architecture
`Software Developer’s
`Manual (1997).
`
`
`
`Am686 Manual
`
`Ex. 1004
`
`Pentium Manual
`
`Ex. 1005
`
`Collins
`
`Ex. 1006
`
`IBM 6x86
`
`Ex. 1012
`
`ASDM
`
`Ex. 1013
`
`GROUNDS OF INSTITUTION
`In our Decisions to Institute, we instituted trial on the following
`grounds:
`Claims 1–4, 11–14, and 21–24 as obvious under 35 U.S.C. § 103 over
`the combination of Collins and the Pentium Manual;
`Claims 1–4, 11–14, and 21–24 as obvious under 35 U.S.C. § 103 over
`the combination of Collins, the Pentium manual and IBM 6x86; and
`Claims 5–10, 15–20, and 25–30 as obvious under 35 U.S.C. § 103
`over the combination of Collins, the Pentium Manual and ASDM.
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`CLAIM CONSTRUCTION
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their “broadest reasonable construction in light of
`the specification of the patent” in which they appear. 37 C.F.R. § 42.100(b);
`see also Cuozzo Speed Techs., LLC, v. Lee, 136 S. Ct. 2131, 2141–46
`(2016). The terms also are generally given their ordinary and customary
`meaning as would be understood by one of ordinary skill in the art in the
`context of the disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`(Fed. Cir. 2007). Our Decision to Institute applies the following claim
`constructions, which the parties do not dispute, and we apply these same
`constructions in this Decision.
`Protected Mode: ordinary meaning as discussed in the Dictionary of
`Computer Terms1 cited by Patent Owner; i.e., “[A] mode of processor
`operation in which an 80286 or later generation x86 microprocessor can
`access the largest possible amount of memory.” Dec. to Inst. 9–10.
`System Management Mode (SMM): an operating mode that is entered
`in response to a dedicated SMI and that uses a dedicated memory space to
`implement power management and enhanced system functions in firmware
`in a manner that is transparent to the operating system and applications
`software. Id. at 10–11.
`
`
`1 Douglas Downing & Michael Covington, BARRON’S BUSINESS GUIDES,
`DICTIONARY OF COMPUTER TERMS (3d. ed. 1992) (“Dictionary”).
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`
`Virtual Mode: a task running in protected mode in which the
`processor emulates an 8086 processor, such that the execution environment
`is the same as that of a real-address mode.2 Id. at 11–12.
`Paging: [A] memory management process for mapping logical
`addresses to physical addresses. Id. at 12–13.
`
`PATENT OWNER’S MOTION TO EXCLUDE
`Collins (Ex. 1006)
`Collins is cited in each of the grounds on which we instituted trial.
`Therefore, we first address Patent Owner’s Motion to Exclude Collins.
`Petitioner identifies Collins as an article published in Dr. Dobb’s
`Journal on May 1, 1997. Pet. 22, 26. The version of Collins filed with the
`Petition as Ex. 1006 is a reproduction of Collins downloaded on August 14,
`2014 from a website identified as http://www/drdobbs.com/the-caveats-of-
`pentium-system-management/184410199 (“dr.dobbs URL”). Ex. 1006, 1.
`The reproduction states “The Caveats of Pentium System Management
`Mode By Robert R. Collins, May 1, 1997.” Id. at 1. The article also
`includes the following copyright notice: “Copyright © 1997, Dr. Dobbs
`Journal.” Id. at 6.
`Patent Owner challenges the admissibility of Ex. 1006, arguing that
`the version of Collins proffered by Petitioner is not an accurate or genuine
`
`
`2 According to ASDM in the real-address mode execution environment, the
`processor supports a 1 M-byte physical address space divided into segments,
`each of which can be up to 64 Kbytes in length, and the base of the segment
`is specified with a 16 bit segment selector, which is zero extended to form a
`20 bit offset from address 0 in the address space, and in which a physical
`address is formed by adding the offset to the 20 bit segment base. Ex. 1013
`§ 15.1, pp. 435–436.
`
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`duplicate of that reference as originally published. Mot. To Exclude 2.
`According to Patent Owner, accessing the Wayback Machine archives of
`Internet webpages showed that the dr.dobbs URL was under construction as
`of November 17, 2000 and that the version proffered by Petitioner could not
`have existed in 1997. Id. (citing, Ex. 2004, Declaration of Christopher
`Frerking, (“Frerking Decl.”) ¶3).
`Patent Owner conflates the existence of the dr.dobbs URL with the
`authenticity of the Collins article. The existence of the URL in 1997 is not
`the issue before us. Petitioner does not claim to have downloaded Collins
`from a 1997 URL. Exhibit 1006 clearly shows that the copy of Collins was
`downloaded on August 11, 2014 from the dr.dobbs URL. The issue before
`us is whether the copy of the article proffered in Ex. 1006 is a duplicate, i.e.,
`a counterpart produced by a mechanical, photographic, chemical, electronic,
`or other equivalent process or technique that accurately reproduces the
`original. Fed. R. Evid. 1001(c) (emphasis added). As Patent Owner notes
`“[a] duplicate is admissible to the same extent as the original unless a
`genuine question is raised about the original’s authenticity or the
`circumstances make it unfair to admit the duplicate.” Mot. To Exclude. 2–3
`(citing Fed. Rule of Evid. 1003).
`Following our Decision to Institute, Petitioner responded to Patent
`Owner’s evidentiary objection to Collins by serving on Patent Owner
`supplemental evidence, i.e., the Declaration of Robert Collins (“Collins
`Decl.”), a copy of Collins as it appeared in the May 1997 Dr. Dobbs Journal,
`and a copy of the cover page of the May 1997 Dr. Dobbs Journal publication
`obtained from the Georgia Tech Library. Mot. To Exclude 3. Patent Owner
`
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`declined to withdraw its objection and, as part of this Motion to Exclude,
`filed Petitioner’s supplemental evidence as Ex. 2007.
`Noting that the cover page indicates the Georgia Tech Library
`received the May 1997 Dr. Dobbs Journal on April 7, 1997, Patent Owner
`suggests that Petitioner seeks to move the date of the reference back to April
`1997. Mot to Exclude 4. Indeed, in its opposition to the Patent Owner
`Response, Petitioner argues that Collins was circulated to libraries as early
`as April 7, 1997 and cites the testimony of Robert Collins that his article was
`in circulation about a month before the May 1, 1997 publication date. Pet.
`Reply 20 (citing Collins Decl., Ex. 2007 ¶ 1; Ex. A). Patent Owner contends
`that Petitioner provided the hard copy of Collins and the Collins Declaration
`as supplemental evidence to overcome an objection, but because Petitioner
`did not file the supplemental evidence in this proceeding, Petitioner may not
`rely upon it for the substantive purpose of arguing an earlier date of
`publication. Mot. To Exclude 4.
`We need not reach the issue of whether Petitioner can rely on the
`Exhibit 2007 filed by Patent Owner because Petitioner has not provided any
`evidence that Collins was accessible to the public prior to its publication
`date of May 1, 1997. For example, Petitioner has not demonstrated how
`Collins would have been catalogued in any library or made accessible to the
`public. Thus, the only date we ascribe to Collins is May 1, 1997.
`Patent Owner also notes that the cover page in 1997 refers to a URL
`(www.ddj.com) that is different URL associated with Exhibit 1006. Mot. To
`Exclude 3–4. However, as discussed above, the existence of any particular
`web page is not the issue before us.
`
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`
`Patent Owner acknowledges that the publication in which Collins
`originally appeared, Dr. Dobb’s Journal, was, in May 1997, published in
`hard copy form. Mot. To Exclude 2. However, Patent Owner argues that
`the version of Collins provided by Petitioner as Ex. 1006 is not a duplicate
`of the article appearing originally in hard copy form. Mot. To Exclude. 2.
`Although the web site on which Collins appears in Ex. 1006 is not a
`copy of the article in its original form, we direct our inquiry to the contents
`of the article. “When the only concern is with getting the words or other
`contents before the court with accuracy and precision, a counterpart serves
`equally well as the original, if the counterpart is the product of a method
`which insures accuracy and genuineness.” Fed. R. Evid. 1003, Advisory
`Committee Notes. Patent Owner acknowledges that there is no difference
`between the contents of Collins in Ex. 1006 and the contents of the hard
`copy of Collins, as published in the May 1997 Dr. Dobbs Journal. Hr’gTr.
`53. Therefore, we conclude that Ex. 1006 is an admissible duplicate of the
`original Collins article and we deny Patent Owner’s Motion to Exclude Ex.
`1006.
`
`Polyudov Declaration (Ex. 1014)
`Patent Owner has also objected to and moved to exclude the
`declaration testimony of Petitioner’s expert Feliks Polyudov, (Ex. 1014
`(“Polyudov Decl.”)) on the ground that he has been employed by Petitioner
`AMI for 15 years and is therefore biased. Mot. To Exclude 6–7. Mr.
`Polyudov acknowledges his past and current employment by AMI and states
`that he is not being compensated specially for his work in this proceeding
`and that his compensation is not dependent upon the results of this
`proceeding. Polyudov Decl. ¶ 5. Patent Owner does not challenge Mr.
`
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`Ployudov’s qualifications or offer any evidence that Mr. Polyudov is biased,
`other than his employment at AMI. Nor does Patent Owner present any
`evidentiary basis for excluding Mr. Polyudov’s testimony.
`Although Mr. Polyudov’s employment background may affect the
`weight we assign his testimony, his status as an employee of AMI alone
`does not disqualify him. In consideration of the above, Patent Owner’s
`Motion to Exclude Exhibit 1014 is denied.
`ANTEDATING OF COLLINS
`We begin with Patent Owner’s contention that Collins, published in
`May 1997, is not prior art because the inventor of the ’604 Patent, David
`Edrich, asserts prior invention, declaring that “the invention had been
`disclosed to Intel engineers around April 1, 1997, meaning that the invention
`had been conceived of by no later than that date.” PO Resp. 14–15; Ex.
`2002, Declaration of David Edrich (“Edrich Decl.”) ¶ 9. As evidence of this
`earlier conception, Patent Owner relies on a Phoenix Technologies Invention
`Disclosure Form that states:
`The invention idea has been disclosed to Intel Engineers,
`informally, as a possible solution since around April 1, 1997. On
`July 1, 1997 Phoenix Engineers will be doing pre-alpha testing
`of the 440BX chipset. Part of this testing is to include SMI
`execution above 1 Megabyte so this invention is scheduled to be
`tested then but that is not the primary concern of the July effort.
`
`Ex. 2003 ¶ 8. The invention disclosure, which identifies Mr. Edrich as the
`sole inventor, states that it was prepared on June 18, 1997, but does not
`indicate who prepared it, and is not signed.
`Petitioner contends that Mr. Edrich’s testimony is entitled to no
`weight because his assertions about discussions with Intel engineers are
`hearsay, he is a paid consultant to Patent Owner, the disclosure is unsigned
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`and uncorroborated, and because among several alleged inventive concepts
`asserted in the disclosure, it is not possible to determine if the invention
`referenced in Mr. Edrich’s declaration is the same invention as that claimed
`in the ’604 Patent. Pet. Reply 15–17.
`“Conception must be proved by corroborating evidence which shows
`that the inventor disclosed to others his ‘completed thought expressed in
`such clear terms as to enable those skilled in the art’ to make the invention.”
`Coleman v. Dines, 754 F.2d 353, 359 (Fed. Cir. 1985). The requirement of
`“independent” corroboration requires evidence other than the inventor’s
`testimony. In re NTP, Inc. 654 F.3d 1279, 1291 (Fed. Cir. 2011). Patent
`Owner offers no corroborating evidence to support Mr. Edrich’s testimony.
`There is no contemporaneous evidence supporting the statements in Mr.
`Edrich’s declaration and there is no testimony corroborating Mr. Edrich’s
`declaration. For example, the Intel engineers are not identified and there is
`no written record of what Mr. Edrich disclosed to these Intel engineers.
`Indeed, prior to the invention form dated June 18, 1997, there is no written
`record of what Mr. Edrich alleges he invented. Although the invention
`disclosure states that testing was to be conducted, Patent Owner provides no
`evidence that such testing was conducted or that any testing proved the
`concept, as purportedly conceived in April 1997.
`In view of the absence of any corroboration of prior invention by Mr.
`Edrich, we conclude Collins is prior art.
`
`
`
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`ANALYSIS OF PRIOR ART CHALLENGES
`Introduction
`We resolve the question of obviousness on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art; (3)
`the level of skill in the art; and (4) objective evidence of nonobviousness,
`i.e., secondary considerations. See Graham v. John Deere Co., 383 U.S. 1,
`17–18 (1966). The test for obviousness is whether the combination of
`references, taken as a whole, would have suggested the patentees’ invention
`to a person having ordinary skill in the art. In re Merck & Co., Inc., 800
`F.2d 1091, 1097 (Fed. Cir. 1986).
`The Supreme Court has made clear that we apply “an expansive and
`flexible approach” to the question of obviousness. KSR Int’l Co. v. Teleflex
`Inc., 550 U.S. 398, 415 (2007). Whether a patent claiming the combination
`of prior art elements would have been obvious is determined by whether the
`improvement is more than the predictable use of prior art elements according
`to their established functions. Id. at 417. To reach this conclusion, however,
`requires more than a mere showing that the prior art includes separate
`references covering each separate limitation in a claim under examination.
`Unigene Labs., Inc. v. Apotex, Inc., 655 F.3d 1352, 1360 (Fed. Cir. 2011).
`Rather, obviousness requires the additional showing that a person of
`ordinary skill at the time of the invention would have selected and combined
`those prior art elements in the normal course of research and development to
`yield the claimed invention. Id. As the Supreme Court recognized, in many
`cases a person of ordinary skill “will be able to fit the teachings of multiple
`patents together like pieces of a puzzle,” recognizing that a person of
`
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`ordinary skill “is also a person of ordinary creativity, not an automaton.”
`KSR at 420–21. Against this general background, we consider the
`references, other evidence, and arguments of the parties.
`
`Claims 1–4, 11–14, and 21–24 As Obvious Over Collins and Pentium
`Manual
`Petitioner contends that Collins discloses a protected mode and a
`virtual mode while in a separate x86 state known as SMM, if the device is
`programmed to perform SMM (which Collin states, it most likely is not).
`Pet. 26 (citing Ex. 1006, 4). The paragraph from Collins cited by Petitioner
`is entitled “Using Protected Mode Within SMM” and discloses the
`capability of operating in protected mode, if the SMM was programmed to
`do it. Ex. 1006, 4. Petitioner notes that the processor can execute directly in
`real address mode 8086 software in a multitasking environment, i.e., a
`virtual-8086 (“v86”) mode. Pet. 26. Petitioner also cites the disclosure in
`Collins concerning using SMM to create a CPL-0 v86 task, which Petitioner
`argues shows enabling virtual mode while employing SMM in protected
`mode. Id.
`Petitioner cites the Pentium Manual as disclosing a processor
`architecture including paging with a real mode, a protected mode, and an
`SMM mode, id. at 26–27 (citing Ex. 1005, 40), and memory management
`features, such as paging, id. at 27 (citing Polyudov Decl. ¶ 141). Petitioner
`further argues that a person of ordinary skill would have recognized that
`protected mode permits instructions located between 1 MB and 4 GB of
`memory to accessed by the processor and that protected mode features the
`ability to execute directly real-address mode 8086 software in a protected,
`multi-taking environment. Id.
`
`
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`In its claim charts Petitioner cites the Pentium Manual as disclosing
`the elements of claim 1, including, SMM (Pet. 28), SMRAM (id), relocating
`RAM to an address above 1 MB (id. at 29), invoking a paging feature (id.),
`configuring the processor to operate in a virtual mode (id. at 29–30),
`processing the instructions stored (id.) wherein the processing steps occur
`upon receipt of a system management request (id.). Petitioner cites Collins
`as disclosing operating in a protected mode while in SMM (id. at 29),
`invoking a paging feature of the processor (id.) and configuring the
`processor to operate in a virtual mode (id. at 30). Petitioner has also
`provided claim charts that support its challenges to claims 2–4, 11–14, and
`21–24 on this ground.
`According to Petitioner, a person of ordinary skill in in the art would
`have been motivated to combine Collins and the Pentium Manual because
`they describe features of the Pentium processor having SMM, protected and
`virtual modes. Id. at 27.
`Patent Owner contends that the ’604 Patent overcomes problems in
`the prior art by teaching that “SMRAM should be mapped to occupy an area
`of memory having unique addressable locations above 1 Mbyte.” PO Resp.
`4 (citing Ex 2010, Expert Report of Dr. John Levy from C.D. Cal. Case No.
`CV14-03009-JVS(PJWx) (“Levy Report.”) ¶ 7).3 Patent Owner states that
`
`
`3 Paragraph 7 of the Levy Declaration does not address this issue; it
`identifies a course Dr. Levy taught at San Francisco State University. The
`Levy Report submitted as Exhibit 2010 in this proceeding appears to be
`taken from co-pending district court litigation. The Levy Report appears to
`address the ’604 Patent at Paragraphs 31–49. It is not clear what paragraph
`of the Levy Report (or any other Exhibit) supports this statement in the
`Patent Owner Response. We also note that in paragraph 40, apparently
`referring to issues in the district court, the Levy Report states that the only
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`“[t]he ’604 Patent discloses creating a virtual monitor that runs under SMM
`with memory paging to execute SMI code in virtual mode, thereby allowing
`SMM code written to run below the 1 Megabyte boundary to execute above
`the 1 Megabyte boundary.” Hr’g Tr. 23:15–19; Levy Report ¶ 38 (citing Ex.
`1001, col. 2, ll. 27–32). According to Patent Owner, the programmatic
`addressing solution described in the ’604 Patent is different from override
`addressing solutions supported by all of the cited prior art, because the ’604
`Patent offers the only addressing solution for operating SMM with
`instructions above 1 Megabyte. PO Resp. 5.
`Patent Owner argues that the Pentium Manual teaches an involved,
`instruction intensive procedure for using SMM mode addressing with special
`overrides per instruction, i.e., override prefixes, to operate with SMRAM
`code above 1 Mbyte so that SMM addressing can reach up to 4 Gbytes of
`address space. PO Resp. 8–9. According to Patent Owner, “the ’604 Patent
`claims do not describe using SMM mode addressing to operate at an address
`above 1 Mbyte, as disclosed in the Pentium Manual. Ex. 2010 ¶15. 4
`
`
`claim at issue is claim 11. This proceeding concerns claims 1–30. Thus, it
`is unclear if Patent Owner meant to reference a different document.
`However, we will not scour the record to determine Patent Owner’s
`intentions.
`4 The Levy Report in Ex. 2010 does not address this issue at paragraph 15.
`Paragraph 15 states that Dr. Levy applies the plain and ordinary meaning to
`terms not construed by the court. It is unclear if Patent Owner’s reference to
`the Pentium Manual as Ex. 2010 is intended to refer to Ex. 1005, as
`designated at page 6 in our Decision to Institute or Ex. 1013, which is
`another Pentium manual. In Exhibit 1005, Chapter 15, which is 9 pages
`long and has a number of subsections, concerns Input-Output and § 15.3 is
`titled “Protected Mode I/O.” In Exhibit 1013, Chapter 15, which is 28 pages
`long and includes numerous subsections, is titled “8086 Emulation” and
`includes a discussion of real address mode and virtual address mode.
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`IPR2015-01081
`Patent 5,987,604
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`Instead, such claims teach a programmatic approach that minimizes
`instructions, instead of relying on what is disclosed in Collins and the
`Pentium Manual.” PO Resp. 9.
`Petitioner argues that recognizing SMM involved executing 16 bit
`code in a 32 bit code execution environment, the ’604 Patent merely utilizes
`virtual 8086 mode for its intended purpose (i.e., to execute 16 bit code in a
`protected mode environment that supports multitasking), instead of utilizing
`real mode to run SMM-related code. Pet. Reply 1. According to Petitioner,
`it is undisputed that a programmatic solution to multitasking (protected
`mode, paging, and virtual mode) is taught in the Intel Pentium Manual. Pet.
`Reply 2–3. Petitioner cites the Pentium Manual as disclosing paging in
`protected mode, transitioning to virtual 8086 mode in protected mode and
`the usefulness of paging for virtual 8086 multitasking in protected mode. Id.
`Petitioner also notes that the salient characteristics of SMM, as embodied in
`the challenged claims 1, 4, 11, 14, 21, and 24 are taught explicitly by the
`Pentium Manual. Id. (citing Ex. 1005 at 41, 493–502). Petitioner further
`argues that functionality inherent in protected mode coexisting with
`operation in SMM was known in the prior art relating to the x86 processor.
`Id. at 3 (citing Ex. 1006, 4; Ex. 1012, § 2.9.5).
`Patent Owner identifies prior art cache coherency problems resulting
`from overlaid SRAM implementations in which the processor cannot
`differentiate between system memory and its internal cache, so that cache
`may contain cached instructions at normal addresses that are at the same
`address of the SMM instructions. PO Resp. 2. Patent Owner reviews
`
`
`However, as noted above, we will not scour the record to determine Patent
`Owner’s intentions
`
`
`
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`IPR2015-01081
`Patent 5,987,604
`
`problems with prior art solutions (turning off the cache and treating
`SMRAM as non-cacheable negates the value of having processor cache;
`flushing the cache to make it useable may not be possible with all legacy
`chipsets; relocating SMRAM space in a non-overlaid environment
`introduces jump restrictions). Id. at 3–4. According to Patent Owner, the
`’604 Patent overcomes these problems by mapping SMRAM to occupy an
`area of memory having unique addressable locations above 1 Mbyte. Id. at
`4.
`
`Claim 1 recites “the processor operating at an address above 1
`Mbyte.” The specification of the ’604 Patent discloses that SMM is invoked
`via assertion of the SMI signal to the CPU, which asserts the SMIACT
`control signal, which accesses SMRAM 20. Ex. 1006, col. 6, ll. 6–10. The
`specification further states: “In accordance with the principles of the present
`invention, the data and code of SMRAM 20 located in physical memory is
`first mapped into a location that is above 1 Megabyte in the system address
`space, as shown in Fig. 5.” Id. at col. 6, ll. 10–14. However, as Petitioner
`notes, independent claims 1, 11, and 21 of the ’604 Patent do not mention
`SMRAM and do not recite relocating SMRAM or mapping SMRAM above
`1 Mbyte. Pet. Reply. 7–8. In general, “even if all of the embodiments
`discussed in the patent included a specific limitation, it would not be proper
`to import from the patent’s written description limitations that are not found
`in the claims themselves.” Cadence Pharm. Inc. v. Exela PharmSci Inc.,
`780 F.3d 1364