Many ways to shrink:
`The right moves to 10 nanometer
`and beyond
`
`Martin van den Brink
`President & Chief Technology Officer
`
`
`24 November 2014
`
`Energetiq Ex. 2038, page 1 - IPR2015-01362
`
`
`The right moves to 10 nanometer
`and beyond
`
`Martin van den Brink
`President & Chief Technology Officer
`
`
`24 November 2014
`
`Energetiq Ex. 2038, page 1 - IPR2015-01362
`
`
`
`Public
`
`Slide 3
`November 2014
`
`Content
`
`• Industry Challenges
`• The desire to shrink
`
`• The device challenges
`
`• The scaling challenges
`
`• ASML Solutions
`
`• Our holistic approach to extend immersion
`
`• The process simplification by using EUV
`
`Energetiq Ex. 2038, page 2 - IPR2015-01362
`
`
`
`Moore’s Law: the rice-and-chessboard challenge
`The benefits of shrink are irresistible
`
`Public
`
`Slide 4
`November 2014
`
`Energetiq Ex. 2038, page 3 - IPR2015-01362
`
`
`
`Driving the semiconductor industry: Moore’s Law;
`“…home computers…and personal portable communication…”
`
`Public
`
`Slide 5
`November 2014
`
`Gordon Moore’s prediction, 1965
`
`Reality, ~ 50 years later, 2014
`
`Source: Gordon E. Moore,
`“Cramming More Components onto Electronic Circuits”,
`Electronics, pp114-117, April 19, 1965
`
`Energetiq Ex. 2038, page 4 - IPR2015-01362
`
`
`
`Some question if Moore’s Law can continue
`
`Public
`
`Slide 6
`November 2014
`
`Energetiq Ex. 2038, page 5 - IPR2015-01362
`
`
`
`Mobile applications continue to be on an yearly cadence
`device and litho innovations driving area, power and performance
`
`Public
`
`Slide 7
`November 2014
`
`28PolySiON
`
`28HKMG
`
`Transistor
`
`Litho
`
`20HKMG
`
`14/16FF
`
`Transistor
`
`Litho
`
`10FF
`
`Area
`
`Power
`
`Performance
`
`ʻ12
`
`ʻ13
`
`ʻ14
`
`ʻ15
`
`ʻ16
`
`Source: Esin Terzioglu, Qualcomm, EUV symposium, Oct 2014
`
`Energetiq Ex. 2038, page 6 - IPR2015-01362
`
`
`
`Mobile chips integrating functionality faster than shrink
`Apple: first high volume 20nm process in the iPhone 6(+)
`
`Apple A6X
`New Dual Core and 4-GPU
`needed for Retina Display iPad 4
`123 mm2 – 32 nm
`
`Public
`
`Slide 8
`November 2014
`
`Apple A8 iPhone 6/6+
`2-core 64bit & 4-GPU’s
`2 Billion transistors
`90mm2 – 20 nm
`
`Apple A6
`New Dual Core and 3-GPU
`needed for Retina Display
`97 mm2 – 32 nm
`
`Apple A4
`1-Core and 1-GPU
`53 mm2 – 45 nm
`
`Apple A5X – iPad 3
`2-Core and 4-GPU
`needed for Retina Display
`169 mm2 – 45 nm
`
`Apple A5
`2-Core and 2-GPU
`needed for iPad Display
`122 mm2 – 45 nm
`
`Apple A5S – AppleTV,
`iPad2, iPAd Mini, iPod
`Touch
`70 mm2 – 32nm
`
`Apple A7 - iPhone 5S &
`iPad Air
`Two 64bit cores
`1 Billion transistors
`102 mm2 – 28 nm Apple
`
`Apple A5_3 - AppleTV
`Single Core, 2-GPU 38 mm2 – 32 nm
`
`Source: Apple
`
`45nm
`
`32nm
`
`28nm
`
`20nm
`
`Energetiq Ex. 2038, page 7 - IPR2015-01362
`
`
`
`And area and cost per function reduction accelerates
`
`Public
`
`Slide 9
`November 2014
`
`Source: Bill Holt, Intel, “Intel Investor meeting”, Nov 2014, *forecast
`
`Energetiq Ex. 2038, page 8 - IPR2015-01362
`
`
`
`And is a competitive item between chip makers
`
`Area Scaling
`
`Public
`
`Slide 10
`November 2014
`
`Intel
`
`Intel’s view on
`TSMC’s shrink¹
`
`TSMC reaction
`on Intel²
`
`~45%
`
`~15%
`
`*35%
`
`Log Scale
`
`32/28 nm
`
`22/20 nm
`
`14 nm*/16FF
`
`10 nm*
`
`Sourcews: ¹Bill Holt, Intel investor conference, Nov 2013
`
`²Mark Liu, TSMC analyst call, Jan 2014
`
`Energetiq Ex. 2038, page 9 - IPR2015-01362
`
`
`
`The challenge of Moore’s law chessboard in numbers
`What about our customers challenges?
`
`
`Public
`
`Slide 11
`November 2014
`
`Energetiq Ex. 2038, page 10 - IPR2015-01362
`
`
`
`Shrink scenarios for logic devices
`
`Bulk CMOS at 100 nm gate length: open
`
`Bulk CMOS at 100 nm gate length: closed
`
`Public
`
`Slide 12
`November 2014
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon on
`insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 11 - IPR2015-01362
`
`
`
`Shrink scenarios for logic devices
`
`Bulk CMOS 20 nm: open
`
`Bulk CMOS 20 nm: closed
`
`Public
`
`Slide 13
`November 2014
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon
`on insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 12 - IPR2015-01362
`
`
`
`Shrink scenarios for logic devices
`
`Silicon on insolator
`
`Public
`
`Slide 14
`November 2014
`
`Solution 1:
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon
`on insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 13 - IPR2015-01362
`
`
`
`Shrink scenarios for logic devices
`
`Bulk FinFet
`
`Public
`
`Slide 15
`November 2014
`
`Solution 2:
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon
`on insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 14 - IPR2015-01362
`
`
`
`Shrink scenarios for logic devices
`
`Gate all around: Open
`
`Gate all around: Closed
`
`Public
`
`Slide 16
`November 2014
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon
`on insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 15 - IPR2015-01362
`
`
`
`No end in sight for logic scaling
`
`Public
`
`Slide 17
`November 2014
`
`N 20
`
`N 20 / N 14
`
`N10
`
`N 20 / N 7 N 7 / N 5 N 5 / N 3.5
`
`Bulk CMOS:
`Complementary
`Metal Oxide
`Semiconductor
`
`
`SOI: Partially
`depleted Silicon
`on insulator
`
`
`SOI: Fully depleted
`Silicon on insulator
`
`
`Bulk FinFet :
`fin field effect
`transistor
`
`
`SOI FinFet :
`silicon on insulator
`fin field effect
`transistor, III-V
`
`
`Gate-all-around
`transistor
`
`
`Energetiq Ex. 2038, page 16 - IPR2015-01362
`
`
`
`Significant architectural innovations ahead for Memory
`
`Speed & Bandwidth
`
`Endurance
`
`Public
`
`Slide 18
`November 2014
`
`Working
`Memory
`
`SRAM
`
`DRAM
`
`On-chip
`NVM
`
`ReRAM/STT-MRAM eFlash
`
`Storage
`Class
`Memory
`
`NAND
`HDD
`
`Capacity
`
`PCRAM/ReRAM
`
`3D-ReRAM 3D-NAND
`
`Retention
`
`Cost
`
`Source: Meng-Fan Chang, NTU Taiwan, Resistive memory workshop, Stanford, Oct 2014
`
`Energetiq Ex. 2038, page 17 - IPR2015-01362
`
`
`
`2D NAND vs 3D V-NAND Challenges
`
`2D
`Cell to cell interference
`
`3D
`Aspect ratio
`
`Public
`
`Slide 19
`November 2014
`
`Source: Jung, Samsung, Flash Memory Summit, Santa Clara, Aug 2013
`
`Energetiq Ex. 2038, page 18 - IPR2015-01362
`
`
`
`NAND memory continuing on multiple fronts
`2D extensions, 3D introduction and ReRam coming
`
`Public
`
`Slide 20
`November 2014
`
`2D NAND
`
`BiCS Bit
`Cost
`Scalable 3D
`NAND
`
`3D ReRAM
`3D Resistive
`RAM
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`19 nm
`X2, x3
`
`15 nm
`X2, x3
`
`…?
`
` BiCS Pilot, 3D Productions
`
` ReRAM Technology Development
`
`Source: Siva Sivaram, Sandisk investor day presentation, May 2014.
`
`Energetiq Ex. 2038, page 19 - IPR2015-01362
`
`
`
`NAND memory continuing on multiple fronts
`2D extensions, 3D introduction and ReRam coming
`
`Public
`
`Slide 21
`November 2014
`
`2D NAND
`
`BiCS Bit
`Cost
`Scalable 3D
`NAND
`
`3D ReRAM
`3D Resistive
`RAM
`
`2013
`
`Scalable Below 10 nm;
`2014
`2015
`2016
`New Product Categories
`
`2017
`
`19 nm
`X2, x3
`
`15 nm
`X2, x3
`
`…?
`
`Lower
`Latency
`
`3D Stacking
`
`Higher
`Endurance
`
` BiCS Pilot, 3D Productions
`
`Scaling
`Potential
`
`Lower
` ReRAM Technology Development
`Power/Energy
`
`Source: Siva Sivaram, Sandisk investor day presentation, May 2014.
`
`Energetiq Ex. 2038, page 20 - IPR2015-01362
`
`
`
`NAND memory continuing on multiple fronts
`2D extensions, 3D introduction and ReRam coming
`
`Public
`
`Slide 22
`November 2014
`
`Memory Technology Timelines
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`19 nm
`X2, x3
`
`15 nm
`X2, x3
`
`…?
`
` BiCS Pilot, 3D Productions
`
` ReRAM Technology Development
`
`2D NAND
`
`BiCS Bit
`Cost
`Scalable 3D
`NAND
`
`3D ReRAM
`3D Resistive
`RAM
`
`Source: Siva Sivaram, Sandisk investor day, May 2014
`
`Scott DeBoer, Micron investor day, Aug 2014
`
`
`
`Hybrid Memory Cube
`
`Resistive RAM
`
`Energetiq Ex. 2038, page 21 - IPR2015-01362
`
`
`
`Critical requirements for scaling 3D memory devices
`Etch aspect ratio vs litho scaling cost challenge
`
`Public
`
`Slide 23
`November 2014
`
`Vertical NAND
`
`Cross bar ReRAM
`
`• Gates around conductive vertical
`channel
`• Lithography light, critical overlay to
`top layer
`• Deposition and deep etch intensive,
`horizontal density limited due to etch
`aspect ratio. Key : deep contact etch
`• Large gate size
`
`• Perpendicular gate and channel
`architecture with horizontal
`conduction
`
`• Lithography intensive (< 15nm, EUV)
`
`• Deposition and litho etch per layer
`similar to 2D, density determined by
`litho
`
`• Scalable gate possible
`
`Energetiq Ex. 2038, page 22 - IPR2015-01362
`
`
`
`New memory competes with DRAM and NAND extensions
`and its likely delayed transition determined by cost scaling
`
`Public
`
`Slide 24
`November 2014
`
`Source: S.W. Park, Hynix, ITPC Hawaii, Nov 2014
`
`Energetiq Ex. 2038, page 23 - IPR2015-01362
`
`
`
`Sub-resolution imaging requires multiple litho steps
`
`
`2D Multi Patterning or EUV single
`expose
`
`1D Self Aligned Multiple Patterning
`(SAMP)
`
`Public
`
`Slide 25
`November 2014
`
`LELE (or EUV SE)
`
`LELELE (or EUV SE)
`
`SADP (D=Double)
`
`SAQP (Q=Quadruple)
`
`Mandrel
`
`Mandrel
`
`
`
`
`
`Spacer
`
`Spacer #1
`
`
`
`
`
`Spacer cut
`
`Spacer #2
`
`
`
`Spacer cut
`
`
`
`Patterning
`cut(s)
`
`
`
`Patterning
`cut(s)
`
`
`
`LE #1
`
`LE #1
`
`
`
`
`
`LE #2
`
`LE #2
`
`
`
`LE #3
`
`
`
`Process Flow
`
`Suitable for 1D or 2D patterning
`•
`• Overlay control of each layer is a key
`
`Suitable for 1D layout ( better CD, LWR control)
`•
`• May need multiple cut patterns
`
`Energetiq Ex. 2038, page 24 - IPR2015-01362
`
`
`
`10nm logic design can be done in 1D
` ..but at the penalty of 15% larger die at comparable design rules
`
`Public
`
`Slide 26
`November 2014
`
`1D
`
`
`
`
`
`Die size: 115%
`
`
`
`2D
`
`
`
`Die size: 100%
`
`
`
`Energetiq Ex. 2038, page 25 - IPR2015-01362
`
`
`
`EUV: reduced complexity & design rule simplification
`Allowing 2D structures and potentially better yield
`
`Public
`
`Slide 27
`November 2014
`
`Able to employ jogs
`Reduced # vias (better yield)
`Less min. length (area) wires
`Able to connect to neighbor wire
`
`Better freedom
`for redundant via
`insertion
`
`Reduced MOL
`complexity
`by 2D M1
`
`See
`next
`slide
`
`Source: Esin Terzioglu, Qualcomm, EUV symposium, Oct 2014
`
`Energetiq Ex. 2038, page 26 - IPR2015-01362
`
`
`
`10nm patterning choices & cost estimates
`EUV lowest cost and complexity for 2D structures
`
`Public
`
`Slide 28
`November 2014
`
`EUV
`2D structure
`Single layer solution
`
`ArFi LE4
`2D structure
`Single layer solution
`
`ArFi – 1D only
`6-8 exposures in 3 layers
`(use separate layers for
`horizontal and vertical connections)
`
`
`
`
`Cost for 1 layer 100%
`
`Cost for 1 layer ~ 170%
`
`Cost for 2-3 layers > 250%
`
`Good pattern fidelity
`Re-use existing designs
`
`Insufficient pattern fidelity
`NO SOLUTION
`
`1-2 extra layers needed
`New integration scheme
`Significant cost increase
`
`Energetiq Ex. 2038, page 27 - IPR2015-01362
`
`
`
`Continued significant cost reduction viewed as possible
`but significant innovation is needed
`
`Public
`
`Slide 29
`November 2014
`
`Relative Cost
`Per Gate at Maturity
`
`???
`“traditional path”
`- Primary culprit: litho cost
`
`- New Materials Opportunities
`- Multi-pattern cost down
`- EUV lithography
`- Design/tech co-optimization
`- ….
`
`
`65
`
`45
`
`28
`
`20/14
`
`10
`
`7
`
`Technology Node (nm)
`
`Source: Esin Terzioglu, Qualcomm, EUV symposium, Oct 2014
`
`Energetiq Ex. 2038, page 28 - IPR2015-01362
`
`
`
`EUV supports “free functionality” for the 7nm node
`
`Doubling functionality (2x # gates)
`node-to-node
`
`Public
`
`Slide 30
`November 2014
`
`“Relative Cost”
`
`N10
`
`N7-193i
`
`N7-EUV LS
`
`Source: Esin Terzioglu, Qualcomm, EUV symposium, Oct 2014
`
`Energetiq Ex. 2038, page 29 - IPR2015-01362
`
`
`
`Industry production roadmap summary
`
`NAND / Non Volatile
`Equivalent Node (Feq)
`Node = (WL + BL) / 2
`
`DRAM / Volatile Memory
`Equivalent Node (Feq)
`HP≥ 79% of Feq
`
`LOGIC
`Node
`/ Metal-HP [nm]
`
`Public
`
`Slide 31
`November 2014
`
`MPU
`Node
`/ Metal-HP [nm]
`
`32 / 60 (planar)
`
`22 / 40 (finFET)
`
`40 / 70
`
`32 / 50
`
`28 / 45
`
`20 / 32 (planar)
`
`14 / 30 (finFET)
`
`14~16 / 32 (finFET)
`
`10 / 24 (finFET)
`
`52
`
`48
`
`38
`
`33
`
`28 (6F2)
`
`25 (6F2)
`
`22 (6F2)
`
`19 (6F2)
`
`35
`
`28
`
`22
`
`19 x 22
`
`19
`
`16
`
`16
`
`13
`
`13
`
`10
`
`5x 3D24lyrs
`
`5x 3D32lyrs
`
`5x 3D48lyrs
`
`5x 3D64lyrs
`
`5x 3D96lyrs
`
`16 ReRAM8lrs
`
` 5x 3D128lyrs
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`2022
`
`Note:
`Node
`represents
`start
`volume
`(>10% unit
`share) of
`the typical
`customer
`roadmap
`
` *
`
` Q1-2014
`customer
`roadmaps
`
`
`10 / 19 (finFET)
`
`7 / 12 (finFET)
`
`5 / 8 (finFET)
`
`3 / 5 (finFET)
`
`16 (6F2)
`
`19 MRAM
`
`7 / 16 (finFET)
`
`12 ReRAM8lyrs 5x 3D128lyrs
`
`16 STT-MRAM
`
`5 / 11 (finFET)
`
`12 ReRAM8lyrs
`
`10 ReRAM8lyrs
`
`14 STT-MRAM
`
`3 / 7 (finFET)
`
`Single expose Pattern
`split / Cut mask
`
`Double patterning
`- SPT
`
`Double patterning
`- LxLE
`
`EUV
`
`Energetiq Ex. 2038, page 30 - IPR2015-01362
`
`
`
`Public
`
`Slide 32
`November 2014
`
`Note:
`Node
`represents
`start
`volume
`(>10% unit
`share) of
`the typical
`customer
`roadmap
`
` *
`
` Q1-2014
`customer
`roadmaps
`
`
`Industry production roadmap summary
`
`NAND / Non Volatile
`Equivalent Node (Feq)
`Node = (WL + BL) / 2
`
`DRAM / Volatile Memory
`Equivalent Node (Feq)
`HP≥ 79% of Feq
`
`LOGIC
`Node
`/ Metal-HP [nm]
`
`2009
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`2022
`
`35
`
`28
`
`22
`
`19 x 22
`
`19
`
`5x 3D24lyrs
`16
`Estimated
`5x 3D32lyrs
`16
`NAND EUV
`5x 3D48lyrs
`13
`insertion
`5x 3D64lyrs
`13
`5x 3D96lyrs
`10
`
`16 ReRAM8lrs
`
` 5x 3D128lyrs
`
`52
`
`48
`
`38
`
`33
`Estimated
`28 (6F2)
`DRAM EUV
`25 (6F2)
`insertion
`22 (6F2)
`19 (6F2)
`
`40 / 70
`
`32 / 50
`
`28 / 45
`Estimated
`Logic EUV
`20 / 32 (planar)
`insertion
`14~16 / 32 (finFET)
`
`10 / 24 (finFET)
`
`16 (6F2)
`
`19 MRAM
`
`7 / 16 (finFET)
`
`12 ReRAM8lyrs 5x 3D128lyrs
`
`16 STT-MRAM
`
`5 / 11 (finFET)
`
`12 ReRAM8lyrs
`
`10 ReRAM8lyrs
`
`14 STT-MRAM
`
`3 / 7 (finFET)
`
`MPU
`Node
`/ Metal-HP [nm]
`
`32 / 60 (planar)
`
`22 / 40 (finFET)
`
`Estimated
`14 / 30 (finFET)
`MPU EUV
`10 / 19 (finFET)
`insertion
`
`7 / 12 (finFET)
`
`5 / 8 (finFET)
`
`3 / 5 (finFET)
`
`Single expose Pattern
`split / Cut mask
`
`Double patterning
`- SPT
`
`Double patterning
`- LxLE
`
`EUV
`
`Energetiq Ex. 2038, page 31 - IPR2015-01362
`
`
`
`Our customers moved to the second half of the board
`During the past 66 years 1.4 shrink/year, with more moves to come!
`
`
`Jack Kilby’s first 1 transistor
`oscillator IC, 1958
`
`Public
`
`Slide 33
`November 2014
`
`High-end MPU: 5
`billion transistors
`
`6 Gb DRAM: 6
`billion transistors
`
`128 Gb SLC
`NAND: 137
`billion transistors
`
`High-end GPU: 7
`billion transistors
`
`High-end FPGA: 20
`billion transistors
`
`Energetiq Ex. 2038, page 32 - IPR2015-01362
`
`
`
`Customer roadmap summary
`
`Public
`
`Slide 34
`November 2014
`
`• Significant innovation ahead in logic including scaling enabling
`the continuation of cost reduction for the next 10 years
`
`• Logics environment very competitive relative to manufacturing
`cost dominated by shrink capability
`
`• Memory roadmap to be diversified through the offering on
`multiple hardware innovations connected through software
`
`• Continued shrink planned for the next 10 years to drive memory
`cost delivering power and speed performance in the memory
`architecture
`
`• EUV to bring process simplicity allowing 2D layout enabling more
`effective shrink
`
`Energetiq Ex. 2038, page 33 - IPR2015-01362
`
`
`
`Public
`
`Slide 35
`November 2014
`
`Content
`
`• Industry Challenges
`• The desire to shrink
`
`• The device challenges
`
`• The scaling challenges
`
`• ASML Solutions
`
`• Our holistic approach to extend immersion
`
`• The process simplification by using EUV
`
`Energetiq Ex. 2038, page 34 - IPR2015-01362
`
`
`
`Multi-patterning complexity explodes using immersion
`
`
`Public
`
`Slide 36
`November 2014
`
`5B
`
`5C
`
`5D
`
`5A
`
`4A
`
`4B
`
`3A
`
`3B
`
`3C
`
`3D
`
`3E
`
`21A 21B 21C 21D
`
`21E 21F 21G 21H 21I
`
`22A
`
`22B
`
`22C
`
`1A
`
`1B
`
`1C
`
`1D
`
`1E
`
`1F
`
`Immersion
`
`0A
`
`0B
`
`0C
`
`0D
`
`0E
`
`Layers
`
`Layers
`
`overlay
`measurements
`
`Layers
`
`Layers
`
`Masks
`
`Masks
`
`Masks
`
`Masks
`
`Node
`
`28nm
`
`20nm
`
`# of lithography
`steps
`
`# OVL metrology
`
`6
`
`7
`
`8
`
`9-11
`
`10nm
`
`23
`
`36-40
`
`7 nm all immersion
`
`7 nm all EUV
`
`34
`
`59-65
`
`9
`
`12
`
`Energetiq Ex. 2038, page 35 - IPR2015-01362
`
`
`
`Our Challenge: keep scaling affordable
`
`Public
`
`Slide 37
`November 2014
`
`• Scaling needs to create lower cost and
`improved performance
`
`• Affordable scaling in lithography can be achieved:
`
`• Holistic Lithography with both EUV and Immersion to
`drive on product requirements
`
`•
`
`Immersion: drive productivity and yield (overlay and
`focus control) with multiple patterning using advanced
`litho equipment
`
`• EUV: drive productivity and improve operational cost
`
`Energetiq Ex. 2038, page 36 - IPR2015-01362
`
`
`
`ASML holistic lithography roadmap
`Linking the scanner to YieldStar metrology and Tachyon design context
`
`Public
`
`Slide 38
`November 2014
`
`1. Advanced
`lithography capability
`(Imaging, overlay and
`focus)
`
`Design context used to identify
`hotspot and correct them
`
`3. BRION
`Computational
`lithography
`
`6. Process window
`detection
`
`2. Metrology
`and
`control SW
`
`Energetiq Ex. 2038, page 37 - IPR2015-01362
`
`
`
`1) TWINSCAN immersion product roadmap
`Enabling extension of customer roadmaps and control capital efficiency
`Application Node
`
`Logic DRAM
`
`190 WpH
`
`230 WpH
`
`250 WpH
`
`>275 WpH
`
`On product
`overlay
`
`1st
`Shipment
`
`Public
`
`Slide 39
`November 2014
`
`28
`
`2H
`
`NXT:1950i
`
`2M
`
`NXT:1960Bi
`
`7 nm
`
`2009
`
`6.5 nm
`
`2011
`
`SNEP 1
`
`NXT:1965Ci
`
`PEP 275
`
`6.5 nm
`
`2013
`
`20/16
`/14
`
`2L
`
`NXT:1970Ci
`
`PEP 275
`
`<5 nm
`
`2013
`
`SNEP 2
`
`10
`
`1H
`
`7
`
`1M
`
`SNEP: System Node
`Extension Package
`
`PEP: Productivity
`Enhancement Package
`
`NXT:1980Di
`
`<3.5 nm
`
`2015
`
`NXT:next
`
`2.5 nm
`
`2017
`
`Energetiq Ex. 2038, page 38 - IPR2015-01362
`
`
`
`2) YieldStar 250D; latest ASML metrology system
`Providing Overlay, Focus and CD feedback for scanner control
`
`Public
`
`Slide 40
`November 2014
`
`Illumination
`• Laser Pumped Plasma Source
`• Narrow and wideband filters
`• Wavelength extension to 765nm
`
`Sensor:
`• Optics to support wavelengths up to 780nm
`• Faster cameras with higher detection efficiency
`
`T-250D
`
`S-250D
`
`Energetiq Ex. 2038, page 39 - IPR2015-01362
`
`
`
`3) Negative tone develop model validation
`10nm node metal layer wafer results (triple patterning, LELELE)
`
`Public
`
`Slide 41
`November 2014
`
`Model calibration RMS: 2nm (1D & 2D), Wafer DOF: 80nm, Across wafer CDU: 1.1nm
`
`M1
`
`Litho 1
`
`Litho 2
`
`Litho 3
`
`Logic
`standard cell
`
`SRAM
`
`Source: Imec
`
`Energetiq Ex. 2038, page 40 - IPR2015-01362
`
`
`
`4) Source-mask optimization of flexible illumination
`improves triple patterning process window >23%
`
`Public
`
`Slide 42
`November 2014
`
`Tachyon
`SMO
`
`Standard
`annular
`
`+23%
`
`DoF @ 5% EL
`= 86 nm
`
`DoF @ 5% EL
`= 70 nm
`
`10
`
`8
`
`6
`
`4
`
`2
`
`0
`
`Exposure Latitude (%)
`
`SRAMs
`
`Logic
`
`Anchor
`
`0
`
`20
`
`60
`40
`Depth of Focus (nm)
`
`80
`
`100
`
`• 10nm node metal1: 48nm min. pitch, 3 splits, NTD and M3D models used
`
`• One common source optimized for best imaging of all 3 splits (LELELE)
`
`Source: Imec
`
`Energetiq Ex. 2038, page 41 - IPR2015-01362
`
`
`
`5) 20% improvement in On Product Overlay (per lot)
`looking at the biggest excursions using integrated metrology
`
`Public
`
`Slide 43
`November 2014
`
`Max Overlay per Lot _X [nm]
`
`Standalone metrology Lots
`
`Integrated metrology (IM) Lots
`
`10 scanners, 3 YieldStar S200
`
`5 Litho-clusters with YieldStar T200
`
`20% improvement with IM
`
`OPO spec
`
`Lots run on YieldStar (S on left, T on right, same sampling, same timeframe)
`
`961
`941
`921
`901
`881
`861
`841
`821
`801
`781
`761
`741
`721
`701
`681
`661
`641
`621
`601
`581
`561
`541
`521
`501
`481
`461
`441
`421
`401
`381
`361
`341
`321
`301
`281
`261
`241
`221
`201
`181
`161
`141
`121
`101
`81
`61
`41
`21
`
`1
`
`One month production data 2x node BEOL layer
`
`Each data point is one Lot
`
`Energetiq Ex. 2038, page 42 - IPR2015-01362
`
`
`
`6) Computational lithography now enters the fab
`provide metrology context reducing target and recipe design qualification
`
`Public
`
`Slide 44
`November 2014
`
`Physical overlay
`measurement
`(SEM)
`
`Overlay
`accuracy KPI
`Simulated
`
`Overlay (Accuracy) KPI:
`
`𝛛𝐎𝐕𝐋
`
`𝛛𝐀𝐬𝐲𝐦𝐢
`
`Asymi = {∆SWA, Floor tilt,…}
`MIN
`Overlay KPI
`Marker, recipe
`(marker, recipe)
`
`Overlay simulated and measured on customer product
`wafers of various markers and recipe combinations
`
`(Reproducibility + 0-180˚offset) measured,
`Total Measurement Uncertainty, TMU, [nm]
`
`Physical overlay, measured [nm]
`
`Overlay accuracy KPI, simulated, [nm]
`
`Energetiq Ex. 2038, page 43 - IPR2015-01362
`
`
`
`ASML enabled 18 moves on the chessboard in 30 years
`
`Public
`
`Slide 45
`November 2014
`
`1958
`
`1973
`
`Contact
`printing
`
`1:1
`scanners
`
`DUV step
`scan or
`expose and
`repeat
`
`1973: 1:1 Scanners,
`3 um, 75 mm Wafers, 40 Wafers/hr,
`5.4 Mpixel/s
`
`1984: G/H line
`1,2 um, 100 mm Wafers, 40 W/hr,
`61 Mpixel/s
`
`2014: 193 nm Immersion
`19 nm, 300 mm Wafers, 250 W/hr,
`14 Tpixel/s
`
`1984
`ASML
`
`2014
`
`Energetiq Ex. 2038, page 44 - IPR2015-01362
`
`
`
`Multi-patterning could explode, but EUV will simplify
`through less patterning and metrology steps
`
`Public
`
`Slide 46
`November 2014
`
`EUV
`
`5A
`
`4A
`
`3A
`
`22A
`
`21A
`
`1A
`
`1B
`
`Layers
`
`Layers
`
`Layers
`
`Layers
`
`Masks
`
`Masks
`
`Masks
`
`0A
`
`0B
`
`Masks
`
`Node
`
`28nm
`
`20nm
`
`# of lithography
`steps
`
`# OVL metrology
`
`6
`
`7
`
`8
`
`9-11
`
`10nm
`
`23
`
`36-40
`
`7nm all immersion
`
`7nm all EUV
`
`34
`
`59-65
`
`9
`
`12
`
`Energetiq Ex. 2038, page 45 - IPR2015-01362
`
`
`
`Public
`
`Slide 47
`November 2014
`
`Full size pSi pellicle
`realized, 103x122 mm,
`85% (single pass)
`transmission mounting
`an evaluation in
`progress
`
`EUV to Immersion overlay
`
`Overlay X Overlay Y
`
`1
`
`2
`
`3
`
`4
`
`NXE:3300B litho performance proven
`Good imaging, overlay and full field pellicles
`
`
`5
`
`4.5
`
`4
`
`3.5
`
`3
`
`2.5
`
`2
`
`1.5
`
`1
`
`0.5
`
`0
`
`Matched Machine Overlay [nm]
`
`-60nm
`
`0nm
`
`Focus
`
`60nm
`
`NXE:3300B, 10 nm logic metal 1 layer example, 45 nm
`minimum pitch, 1.6 nm RMS
`
`Source: ST, 2014
`
`Energetiq Ex. 2038, page 46 - IPR2015-01362
`
`
`
`NXE:33x0B demonstrated power supports >1000 wpd
`Up to 7 systems operational at >40W; 100W source operation demonstrated
`
`Public
`
`Slide 48
`November 2014
`
` @ 15 mJ/cm2, 50% efficiency [w/day]
`
`Equivalent Productivity
`
`1200
`
`1000
`
`800
`
`600
`
`400
`
`02
`
`00
`
` NXE:3100
` Proto
`
`Expose speed
`
`Expose speed 3350B (calc.)
`
`Projected WPD
`
` NXE:3300B
`
` NXE:3350B
`
`Demonstrated WPD at
`multiple customer sites
`(@customer conditions)
`
`Lot overhead improvements
`
`100W
`
`100W
`
`80W
`
`80W
`
`40W
`
`100
`
`90
`
`80
`
`70
`
`60
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`@ dose-to-clear [cm2/s]
`
`Expose speed
`
`2Q12
`
`2Q13
`
`4Q13
`
`1Q14
`
`2Q14
`
`3Q14
`
`Oct.
`
`Oct.
`
`Oct.
`
`3350B
`
`3350B
`
`o Dose-to-expose is 2.5x dose-to-clear
`o Productivity: field size 26x33 mm2, 96 fields/wafer, 50% efficiency
`o NXE:3350B data calculated using measured transmission of last system
`
`Time
`
`Energetiq Ex. 2038, page 47 - IPR2015-01362
`
`
`
`Multi-patterning planned with EUV on future nodes but…
`>0.5 high-NA will simplify and extend roadmap again
`
`Public
`
`Slide 49
`November 2014
`
`5B
`
`4B
`
`5A
`
`4A
`
`22A
`
`3A
`
`3B
`
`21A
`
`Layers
`
`5A
`
`4A
`
`3A
`
`22A
`
`21A
`
`Layers
`
`22A
`
`22B
`
`5A
`
`4A
`
`3A
`
`5B
`
`4B
`
`5A
`
`4A
`
`5B
`
`5C
`
`4B
`
`4C
`
`5A
`
`4A
`
`3A
`
`3B
`
`3A
`
`3B
`
`3C
`
`3D
`
`21A
`
`21B
`
`Layers
`
`22A
`
`21A
`
`Layers
`
`22A
`
`21A
`
`Layers
`
`1A
`
`1B
`
`1A
`
`1B
`
`1A
`
`1B
`
`1A
`
`1B
`
`1A
`
`1B
`
`0A
`
`0B
`
`0A
`
`0B
`
`0A
`
`0B
`
`0C
`
`Masks
`
`Masks
`
`Masks
`
`0A
`
`0B
`
`Masks
`
`0A
`
`0B
`
`Masks
`
`Node
`
`7nm - EUV
`
`5nm - EUV
`
`3nm - EUV
`
`5nm - high NA EUV
`
`3nm - high NA EUV
`
`# of lithography
`steps
`
`# OVL metrology
`
`9
`
`12
`
`12
`
`18-22
`
`19
`
`29-36
`
`9
`
`12
`
`12
`
`18-22
`
`Energetiq Ex. 2038, page 48 - IPR2015-01362
`
`
`
`We are preparing to make another 6 moves in 10 years
`Our next move: 13nm EUV lithography
`
`Public
`
`Slide 50
`November 2014
`
`2019-2024: 13nm EUV
`1984: G/H line
`3 nm, 300 mm Wafers,
`1,2 um, 100 mm Wafers, 40 W/hr,
`200 W/hr, 0.45 Ppixel/s
`61 Mpixel/s
`
`1984
`
`2014
`
`2019/
`2024
`
`1958¹
`
`1973
`
`Contact
`printing
`
`1:1
`scanners
`
`DUV step
`scan or
`expose and
`repeat
`
`EUV
`
`¹Jack Kilby’s
`oscillator contains ~
`50 pixels to be
`exposed through
`contact printing
`in 1 sec
`
`Energetiq Ex. 2038, page 49 - IPR2015-01362
`
`
`
`Summary
`
`Public
`
`Slide 51
`November 2014
`
`• Node progression enabled by immersion multi pass patterning and
`extended litho metrology and computational litho to control complexity
`
`• To address highly complex multi-patterning schemes, EUV insertion is
`likely at the 10nm logic and 7nm MPU node with full production one node
`later
`
`• ASML has demonstrated consistent EUV source progress. Today
`performance approaching 100W exposure power. System uptime
`remains a key challenge
`
`• EUV infrastructure supportive for above transition scenarios
`
`• Lithography roadmap defined down to the 3nm node
`
`
`
`
`
`Energetiq Ex. 2038, page 50 - IPR2015-01362
`
`
`
`Public
`
`Slide 52
`November 2014
`
`Had the King’s name been Moore….
`
`Requires careful consideration of the right moves to scale to N10 and beyond
`
`
`
`He would have worked to find ways to scale down his grains, keep
`their nutritional value and double the amount with every move.
`He could have fed the world, instead of having lost a Kingdom.
`
`Energetiq Ex. 2038, page 51 - IPR2015-01362
`
`
`
`Public
`
`Slide 53
`November 2014
`
`Energetiq Ex. 2038, page 52 - IPR2015-01362
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