Trials@uspto.gov
`571-272-7822
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` Paper 29
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` Entered: January 19, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`AMERICAN MEGATRENDS, INC., MICRO-
`STAR INTERNATIONAL CO., LTD, MSI COMPUTER CORP.,
`GIGA-BYTE TECHNOLOGY CO., LTD., and G.B.T., INC.,
`Petitioners,
`
`v.
`
`KINGLITE HOLDINGS INC.,
`Patent Owner.
`_______________
`
`Case IPR2015-01488
`Patent 7,185,189 B2
`____________
`
`
`
`Before GLENN J. PERRY, TREVOR M. JEFFERSON, and
`BRIAN J. McNAMARA, Administrative Patent Judges.
`
`JEFFERSON, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
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`571-272-7822
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` Paper 29
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` Entered: January 19, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`AMERICAN MEGATRENDS, INC., MICRO-
`STAR INTERNATIONAL CO., LTD, MSI COMPUTER CORP.,
`GIGA-BYTE TECHNOLOGY CO., LTD., and G.B.T., INC.,
`Petitioners,
`
`v.
`
`KINGLITE HOLDINGS INC.,
`Patent Owner.
`_______________
`
`Case IPR2015-01488
`Patent 7,185,189 B2
`____________
`
`
`
`Before GLENN J. PERRY, TREVOR M. JEFFERSON, and
`BRIAN J. McNAMARA, Administrative Patent Judges.
`
`JEFFERSON, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
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`IPR2015-01488
`Patent 7,185,189 B2
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`INTRODUCTION
`I.
`American Megatrends, Inc., Micro-Star International Co., Ltd, MSI
`Computer Corp., Giga-Byte Technology Co., Ltd., and G.B.T., Inc.
`(collectively “Petitioner”) filed a Petition (Paper 7, “Pet.”) to institute an
`inter partes review of claims 1–50 of U.S. Patent No. 7,185,189 B2 (Ex.
`1001, “the ’189 patent”) pursuant to 35 U.S.C. § 311 et seq. Patent Owner,
`Kinglite Holdings Inc., filed a Preliminary Response to the Petition (Paper
`11, “Prelim. Resp.”). On January 21, 2016, we instituted inter partes review
`of claims 1–50 of the ’189 patent. Paper 15 (“Dec. to Inst.”). Patent Owner
`filed a Patent Owner Response (Paper 21, “PO Resp.”) and Petitioner filed a
`Reply (Paper 21, “Reply”). Petitioner also filed a Motion to Exclude. Paper
`24 (“Pet. Mot. To Exclude”). Patent Owner filed an Opposition to
`Petitioner’s Motion to Exclude (Paper 25, “Opp. Mot. Exclude”), and
`Petitioner filed a reply (Paper 26, “Pet. Mot. Reply”). A transcript of an oral
`hearing held on October 17, 2016 (Paper 28) has been entered into the
`record.
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). We base our decision on
`the preponderance of the evidence. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d).
`Having reviewed the full record, we conclude that Petitioner has
`demonstrated by a preponderance of the evidence that the challenged claims
`1–50 of the ’189 patent are unpatentable for the reasons set forth below. For
`the reasons discussed below, we also deny Petitioner’s Motion to Exclude.
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`A. Related Proceedings
`The parties state that the ’189 patent has been asserted in Kinglite
`Holdings Inc. v. Giga-Byte Technology Co. Ltd., Case No. 1:14-cv-04989
`(C.D. Cal.), and Kinglite Holdings Inc. v. Micro-Star International Co Ltd.,
`Case No. 1:14-cv-03009 (C.D. Cal.). Paper 6, 1; Paper 9, 1.
`
`B. The ʼ189 Patent
`The ’189 patent is titled “Method of Storing BIOS Modules and
`Transferring Them to Memory for Execution.” Ex. 1001, at [54]. The ’189
`patent discloses a “[m]ethod [] for processing basic input output system
`(BIOS) modules of a computer to initialize the computer.” Id. at [57]. The
`’189 patent states that “[s]elected BIOS modules required for operation of
`the computer are transferred from the critical nonvolatile storage device, and
`optionally a protected area of the secondary nonvolatile storage device, to
`system memory and executed to initialize the computer.” Id.
`Figure 2, depicted below, illustrates an embodiment of the ’189
`patent.
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`Figure 2 illustrates computer 10a that stores BIOS modules in a protected
`area, transfers selected BIOS modules to system memory 13 and executes
`selected BIOS modules. Id. at 4:52–60. A first portion of nonvolatile
`storage device 15 stores initialization code 16 that is operative to initialize
`CPU 11 and system memory 13. Id. at 5:9–11. A second portion of
`“nonvolatile storage device 15 stores a dispatch manager 17 that contains a
`list of tasks, which must execute to fully initialize the computer 10a.” Id. at
`11–14. Dispatch manager 17 selectively loads and iteratively executes a
`number of tasks relating to complete initialization of the computer. Id. at
`14–17.
`The ’189 patent also states that
`In operation, when the computer 10a is turned on, the
`initialization code 16 is run to initialize the CPU 11 and the
`system memory 13. The dispatch manager 17 is then loaded 20
`into the system memory 13. The dispatch manager 17 executes
`the list of tasks contained therein to cause all required BIOS
`modules to be loaded into the system memory 13 [that] must be
`executed.
`Id.at 5:18–24.
`Figure 6, depicted below, illustrates method 50 used to store BIOS
`modules in a computer protected area.
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`Figure 6 provides a flow diagram depicting in step 51 that minimal
`initialization code 16 corresponding to a small portion of the computer
`system BIOS is stored in a first portion of nonvolatile storage device 15. Id.
`at 8:20–35. In step 52, dispatch manager 17 containing tasks relating to
`configuring the computer 10a is stored in a second portion of nonvolatile
`storage device 15. Id. A plurality of BIOS modules are stored in step 53 in
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`a protected area of a secondary nonvolatile storage device. Id. Storage
`device 15 “may comprise a hard disk drive, a compact disk ROM, a flash
`memory, a floppy disk drive, a Zip drive, or a SuperDisk drive, for
`example.” Id. at 8:35–38.
`Once the computer is turned on in step 54, minimal initialization code
`is executed in step 55. In step 56, the dispatch manager 17 is copied in step
`56 from the critical nonvolatile storage device 15 into the system memory
`11, and executed in step 57. Id. at 8:40–44. Steps 58 and 59 execute tasks
`that are already loaded into memory or find the code necessary to execute
`the tasks if not already loaded into memory. Id. at 8:44–53. The operating
`system of the computer is launched in step 65 once all the tasks are loaded
`and executed. Id. at 8:53–57.
`
`C. Illustrative Claims
`Independent claims 1 and 14 are illustrative and reproduced below
`(Ex. 1001, 9:1–24, 10:33–54):
`1. A computer program product comprising: a computer
`usable medium having computer program code embodied
`therein to process basic input output system (BIOS)
`modules of a computer, said computer having a central
`processing unit (CPU), a system memory and a nonvolatile
`storage device, the computer usable medium having:
`computer readable program code for storing a
`predetermined amount of BIOS initialization code in a
`first portion of the nonvolatile storage device;
`computer readable program code for storing a
`dispatch manager in a second portion of the nonvolatile
`storage device that is operative to selectively load and
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`iteratively execute a predetermined number of tasks
`relating to initialization of the computer;
`computer readable program code for executing the
`predetermined amount of BIOS initialization code to
`initialize the CPU and the system memory;
`computer readable program code for copying the
`dispatch manager from the nonvolatile storage device to
`the system memory; and
`computer readable program code for executing the
`dispatch manager to execute the predetermined number of
`tasks to initialize the computer.
`
`14. A system for processing basic input output system
`(BIOS) modules comprising:
`a processor;
`a nonvolatile storage device coupled
`processor; and
`a memory coupled to the processor, said memory
`containing instruction sequences which, when executed by
`the processor, cause the processor to:
`store a predetermined amount of BIOS initialization
`code in a first portion of the nonvolatile storage device that
`is operative to initialize the processor and a system
`memory,
`store a dispatch manager in a second portion of the
`nonvolatile storage device that is operative to selectively
`load and iteratively execute a predetermined number of
`tasks relating to complete initialization,
`execute
`the predetermined amount of BIOS
`initialization code to initialize the processor and the
`system memory,
`copy the dispatch manager from the nonvolatile
`storage device to the system memory, and
`execute the dispatch manager to execute said
`predetermined number of tasks.
`
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`D. Grounds of Unpatentability Instituted
`We instituted inter partes review on the following grounds of
`unpatentability (Dec. to Inst. 24–25):
`
`Reference(s)
`Shipman1
`
`Shipman and Harmer2
`Shipman, Harmer, and
`Patel3
`
`Basis
`35 U.S.C. § 103(a)
`
`35 U.S.C. § 103(a)
`
`35 U.S.C. § 103(a)
`
`Claims Challenged
`1 and 14
`2–5, 7–13, 15–18, 20–30,
`32–42, and 44–50
`6, 19, 31, and 43
`
`II. ANALYSIS
`A. Claim Interpretation
`
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. See 37 C.F.R. § 42.100(b); Cuozzo Speed
`Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016). Under this standard,
`we interpret claim terms using “the broadest reasonable meaning of the
`words in their ordinary usage as they would be understood by one of
`ordinary skill in the art, taking into account whatever enlightenment by way
`of definitions or otherwise that may be afforded by the written description
`
`
`1 U.S. Patent No. 5,671,413 to Shipman et al., filed Oct. 31, 1994, and issued
`Sep. 23, 1997 (Ex. 1005, “Shipman”).
`2 U.S. Patent No. 5,835,760 to Harmer, filed Oct. 13, 1995, and issued
`Nov. 10, 1998 (Ex. 1003, “Harmer”).
`3 U.S. Patent No. 5,999,989 to Patel, filed Jun. 17, 1997, and issued Dec. 7,
`1999 (Ex. 1007, “Patel”).
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`contained in the applicant’s specification.” In re Morris, 127 F.3d 1048,
`1054 (Fed. Cir. 1997).
`In the Decision to Institute, we applied the following claim
`constructions. Dec. to Inst. 10–12. We determined that “BIOS initialization
`code” as recited in claims 1, 14, 27, and 39 as “predetermined amount of
`BIOS initialization code” does not require further construction. Id. at 11.
`We also determined that “dispatch manager” as recited in claims 1–4, 14–17,
`27–29, and 39–41, is construed as a program that handles the locating,
`loading and executing of task code. Id. at 12. Finally, we adopted the
`parties’ agreed construction of “system memory” as “random access
`memory (RAM).” Id. As neither Petitioner’s nor Patent Owner’s
`arguments persuade us to revise our interpretations of “BIOS initialization
`code,” “dispatch manager,” or “system memory,” we adopt as final our
`determinations of the broadest reasonable interpretations of those terms.
`Dec. to Inst. 10–12.
`
`B. Level of Skill in the Art
`Petitioner contends that a person of ordinary skill in the art for the
`’189 patent would be “a person having at least a Bachelor of Science degree
`in computer science or software engineering or a Bachelor of Science degree
`in a technical field requiring computer science or software engineering
`courses and at least one year of industry experience in computer science or
`engineering related to firmware.” Pet. 10 (citing Ex. 1013 ¶ 15). Patent
`Owner does not dispute this proposed level of skill in the art. Based on the
`full record, we agree with Petitioner.
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`C. Claims 1 and 14: Shipman (Ex. 1005)
`1. Shipman (Ex. 1005)
`Shipman discloses that BIOS services for a computer “are
`implemented via a number of independently executable service
`components.” Ex. 1005, [57]. The BIOS uses a decompression dispatcher
`for decompressing and dispatching the service components into RAM of the
`computer for execution. Id. When the service components are no longer
`needed, the decompression dispatcher also removes the service components
`and stores them in a compressed state. Id.
`Shipman discloses that “different . . . (BIOS) functions are split into
`components, or objects, and selected ones of the components are stored in a
`compressed state and these compressed components are only decompressed
`and executed when needed.” Id. at 1:47–51. Shipman further states that
`[t]he BIOS stored in a read only memory (ROM) is organized
`into a set of components, each being dispatched as an
`independent executable object after being copied to a shadow
`memory portion of a random access memory (RAM). Three
`types of components are defined, initialization components,
`runtime components and
`functional components.
` The
`initialization components are dispatched during a Power On Self
`Test (POST) cycle such that the initialization components are
`active during initialization.
`Id. at 1:60–2:1 (emphasis added).
`Figure 1 below depicts a block diagram of a computer system that
`embodies the invention disclosed by Shipman.
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`Figure 1 of Shipman shows read only memory (ROM) 10, dynamic
`random access memory (DRAM) 22, memory cache 24, controller 20, and
`central processing units (CPUs) (28, 30). Id. at 2:63–3:1. The modularized
`BIOS in ROM 10 facilitates transfer of data and instructions between the
`CPUs and peripheral devices. Id. at 3:2–5. The BIOS is organized into
`components (32 through 54) that each perform a certain task or function and
`are capable of being dispatched as independent executable objects. Id. at
`3:6–12. The BIOS components fall into three types: initialization
`components, runtime components, and functional components. Id.
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`2. Analysis
`Petitioner contends that Shipman renders claims 1 and 14 obvious.
`Pet. 14–31. Petitioner provides claim charts and citations to the Declaration
`of Michael Perla (Ex. 1013) to support its contentions. Id. (citing Ex. 1013
`¶¶ 58, 61, 66, 68, 69, 71, 73, 75–79, 84–91, 96, and 97).
`Petitioner contends that the BIOS components and objects used with
`the decompression dispatcher in Shipman disclose the BIOS modules, BIOS
`initialization code, nonvolatile storage, and dispatch manager of claims 1
`and 14. Pet. 14–15. Petitioner contends that to the extent Shipman does not
`expressly disclose “executing the predetermined amount of BIOS
`initialization code to initialize the CPU and the system memory” as recited
`in the challenged claims, Shipman’s disclosure of beginning instructions of
`testing and initializing the memory controller in Figure 2 (Ex. 1005, Fig. 2,
`step 202) renders the limitation obvious. Pet. 15–16.
`Petitioner provides detailed evidence and argument showing that
`Shipman discloses a computer program with BIOS modules (Pet. 16–18),
`code for storing a predetermined amount of BIOS initialization code in
`storage (id. at 18–20), a dispatch manager that selectively loads and
`iteratively executes tasks related to initialization (id. at 20–23), code for
`executing the BIOS initialization code (id. at 23–25), and code for copying
`the dispatch manager from storage memory to system memory and
`executing the dispatch manager to execute the tasks (id. at 25–26).
`Patent Owner contends that Petitioner’s declarant testimony from Mr.
`Perla should be disregarded (PO Resp. 3–5) and that Mr. Perla’s testimony
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`fails to show that Shipman discloses that the dispatch manager “selectively
`load[s] and iteratively execute[s] a predetermined number of tasks relating to
`complete initialization of the computer” as recited in claims 1 and 14 (PO
`Resp. 7–8).
`With respect to Mr. Perla’s testimony, Patent Owner contends that
`Mr. Perla’s declaration testimony (Ex. 1013 ¶ 56) is contradicted and
`undermined by his deposition testimony that shows him scrambling and
`leading counsel “on a wild goose chase” to support his declaration (PO
`Resp. 3–54 (citing Ex. 2010, 28:7–8, 29:7–23, 32:20–33:6, 33:15–20, 33:21–
`34:14; 35:7–36:25, 46:1–12)). Patent Owner argues that Mr. Perla’s
`testimony should be ignored because he “fabricates an aspect of modularity”
`in the Harmer reference to combine it with the modularity contemplated in
`the Shipman reference. PO Resp. 3–5. We disagree, finding that the
`deposition testimony cited by Patent Owner concerning “portions of BIOS”
`as contrasted with “BIOS modules” does not support the conclusion that Mr.
`Perla’s testimony should be disregarded in its entirety or given no weight.
`Considered in its entirety (Ex. 2010 and Ex. 1013), we find sufficient
`support and explanation for Mr. Perla’s testimony regarding modularity of
`Harmer and Shipman. In addition, Patent Owner’s deposition questions are
`
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`4 We note that Patent Owner’s citations to the testimony of Mr. Perla (PO
`Resp. 3–5) do not support Patent Owner’s contentions. For example, the
`Patent Owner response quotes Mr. Perla’s testimony (PO Resp. 3–4), but the
`deposition exhibit citations (Ex. 2010, 28:7–8, 28:10–12, 28:13–16), do not
`contain the quoted language and do not support Patent Owner’s contentions.
`In the absence of accurate citations to the record, we have considered Mr.
`Perla’s testimony in its entirety (see Ex. 2010).
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`narrowly drawn and fail to support Patent Owner’s contentions that Mr.
`Perla fabricated his testimony regarding the modular teachings of the
`Harmer reference. PO Resp. 3–5 (citing Ex. 2010, 28:7–8, 29:7–23, 32:20–
`33:6, 33:15–20, 33:21–34:14; 35:7–36:25, 46:1–12). Accordingly, we do
`not disregard the testimony of Mr. Perla.
`With respect to the merits of the Shipman disclosure, Patent Owner
`contends that Mr. Perla’s testimony shows that Shipman offers only a binary
`choice to load either all class components or one class component, but fails
`to show selectively loading less than all class components. PO Resp. 7–8
`(citing Ex. 2010, 22:22–24, 22:25–30, 25:16–26:23). In sum, Patent Owner
`asserts that Shipman does not disclose “selectively loading” as recited in
`claims 1 and 14, arguing that the claims require the option of loading more
`than one, but less than all, components. PO Resp. 7–8.
`We are not persuaded by Patent Owner’s contentions. Petitioner
`provides persuasive evidence that Figure 5 of Shipman (a flowchart
`depicting how components are dispatched) is used with the “packing list” to
`determine which modules to load and execute. Pet. 20–21; Reply 1–2. We
`agree with Petitioner that Mr. Perla’s testimony (Ex. 2020, 26:22–28:3)
`supports the disclosure evidenced in Shipman that the packing list allows for
`selection of a smaller amount of the available modules. We find that steps
`502 and 504 in Figure 5 of Shipman disclose that not all components in a
`class may be loaded and expressly branch to step 512 to refer to the packing
`list to load selected components of a class. See Ex. 1005, 12:49–56. Thus,
`we agree with Petitioner that Figure 5 of Shipman “refer[s] to step 512 (get
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`packing information), step 514 (uncompress and place in RAM), step 516
`(check if there are more components to uncompress), and if yes proceed to
`step 518 (decrement counter and get packing list information as stated in
`step 512).” Reply 1. Based on complete record, we find that Figure 5 of
`Shipman discloses that less than all components, but more than one
`component, of a class may be loaded. Ex. 1005, Fig. 5 (steps 504, 512, 514,
`516, and 518).
`We also note that even if Shipman were limited to loading one or all
`class components, “the selectively load” limitation of claim 1 is disclosed in
`the packing list used in Shipman to select which modules are needed even if
`the choice was limited one component or all components. Thus, we are not
`persuaded by Patent Owner’s argument that “selectively load and iteratively
`execute a predetermined number of tasks relating to complete initialization
`of the computer” requires more than one but less than all components to
`disclose selectively loading. PO Resp. 7–8. We find that Shipman’s
`“decompression dispatcher” is operative to execute a predetermined number
`of tasks. “When dispatching components the decompression dispatcher
`works from a Packing List provided in the ROM image by the BIOS build
`process.” Ex. 1005, 5:27–29. The packing list in Shipman “provides a
`detailed description of the packing as well as other important pieces of
`information regarding the types of components.” Id. at 5:31–34. Consistent
`with the teachings of Shipman, we agree with Petitioner’s argument and
`testimony from Mr. Perla that a person of ordinary skill in the art would
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`understand that a packing list specifies a predetermined number of tasks.
`Pet. 21–22; Ex. 1013 ¶ 78.
`Patent Owner also contends that Shipman differs from the ’189 patent
`which “depicts [in Figure 6] that a minimum degree of BIOS initialization
`code must be executed (step 55) in order for both the processor and system
`memory to be ready for the operation of the dispatch manager (steps 56–57).
`PO Resp. 8–9. Patent Owner argues that the opposite process occurs in
`Shipman where “the system cannot be initialized unless the decompression
`dispatcher decompresses and dispatches the main POST component.” Id. at
`9. Patent Owner asserts that
`unlike the teachings of the ’189 Patent, where the operation of
`the BIOS initialization code is executed before the operation of
`the dispatch manager, the component charged with the
`initialization of the memory in Shipman, i.e., POST component
`(32), comes
`into play only after the operation of the
`decompression dispatcher (52).
`Id. at 9–10. Thus, Patent Owner argues that Shipman does not disclose
`“BIOS initialization code” or the “dispatch manager” of the ’189 patent
`because the dispatch manager must be operating on initialized memory. Id.
`at 9–10 (citing Ex. 2010, 71:11–23).
`We are not persuaded by Patent Owner’s arguments, which conflate
`the POST Loader and POST disclosed in Shipman. Petitioner relies on the
`POST Loader to disclose the “BIOS initialization code” limitations. Pet.
`18–20, 27; Reply 3–5. Shipman describes the process of dispatching its
`modular BIOS in Figure 2. Ex. 1005, Fig. 2, 2:32–33. We find that Figure 2
`of Shipman discloses the initialization of memory controller related
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`components in step 202 before the initialization of the decompression
`dispatcher (dispatch manager) and execution of POST. Ex. 1005, 12:8–13,
`Fig. 2 (steps 202, 204, and 206). Petitioner relies on the POST Loader as the
`code in step 202 of Figure 2 as the BIOS initialization code that leads to the
`dispatch manager being copied and executed. Pet. 19; Reply 4; Ex. 1013
`¶ 73. Patent Owner’s arguments are not commensurate with the scope of the
`Shipman reference, which discloses code that initializes the memory to copy
`and execute the dispatch code. Ex. 1005, 6:49–59, 12:10–16; Ex. 1013
`¶¶ 71, 86. Once initialized, Shipman includes BIOS modules like POST that
`is handled by the dispatch manager to initialize the rest of the system. Ex.
`1005, 4:53–54, 6:61–67, 12:12–16, Fig. 2 (steps 204, 206).
`We are not persuaded by Patent Owner’s argument that Shipman fails
`to disclose “BIOS initialization code” or the “dispatch manager” as recited
`in claims 1 and 14. We credit and adopt Petitioner’s evidence and argument
`showing that the POST Loader discloses the “BIOS initialization code”
`limitations and the “decompression dispatcher” discloses the dispatch
`manager limitation. Reply 3–5; Pet. 18, 20; Ex. 1013 ¶¶ 75–76; Ex. 1005,
`4:37–40; 6:50–59.
`Based on the full record, Petitioner has provided sufficient evidence
`and argument that Shipman teaches the limitations of claims 1 and 14. Thus,
`we determine that Petitioner has shown by a preponderance of the evidence
`that claims 1 and 14 are unpatentable as obvious under 35 U.S.C § 103(a)
`over Shipman.
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`D. Claims 2–5, 7–13, 15–18, 20–30, 32–42, and 44–50:
`Shipman (Ex. 1005) and Harmer (Ex. 1003)
`1. Harmer (Ex. 1003)
`Harmer (Ex. 1003) is cited and discussed in the ’189 patent as
`background prior art. Ex. 1001, 1:63–2:9. The ’189 patent states that in
`Harmer “[t]he host computer executes instructions contained in the first
`portion of the BIOS and reads the second portion of the BIOS (i.e., the entire
`BIOS) from the protected area of the hard disk drive into the system RAM.”
`Ex. 1001, 1:56–60 (discussing Harmer). Harmer discloses a method where a
`portion of the BIOS used to start and initialize a host computer is stored
`within the mass memory storage rather than stored within ROM. Ex. 1003,
`[57].
`Harmer states that “[a] first portion of the BIOS (initialization code) is
`stored in a read only memory (ROM) which is not a flash memory, and a
`second portion of the BIOS is stored in a protected area of a mass memory
`storage peripheral computer device (hard disk) rather than in ROM.” Ex.
`1001, 1:45–49. “[T]he second portion of the BIOS may be expansion BIOS
`associated with a particular peripheral computer device or system BIOS
`associated with the host computer.” Id. at 1:50–53.
`2. Analysis
`Petitioner contends that Shipman and Harmer render claims 2–5, 7–
`13, 15–18, 20–30, 32–42, and 44–50 obvious. Pet. 31–57. Petitioner
`provides claim charts (Pet. 44–56) and citations to the prior art and
`testimony in support of its contention. Petitioner also provides an articulated
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`reason with a rational underpinning to support why a person of ordinary skill
`in the art would be motivated to combine the decompression dispatcher in
`Shipman with the distribution of BIOS to different memory devices of
`Harmer. Pet. 32. Petitioner contends that the combination of Harmer and
`Shipman would be a combination of familiar elements according to known
`methods that would yield predictable results. Pet. 33 (citing KSR Int’l Co. v.
`Teleflex, Inc., 550 U.S. 398, 416 (2007)).
`Petitioner provides citations to the art of record and testimony of Mr.
`Perla to support its contentions that the BIOS modules stored in nonvolatile
`memory disclosed in Shipman, combined with Harmer’s usage of storing
`BIOS in secondary nonvolatile storage devices, teaches the limitations of
`independent claims 27 and 39 and dependent claims 2–5, 7–13, 15–18, 20–
`26, 28–30, 32–38, 40–42, and 44–50. Pet. 33–57. The challenged claims
`are directed to storing BIOS modules in a protected area of secondary
`nonvolatile storage while the dispatch manager and BIOS initialization code
`are stored in the nonvolatile storage device. Thus, Petitioner asserts that
`Shipman, which discloses storing all components in a read-only memory
`(Ex. 1005, Fig. 1 (ROM 10)), in combination with Harmer’s teaching of
`storing BIOS in secondary nonvolatile storage devices renders the
`challenged claims obvious.
`Based on the full record, Petitioner has provided sufficient evidence
`and argument that Shipman and Harmer teach the limitations of claims 2–5,
`7–13, 15–18, 20–30, 32–42, and 44–50 by a preponderance of the evidence.
`Pet. 31–57. Accordingly, we agree with and adopt Petitioner’s analysis.
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`Pet. 31–57; Reply 5–14. Patent Owner challenges the motivation to
`combine Shipman and Harmer, selected limitations general to all challenged
`claims, and dependent claims 7, 20, 32, and 44. We address Patent Owner’s
`contentions below.
`Patent Owner contends that there is no motivation to combine the
`Harmer and Shipman references because there is no support for the
`testimony of Mr. Perla that Harmer contemplates modular BIOS. PO Resp.
`3–5, 11–13. As discussed above, we disagree with Patent Owner’s argument
`that Mr. Perla’s deposition testimony shows there is no support for his
`opinion that a skilled artisan would have been motivated to combine Harner
`and Shipman given that both deal with BIOS modularity because “Harmer’s
`purported BIOS modularity was fiction.” PO Resp. 11. Considering Mr.
`Perla’s testimony in its entirety, Mr. Perla’s deposition testimony is
`consistent with his declaration testimony that Harmer’s teachings of
`expansion BIOS are similar to the teachings in Shipman relied upon by
`Petitioner. Compare Ex. 1013 ¶ 56, with Ex. 2010, 30:3–11. We do not find
`that Mr. Perla’s deposition testimony undermines the testimony regarding
`what Harmer teaches a person of ordinary skill in the art. Petitioner relies on
`Harmer to establish that it was known, prior to the time of invention of the
`’189 patent, to store BIOS modules in a protected area of a secondary
`nonvolatile storage device to reduce the cost of the ROM by relocating
`BIOS components to the mass memory storage of peripheral computer
`devices. Reply 9–10; Ex. 1013 ¶¶ 110–111; Ex. 1003, 4:63–67; Pet. 32–33.
`We are not persuaded by Patent Owner’s argument based solely on the
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`deposition testimony of Mr. Perla that there is no support for Mr. Perla’s
`opinion regarding the applicability of Harmer to modular BIOS. PO Resp.
`11.
`
`We also find unavailing Patent Owner’s argument that we should not
`credit Mr. Perla’s testimony because he did not encounter Shipman and
`Harmer at the time of invention of the ’189 patent. PO Resp. 12. Patent
`Owner cites no case law or support for the contention that Mr. Perla’s
`testimony should be disregarded because he lacked familiarity with a
`reference. The proper inquiry is what the references, which are presumed to
`be available, teach a person of ordinary skill in the art at the time of
`invention. See In re Rouffet, 149 F.3d 1350, 1357 (Fed. Cir. 1998) (“[The
`law] presumes that all prior art references in the field of the invention are
`available to this hypothetical skilled artisan.”); Custom Accessories, Inc. v.
`Jeffrey-Allan Indus., 807 F.2d 955, 962 (Fed. Cir. 1986) (“The person of
`ordinary skill is a hypothetical person who is presumed to be aware of all the
`pertinent prior art.”). Accordingly, Patent Owner’s arguments about Mr.
`Perla’s awareness of Harmer or Shipman are not well founded and
`unavailing.
`We also disagree with Patent Owner’s contention that Shipman is
`limited to operating on primary storage and excludes use of secondary
`storage. PO Resp. 12–13 (citing Ex. 2011 ¶¶ 3–4; Ex. 1005, 3:32–40, Fig 1
`(items 36, 42, and 48)). Patent Owner’s evidence does not show that
`Shipman purposefully excludes the possibility of using secondary storage.
`We do not credit Patent Owner’s declarant’s conclusory statement limiting
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`Shipman to primary storage and excluding secondary storage, as that
`testimony lacks a citation to evidence or support. Instead, we agree with and
`credit Petitioner’s evidence that Shipman and Harmer teach use of PCI
`(Peripheral Components Interconnect) that would support expansion ROM
`for PCI devices for use during initialization or boot functions. Ex. 1003,
`1:43–47, 4:27; Ex. 1013 ¶¶ 108–109; Ex. 1009 § 6.3. We also agree with
`Petitioner that Shipman discloses use of Option ROM indicating that
`Shipman contemplates use of non-primary, nonvolatile storage during BIOS
`module component loading. Ex. 1005, Fig. 5 (item 520), 3:3–5, 10:35–58;
`Ex. 1017, 51:5–52:21; Reply 13.
`Based on the full record, Petitioner has provided articulated reasons
`with rational underpinnings to support the combination of Shipman, which
`teaches use of nonvolatile storage for BIOS modules, with Harmer, which
`teaches storing BIOS in secondary nonvolatile storage devices.
`Patent Owner also contends that Mr. Perla’s discussion of “secondary
`nonvolatile storage device” in Shipman is baseless and should be ignored.
`PO Resp. 13–14 (citing Ex. 1013 ¶¶ 116, 117, 131); Ex. 2010, 47:11–19,
`48:1–21; 49:4–6.
`Petitioner responds that “secondary nonvolatile storage device” as
`recited in the challenged claims is disclosed in Harmer, which states: “A
`second portion of the expansion BIOS associated with the particular
`peripheral computer device is stored within the mass memory storage of the
`m
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