IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Robert C. Chang et al.:
`
`Petition for Inter Partes Review
`
`U.S. Patent No. 6,831,865
`
`Issued: December 14, 2004
`
`Title: Maintaining Erase Counts in
`Non-Volatile Storage Systems
`
`Attorney Docket No.:
`337722-000080.865
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`Real Party-in-Interest: Apple Inc.
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,831,865
`
`Mail Stop Patent Board
`
`Patent Trial and Appeal Board
`
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
`
`
`
`Dear Sir:
`
`Pursuant to the provisions of 35 U.S.C. §§ 311-319, Apple Inc. (hereinafter
`
`“Petitioner”) hereby petitions the Patent Trial and Appeal Board to institute an
`
`inter partes review of claims 1-5, 8, 18, and 24-29 of United States Patent
`
`No. 6,831,865 (Ex. 1001).
`
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`Page
`I. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Lead and Back-up Counsel .................................................................. 1
`D.
`Service Information .............................................................................. 2
`II. GROUNDS FOR STANDING ....................................................................... 2
`III. RELIEF REQUESTED .................................................................................. 2
`IV. THE REASONS FOR THE REQUESTED RELIEF ..................................... 2
`A.
`Summary of Reasons ............................................................................ 3
`B.
`Relevant Background Technology ....................................................... 4
`1.
`Overview of Flash Memory ....................................................... 4
`2.
`Failure Mechanisms in Flash Memory ...................................... 5
`3. Managing Flash Memory Failures ............................................. 6
`4.
`Organization of Data and Metadata Within Flash
`Memory ...................................................................................... 7
`Overview of the PCMCIA Standard : FTL Specification ......... 9
`5.
`Overview of the ’865 Patent .................................................... 12
`6.
`Level of Ordinary Skill in the Art ...................................................... 13
`Claim Construction under 37 C.F.R. § 42.104(b)(3) ......................... 14
`1.
`“data structure” (claims 1-5, 8 and 25-29) ............................... 15
`2.
`“means for indicating in the system memory a number of
`times each usable block included in the plurality of
`blocks has been erased” (claim 18) .......................................... 15
`Challenge #1: U.S. Patent No. 5,485,595 (“Assar”) Anticipates
`Claims 1-3, 5, 18, and 25- 27 ............................................................. 17
`1.
`Overview of Assar ................................................................... 17
`2.
`Assar anticipates independent claim 1 ..................................... 19
`3.
`Assar anticipates dependent claim 2 ........................................ 22
`4.
`Assar anticipates dependent claim 3 ........................................ 23
`5.
`Assar anticipates dependent claim 5 ........................................ 24
`- i -
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`C.
`D.
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`E.
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`TABLE OF CONTENTS
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`

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`Page
`I. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Lead and Back-up Counsel .................................................................. 1
`D.
`Service Information .............................................................................. 2
`II. GROUNDS FOR STANDING ....................................................................... 2
`III. RELIEF REQUESTED .................................................................................. 2
`IV. THE REASONS FOR THE REQUESTED RELIEF ..................................... 2
`A.
`Summary of Reasons ............................................................................ 3
`B.
`Relevant Background Technology ....................................................... 4
`1.
`Overview of Flash Memory ....................................................... 4
`2.
`Failure Mechanisms in Flash Memory ...................................... 5
`3. Managing Flash Memory Failures ............................................. 6
`4.
`Organization of Data and Metadata Within Flash
`Memory ...................................................................................... 7
`Overview of the PCMCIA Standard : FTL Specification ......... 9
`5.
`Overview of the ’865 Patent .................................................... 12
`6.
`Level of Ordinary Skill in the Art ...................................................... 13
`Claim Construction under 37 C.F.R. § 42.104(b)(3) ......................... 14
`1.
`“data structure” (claims 1-5, 8 and 25-29) ............................... 15
`2.
`“means for indicating in the system memory a number of
`times each usable block included in the plurality of
`blocks has been erased” (claim 18) .......................................... 15
`Challenge #1: U.S. Patent No. 5,485,595 (“Assar”) Anticipates
`Claims 1-3, 5, 18, and 25- 27 ............................................................. 17
`1.
`Overview of Assar ................................................................... 17
`2.
`Assar anticipates independent claim 1 ..................................... 19
`3.
`Assar anticipates dependent claim 2 ........................................ 22
`4.
`Assar anticipates dependent claim 3 ........................................ 23
`5.
`Assar anticipates dependent claim 5 ........................................ 24
`- i -
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`C.
`D.
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`E.
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`TABLE OF CONTENTS
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`

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`TABLE OF CONTENTS
`(continued)
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`Page
`
`F.
`
`G.
`
`H.
`
`I.
`
`J.
`
`Assar anticipates independent claim 18 ................................... 25
`6.
`Assar anticipates independent claim 25 ................................... 27
`7.
`Assar anticipates dependent claim 26 ...................................... 30
`8.
`Assar anticipates claim 27 ....................................................... 31
`9.
`Challenge #2: Claims 8, 24 and 29 are obvious over Assar in
`view of the knowledge of a POSITA ................................................. 31
`1.
`Assar, in combination with the knowledge of a POSITA
`renders obvious claims 8, 24 and 29 ........................................ 31
`Challenge #3: Claims 4-5 and 28 are obvious over Assar in
`view of U.S. Patent No. 5,838,614 (“Estakhri”) ................................ 33
`1.
`Overview of Estakhri ............................................................... 33
`2. Motivation to Combine Assar and Estakhri ............................. 34
`3.
`Assar and Estakhri render obvious Claims 4, 5, and 28 .......... 35
`Challenge #4: U.S. Patent No. 6,427,186 (“Lin”) anticipates
`Claim 18 ............................................................................................. 37
`1.
`Overview of Lin ....................................................................... 37
`2.
`Lin anticipates claim 18 ........................................................... 39
`Challenge #5: Claim 24 is obvious over Lin in view of the
`knowledge of a POSITA .................................................................... 41
`1.
`Claim 24: The non-volatile memory system of claim 18
`wherein the non-volatile memory is a NAND flash
`memory .................................................................................... 41
`Challenge #6: Claims 1-3, 8, 18, 24- 27 and 29 are obvious over
`U.S. Patent No. 6,381,176 (“Kim”) in view of the Linux
`Publication and the knowledge of POSITA ....................................... 42
`1.
`Overview of Kim ..................................................................... 42
`2.
`Overview of the Linux Publication .......................................... 44
`3.
`Independent claim 1 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 46
`
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`TABLE OF CONTENTS
`(continued)
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`Page
`
`4.
`
`5.
`
`6.
`
`7.
`
`Dependent claim 2 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 50
`Dependent claim 3 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 51
`Claim 8 is obvious over Kim in view of the Linux
`Publication and the knowledge of POSITA ............................. 52
`Independent claim 25 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 52
`Dependent claim 26 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 54
`Claim 27 is obvious over Kim in view of the Linux
`Publication and the knowledge of POSITA ............................. 55
`10. Dependent claim 29 is obvious over Kim in view of the
`Linux Publication and the knowledge of POSITA .................. 56
`Challenge #7: Claims 4, 5, 24 and 28 are obvious over Kim in
`view of Lin ......................................................................................... 56
`1.
`Kim and Lin render obvious Claims 4, 5, and 28 .................... 56
`2.
`Kim and Lin render obvious Claims 24 ................................... 59
`CONCLUSION ............................................................................................. 60
`
`8.
`
`9.
`
`K.
`
`
`
`V.
`
`
`
`- iii -
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`

`
`Exhibit Number
`
`Description
`
`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`U.S. Patent No. 6,831,865 to Chang et al. (“the ’865
`Patent”)
`
`Prosecution File History For U.S. Patent No.
`6,831,865 to Chang et al.
`
`Declaration of Dr. R. Jacob Baker in Support of
`Petition
`
`U.S. Patent No. 5,341,339 to Wells
`
`U.S. Patent No. 6,151,246 to So
`
`U.S. Patent No. 6,396,744 to Wong
`
`U.S. Patent No. 5,838,614 to Estakhri
`
`Excerpts from Designing with FLASH MEMORY: The
`
`Definitive Guide to Designing Flash Memory
`
`Hardware and Software for Components and
`
`PCMCIA Cards by Brian Dipert & Markus Levy
`
`Annabooks (1993, 1994)
`
`U.S. Patent No. 5,485,595 to Assar
`
`PC Card Standard, Volume 7, Media Storage Formats
`Specification
`
`A Floating Gate and Its Application to Memory
`Devices, D. Kahng and S. M. Sze
`
`New Ultra High Density EPROM and Flash
`EEPROM with NAND Structure Cell, Fujio Masuoka
`et. al.
`
`iv
`
`Ex. 1001
`
`Ex. 1002
`
`Ex. 1003
`
`Ex. 1004
`
`Ex. 1005
`
`Ex. 1006
`
`Ex. 1007
`
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
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`
`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`Toshiba Web at flash25.toshiba.com
`
`U.S. Patent No. 5,418,752 to Harari
`
`U.S. Patent No. 6,362,049 to Cagnina
`
`Intel FDI User Manual
`
`Cleaning Policies in Mobile Computers Using Flash
`Memory, M.-L. Chiang & R.-C. Chang
`
`Managing Flash Memory in Personal Communication
`Devices, Mei-Ling Chiang et. al.
`
`U.S. Patent No. 5,740,395 to Wells
`
`U.S. Patent No. 5,940,861 to Brown
`
`U.S. Patent No. 7,012,835 to Gonzalez
`
`U.S. Publication No. 2003/0046487 to Swaminathan
`
`Intel Series 2 Flash Memory Cards Data Sheet
`
`Curriculum Vitae of Dr. R. Jacob Baker
`
`Declaration of Dr. David Hinds in Support of Petition
`
`SUPPORTED.CARDS file within published pcmcia-
`cs-3.1.21.tar
`
`CHANGES file within published pcmcia-cs-3.1.21.tar
`
`PCMCIA Programmer’s Guide within published
`pcmcia-cs-3.1.21.tar
`
`PCMCIA How-To within published pcmcia-cs-
`3.1.21.tar
`
`ftl.h within published pcmcia-cs-3.1.21.tar
`
`ftl_cs.c within published pcmcia-cs-3.1.21.tar
`
`Ex. 1013
`
`Ex. 1014
`
`Ex. 1015
`
`Ex. 1016
`
`Ex. 1017
`
`Ex. 1018
`
`Ex. 1019
`
`Ex. 1020
`
`Ex. 1021
`
`Ex. 1022
`
`Ex. 1023
`
`Ex. 1024
`
`Ex. 1025
`
`Ex. 1026
`
`Ex. 1027
`
`Ex. 1028
`
`Ex. 1029
`
`Ex. 1030
`
`Ex. 1031
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`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`ftl_check.c within published pcmcia-cs-3.1.21.tar
`
`ftl_format.c within published pcmcia-cs-3.1.21.tar
`
`iflash.h within published pcmcia-cs-3.1.21.tar
`
`iflash2_mtd.c within published pcmcia-cs-3.1.21.tar
`
`iflash2+_mtd.c within published pcmcia-cs-3.1.21.tar
`
`Excerpts from Nonvolatile Semiconductor Memory
`Technology: A Comprehensive Guide to
`Understanding and Using NVSM Devices, by William
`D. Brown and Joe E. Brewer, ed., IEEE Press (1998).
`
`U.S. Patent No. 6,381,176 to Kim
`
`U.S. Patent No. 6,427,186 to Lin
`
`Exhibit A to Joint Claim Construction and Pre-
`Hearing Statement
`
`
`
`Ex. 1032
`
`Ex. 1033
`
`Ex. 1034
`
`Ex. 1035
`
`Ex. 1036
`
`Ex. 1037
`
`Ex. 1038
`
`Ex. 1039
`
`Ex. 1040
`
`
`
`
`
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`vi
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`

`
`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`I. MANDATORY NOTICES
`
`A. Real Party-in-Interest
`Pursuant to 37 C.F.R. § 42.8(b)(1), the real party-in-interest is Apple Inc.
`
`(“Petitioner”).
`
`B. Related Matters
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner states that Longitude Flash
`
`Memory Systems S.A.R.L. (“Patent Owner”) is asserting U.S. Patent 6,831,865
`
`(the “’865 patent”) against the Real Party-In-Interest in a suit filed September 23,
`
`2014, styled Longitude Licensing Ltd., and Longitude Flash Memory Systems
`
`S.A.R.L. v. Apple Inc., Case No. 3:14-cv-4275, pending in the United States
`
`District Court for the Northern District of California (the “Related Litigation”).
`
`Petitioner has filed, or soon will file, petitions for inter partes review of U.S.
`
`Patent Nos. 6,510,488; 6,763,424; 6,968,421; 7,012,835; 7,120,729; 7,224,607;
`
`7,181,611; 7,657,702; 7,818,490; 7,970,987; 8,050,095; and 8,316,177.
`
`As of the filing of this petition, no other judicial or administrative matters
`
`are known to Petitioner that would affect, or be affected by, a decision in an inter
`
`partes review of the ’865 patent.
`
`C. Lead and Back-up Counsel
`Lead counsel for this matter is Brent Yamashita (USPTO Reg. No. 53,808 ),
`
`and back-up counsel for this matter is Edward Sikorski (USPTO Reg. No. 39478),
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`U.S. Patent No. 6,831,865
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`both at the e-mail address: Apple-Longitude-IPR@dlapiper.com. The postal and
`
`hand delivery address for both is DLA Piper LLP (US), 2000 University Avenue,
`
`East Palo Alto, California, 94303, and the telephone and fax numbers are (650)
`
`833-2348 (for phone) and (650) 687-1206 (for fax).
`
`Service Information
`
`D.
`Pursuant to 37 C.F.R. § 42.8(b)(4), papers concerning this matter should be
`
`served on the following email address: Apple-Longitude-IPR@dlapiper.com.
`
`II. GROUNDS FOR STANDING
`
`Pursuant to 37 CFR § 42.104(a), Petitioner certifies that the ’865 patent is
`
`available for inter partes review, and Petitioner is not estopped or barred from
`
`requesting inter partes review challenging the ’865 patent on the grounds
`
`identified in this petition.
`
`III. RELIEF REQUESTED
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis, institute a trial for inter partes review of claims 1-5, 8, 18, and 24-29 of
`
`the ’865 patent, and cancel claims 1-5, 8, 18, and 24-29 as invalid for the reasons
`
`set forth below.
`
`IV. THE REASONS FOR THE REQUESTED RELIEF
`
`The full statement of the reasons for relief requested is as follows:
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`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`A.
`
`Summary of Reasons
`
`
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`
`
`
`
`
`
`
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`
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`Challenge #1: Claims 1-3, 5, 18, and 25-27 of the ’865 patent
`
`are anticipated by U.S. Patent No. 5,485,595 (“Assar”).
`
`Challenge #2: Claims 8, 24, 29 are obvious over Assar in view
`
`of the knowledge of a person of ordinary skill in the art.
`
`Challenge #3: Claims 4, 5, and 28 are rendered obvious by
`
`Assar in view of U.S. Patent No. 5,838,614 (“Estakhri”).
`
`Challenge #4: Claim 18 is anticipated by U.S. Patent No.
`
`6,427,186 to Lin (“Lin”).
`
`Challenge #5: Claim 24 is rendered obvious by Lin in view of
`
`the knowledge of a person of ordinary skill in the art.
`
`Challenge #6: Claims 1-3, 8, 25-27 and 29 of the ’865 patent
`
`are rendered obvious by U.S. Patent No. 6,381,176 to Kim
`
`(“Kim”) alone, or in view of pcmcia-cs-3.1.21.tar (“the Linux
`
`Publication”) and Volume 7, Media Storage Formats
`
`Specification to the PC Card Standard (“PC Card standard”)
`
`
`
`Challenge #7: Claims 4, 5, 24 and 28 are rendered obvious by
`
`Kim in view of the Linux Publication and the PC Card
`
`Standard, and further in view of Lin
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`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`B. Relevant Background Technology
`1. Overview of Flash Memory
`Flash memory is a type of solid state semiconductor non-volatile memory.
`
`These devices are now ubiquitous in consumer electronic devices as data storage
`
`devices, including as a replacement for magnetic disk drives even in desktop
`
`computers. Ex. 1003, Declaration of Dr. Jacob Baker (“Baker Decl.”) at ¶15.
`
`Flash memory typically comprises an array of flash memory cells organized
`
`in rows and columns, as in conventional memory systems (such as DRAM or
`
`SRAM). Ex. 1003 at ¶¶ 24, 32, 33. Each flash memory cell utilizes a floating gate
`
`within a field effect transistor (“FET”) to store electrical charge. Ex. 1003 at ¶ 19.
`
`Shown below is an illustration of a typical flash memory cell with a floating
`
`gate added to a standard FET structure. Ex. 1003 at ¶¶ 20, 21.
`
`
`
`
`
`The amount of electrical charge stored in the floating gate can be used to
`
`represent data bits (“1” or “0”). Ex. 1003 at ¶¶ 21,22. Since the “floating gate” is
`
`electrically insulated from the terminals of the FET, charge cannot readily conduct
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`U.S. Patent No. 6,831,865
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`into or out of the floating gate, which allows long-term storage of the charge even
`
`when power is removed from the device. Ex. 1003 at ¶ 19. However, by applying
`
`a carefully controlled and sufficiently high voltage across the appropriate
`
`terminals, charge can be added to (“programmed”) or removed from (“erased”) the
`
`floating gate. See e.g. Ex. 1008 at 27, 28, 33, 34, 36.
`
`Two common types of flash memory that were already commercially
`
`available by the early 1990s are NOR flash and NAND flash. Ex. 1003 at ¶ 31.
`
`They are so named because of the way that individual cells are electrically
`
`connected to form a memory cell array. In general, NAND flash memory has
`
`higher storage density compared to NOR flash, and are more advantageous in some
`
`storage applications. Id. at ¶¶ 34-35. However, the two types of flash both use the
`
`floating gate FET structure as the individual memory cell for charge storage. Id. at
`
`¶ 31. Accordingly, problems that generally affect floating gate cells (to be
`
`discussed below) are known to affect both NOR- and NAND-type flash devices.
`
`Failure Mechanisms in Flash Memory
`
`2.
`When floating gate cells are used in real-world devices, electrons are moved
`
`back and forth across the floating gate’s oxide region as the memory undergo
`
`numerous program and erase cycles (“P/E cycles”). These operations create stress
`
`on the oxide layer, and eventually cause the oxide to break down. When the oxide
`
`breaks down, the cell short circuits and becomes unusable. Ex. 1008 at 40. This
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`failure mechanism is known as “oxide breakdown.” Ex. 1003 at ¶¶ 36-37. In
`
`addition, electrons migrating through can also become trapped in the oxide layer
`
`due to “electron trapup,” rendering the cell unusable for any practical purposes. Ex.
`
`1003 at ¶ 38. By 2002, both oxide breakdown and electron trapup were well known
`
`to affect all floating gate type memory cells, and were thus extensively studied. Ex.
`
`1037 at 69. See also id. at 130-144. It was well known that both NAND and NOR
`
`flash were susceptible to these failure modes. Ex. 1003 at ¶ 36.
`
`3. Managing Flash Memory Failures
`In real-world devices, given the inevitable failure of these cells, well-
`
`designed flash memory systems must manage such failures accordingly. Indeed, it
`
`was known that some flash memory devices were actually shipped with pre-
`
`existing defects in some of the cells. This is not surprising because real-world
`
`manufacturing processes generally do not yield completely defect-free devices. Ex.
`
`1003 at ¶ 41. In practice, quality control testing may be performed by the
`
`manufacturer at the factory to identify the locations of these defective blocks.
`
`Manufacturers would thereafter program a special data bit pattern into the flash
`
`memory itself in order to identify these defects so that the users of the product
`
`could avoid trying to program into these defective blocks. Ex. 1003 at ¶ 43.
`
`In addition to managing these manufacturing defects, techniques were also
`
`developed to manage defects that develop during normal usage (e.g. due to oxide
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`U.S. Patent No. 6,831,865
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`breakdown or electron trapup). Known commercial implementations of flash
`
`memory devices at the time generally verify the nominal program/erase operations
`
`to ensure the program or erase operation succeeded. If the verification fails after
`
`exceeding a set time limit, the cells are recognized by the system as “bad.” Ex.
`
`1008 at 41, 140-143, 154. By tagging the cells as “bad,” the memory system can
`
`avoid reusing these defective cells. Ex. 1003 at ¶ 39.
`
`To mitigate these failures that result from normal use, it is important to
`
`equalize as much as possible the programming and erasing activity across all
`
`memory cells in the flash array so that certain memory cells do not fail prematurely
`
`from excessive concentrated use. This process is known as “wear leveling,” and
`
`was already well known and commonplace by 2002. Ex. 1008 at 263-265. Ex.
`
`1003 at ¶¶ 44-46. This often involved copying data from one block (the “source”
`
`block) to another block (the “destination” block) to balance the usage among the
`
`blocks. Ex. 1003 at ¶¶ 45-46. Balancing usage generally involved some
`
`comparison of the erase counts between the erase blocks in the device. Ex. 1003 at
`
`¶¶ 44-46. Therefore, it was widely known to preserve and keep track of erase count
`
`information for memory blocks in erasable flash memory. Ex. 1003 at ¶ 46.
`
`4. Organization of Data and Metadata Within Flash Memory
`Digital data comprises a string of 1’s and 0’s, and therefore, data stored in
`
`such storage media must be done in an organized manner (e.g. a “storage format”)
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`U.S. Patent No. 6,831,865
`Petition For Inter Partes Review
`
`so that they can be retrieved and parsed in a meaningful way. This is not unique to
`
`flash memory media, and for example, in magnetic disk drives, it was well known
`
`to structure the stored data in an appropriate format (e.g. by using the file
`
`allocation table “FAT” for DOS operating systems). The significance of data
`
`structures in general can be readily appreciated by recalling that in the early 1990s
`
`a DOS (or Windows) formatted disk was incompatible with Macintosh computers.
`
`The entire disk is essentially inaccessible and useless under the wrong format.
`
`By extension, it was also well known to maintain data structures about the
`
`flash memory array itself, like the locations of free blocks and any defective
`
`blocks. (“Whatever the type of flash file system, there will be varying amounts of
`
`data structures stored on the flash memory in addition to the user’s data.”). See Ex.
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`1008 at 269-70. Other important flash media parameters such as memory capacity,
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`block and sector sizes and configurations, as well as other operational parameters
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`and media management metadata discussed above such as erase counts and defect
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`mappings, etc., likewise were organized in data structures within the flash memory
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`itself so they can be retrieved. Ex. 1003 at ¶ 65.
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`In order to facilitate use of flash memory in computer systems as a modular
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`replacement of traditional hard disk drives, methods were developed to provide an
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`additional layer of software between the physical flash memory and the computer
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`systems that would control the memory. See Ex. 1010 at 1. This layer could
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`essentially allow the host system to interact with both traditional hard disk drives
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`and flash memory using the same set of commands without having to
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`accommodate for the unique requirements of flash at the system level. See Ex.
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`1010 at 1. As even a layperson can appreciate from the Macintosh vs. DOS disk
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`format example above, a standardized data structure format would ensure the
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`greatest compatibility across devices and host systems. See Ex. 1008 at 276-277.
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`The result of one such standardization effort occurred in the early 1990s within an
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`industry group known as the Personal Computer Memory Card International
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`Association (PCMCIA).
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`5. Overview of the PCMCIA Standard : FTL Specification
`The PCMCIA formed in early 1990 to standardize specifications for
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`peripheral cards (which became known as PCMCIA Cards, also commonly
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`referred to as PC Cards). The PCMCIA consisted of several hundred companies
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`that developed and maintained standards for these devices, and the first version
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`(PCMCIA 1.0) was published in 1990. The standard is comprehensive, and
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`specifies many aspects of these peripheral cards such as physical dimensions,
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`electrical connections and other such characteristics to ensure compatibility. This
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`effort allowed users to connect a wide variety of peripheral cards such as network
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`cards, modems, and flash memory cards, to their personal computers. See, e.g., Ex.
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`1008 at 187-189, 276-277.
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`Of specific relevance to flash memory, the PCMCIA also approved the Flash
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`Translation Layer (FTL) specification around 1994, which became a heavily-used
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`interface between the file system and the storage media. Persons of ordinary skill
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`in the art would have been generally familiar with the concepts and terminologies
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`used in this standard. Ex. 1003 at ¶73. Exhibit 1010 is the Media Storage Formats
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`Specification (Volume 7) from the PC Card Standard Release 7.0 (1999), referred
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`to herein as the “PC Card Standard.”
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`The PC Card Standard establishes a data format for PC Cards that allows
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`those cards to be used on different host systems, emulating a traditional block
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`device. Ex. 1010 at 1, 24. In order to manage data blocks, FTL organizes the
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`memory into “partitions” (a concept that is similar to traditional hard disks)
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`comprising multiple “erase units,” i.e. the smallest unit of flash memory that can
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`be individually erased (referred to as “blocks” in the ’865 patent). Ex. 1003 at ¶70.
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`FTL keeps track of certain data about a given partition by including an Erase Unit
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`Header (EUH) and a Block Allocation Map (BAM) in each erase unit. See, e.g.,
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`Ex. 1010 at 27. The formatted partition “uses a well-defined header to allow
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`directory functions and file access to be performed across a wide variety of
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`operating environments and host platforms.” Id. at 19.
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`The header is important as it maintains global information about the partition
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`in which the erase unit belongs. “The Erase Unit Header contains information
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`specific to the Erase Unit and global information about the entire FTL partition.”
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`Ex. 1010 at 34. It includes information such as the size of the erase unit, the
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`number of erase units in the partition, and the formatted size of the partition. Id. at
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`34-37. Skilled artisans recognized the importance of such global information
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`within this header, as it is redundantly stored in every erase unit within the
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`partition, allowing the system to readily locate any EUH, and thus retrieve the
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`“self-management” information about the flash memory partition. Id. at 34, 38.
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`The standard also specifies a Block Allocation Map (BAM), adjacent to the
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`EUH header. The BAM is a sequence of 4-byte values (called Block Allocation
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`Information, or BAI) each of which tracks a corresponding block in the data erase
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`unit using a virtual address. Ex. 1010 at 28-30. The BAM may hold information
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`about “bad” blocks on the memory, as shown in the figures reproduced from Ex.
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`1010, with annotations added below:
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`Ex. 1010 at Figure 5-3 (excerpt, red lines added), 29.
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`It is unsurprising that the PC Card standard expressly contemplates
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`including means for managing bad blocks or areas within the flash memory, given
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`the prevalence of defects as explained above.
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`6. Overview of the ’865 Patent
`The ’865 patent, titled “Maintaining Erase Counts in Non-Volatile Storage
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`Systems,” was filed October 28, 2002 and issued December 14, 2004 to inventors
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`Robert C. Chang, Bahman Qwami, and Farshid Sabet-Sharghi. Ex. 1001.
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`The ’865 patent generally discloses a
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`system that facilitates performing of wear
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`leveling operations in a flash memory storage
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`system. See id. at 3:19-26. The ’865 patent
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`describes a wear leveling operation based on
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`“a counter which keeps track of how many
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`times a block has been erased may be
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`maintained an incremented each time the
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`block is erased,” i.e. erase counts. Id. at 9:39-42. Of relevance to the challenged
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`claims, the ’865 patent discloses to store erase counts and other information about
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`the blocks in the non-volatile memory, such as indications that certain blocks are
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`unusable due to factory defects or growing defects. Id. at 3:57-60. Information
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`may be stored in tables or arrays, or in an exemplary embodiment, an “erase count
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`block” (“ECB”). Id. at 3:29-31, 5:52-6:9, Figs. 8a-d. The ECB is depicted in Fig.
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`8a, reproduced on the right:
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`The ’865 patent generally discloses wear leveling operations that utilize the
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`stored erase count information. For example, a data block may be identified and
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`exchanged (or “swapped”) with one of the least frequently erased blocks based on
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`information stored in the table. Id. at 15:55-16:11 and at Fig. 6. However, none of
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`the claims are specifically directed to the actual wear leveling operation or
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`algorithm, and the claims simply require these various indicators be stored in
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`memory.
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`C. Level of Ordinary Skill in the Art
`A person of ordinary skill in the art (“POSITA”) is a hypothetical person
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`who is presumed to have known the relevant art at the time of the alleged
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`invention. Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc., 807 F.2d 955, 962
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`(Fed. Cir. 1986). Petitioner submits that a person of ordinary skill in the art
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`(“POSITA”) at the time of the ’865 patent would have a Bachelor of Science
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`degree in electrical engineering, computer science, computer engineering, or
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`related field, and at least two years of experience working in the field of
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`semiconductor memory design, or equivalent. Ex. 1003 at ¶ 77.
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`D. Claim Construction under 37 C.F.R. § 42.104(b)(3)
`Pursuant to 37 C.F.R. §§ 42.100(b) and 42.204(b)(2), this petition presents
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`claim analysis construing claim language such that it is “given its broadest
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`reasonable construction in light of the specification of the patent in which it
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`appears.” Proposed claim constructions contained below are presented using the
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`broadest reasonable interpretation standard, which is applied solely for the
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`purposes of inter partes review. Because the standard for claim construction at the
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`PTO is different than that used in litigation, see In re Am. Acad. of Sci. Tech Ctr.,
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`367 F.3d 1359, 1364, 1369 (Fed. Cir. 2004); MPEP § 2111, Petitioner expressly
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`reserves the right to argue in litigation constructions for any term in the ’865
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`patent, as appropriate to that proceeding. Petitioner further notes that in the Related
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`Litigation, Pa